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CN115395890B - Temperature compensation RC oscillator circuit and application chip thereof - Google Patents

Temperature compensation RC oscillator circuit and application chip thereof Download PDF

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Publication number
CN115395890B
CN115395890B CN202211123848.4A CN202211123848A CN115395890B CN 115395890 B CN115395890 B CN 115395890B CN 202211123848 A CN202211123848 A CN 202211123848A CN 115395890 B CN115395890 B CN 115395890B
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China
Prior art keywords
pmos tube
tube
nmos
gate
pmos
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CN115395890A (en
Inventor
邱鼎
郭春炳
肖亦成
林鑫
张春华
严家树
简明朝
孔祥键
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Guangdong University of Technology
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Guangdong University of Technology
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
    • H03B5/00—Generation of oscillations using amplifier with regenerative feedback from output to input
    • H03B5/02—Details
    • H03B5/04—Modifications of generator to compensate for variations in physical values, e.g. power supply, load, temperature
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
    • H03B5/00—Generation of oscillations using amplifier with regenerative feedback from output to input
    • H03B5/08—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance
    • H03B5/12—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device
    • H03B5/1206—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device using multiple transistors for amplification
    • H03B5/1218—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device using multiple transistors for amplification the generator being of the balanced type
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
    • H03B5/00—Generation of oscillations using amplifier with regenerative feedback from output to input
    • H03B5/08—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance
    • H03B5/12—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device
    • H03B5/1228—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device the amplifier comprising one or more field effect transistors

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  • Oscillators With Electromechanical Resonators (AREA)
  • Inductance-Capacitance Distribution Constants And Capacitance-Resistance Oscillators (AREA)
  • Logic Circuits (AREA)

Abstract

The invention provides a temperature compensation RC oscillator circuit and an application chip thereof, which relate to the technical field of analog integrated circuits and solve the problem that in the current temperature sensing oscillator, the current of the oscillator circuit is influenced by temperature change and cannot guarantee the stability of oscillation frequency.

Description

Temperature compensation RC oscillator circuit and application chip thereof
Technical Field
The invention relates to the technical field of analog integrated circuits, in particular to a temperature compensation RC oscillator circuit and an application chip thereof.
Background
With the continuous development of the fields of communication, internet of things, sensors and the like, the requirements of system on chip (System on Circuits, soC) chips are increasingly high, and the development of the system on chip (System on Circuits, soC) chips is promoted to be lower in cost, lower in power consumption and more stable. The SoC is provided with a stable and reliable high-precision clock module, and in the SoC, the original off-chip oscillating circuit is integrated in an on-chip manner, so that the goals of greatly reducing cost, reducing power consumption and the like can be achieved, and an on-chip integratable clock source becomes the best choice. The RC oscillator is an oscillator formed by a resistor and a capacitor, and is widely applied to an on-chip clock generation circuit due to the advantages of simple structure, low cost, easiness in integration and the like.
In practical applications, the output frequency of the RC oscillator is affected by the process, temperature and power supply voltage variations, so that it is not possible to achieve high enough precision, although the performance of the on-chip clock source can meet the normal operation of the system under most low-cost and low-power application environments, such as a bio-transplantation chip and an intelligent home control chip, the on-chip clock source cannot be balanced to achieve the integration and frequency precision, and the on-chip integrated clock source provides a good solution to the above problems, so that it is important to design an RC oscillator with high frequency stability, and especially to maintain a signal with stable output frequency under the condition of temperature variation.
The prior art discloses a temperature sensing oscillator, firstly, the influence of offset voltage of a comparator is eliminated by alternately charging a capacitor C1 and a capacitor C2 in one clock period, then the whole working temperature range is divided into a plurality of small temperature intervals, a plurality of selectable resistor branches are formed by proportioning positive temperature coefficient resistors and negative temperature coefficient resistors according to proper proportion in each small temperature interval, meanwhile, a temperature sensing circuit is adopted to sense the current temperature and start the resistor branch corresponding to the temperature interval, and finally, the influence of temperature on the current is reduced by changing the size of the resistor, but the charge and discharge current of a capacitor polar plate of the oscillator has high sensitivity to temperature change, the current is still influenced by the temperature change, so that the charge and discharge time is difficult to control, and the stability of the oscillation frequency cannot be ensured.
Disclosure of Invention
In order to solve the problem that in the current temperature sensing oscillator, the current of the oscillator circuit is influenced by temperature change and the stability of the oscillating frequency cannot be ensured, the invention provides a temperature compensation RC oscillator circuit, which reduces the influence of the temperature change on the current of the oscillator circuit and ensures the stability of the oscillating frequency.
A temperature compensated RC oscillator circuit comprising: the RC oscillator core circuit and the current-mode summing band-gap reference circuit generate a negative temperature coefficient current and a positive temperature coefficient current, and the negative temperature coefficient current and the positive temperature coefficient current are superposed to form a temperature stabilizing current to be used as a charging current of the RC oscillator core circuit.
In the technical scheme, the temperature compensation RC oscillator circuit comprises an RC oscillator core circuit and a current mode summation band gap reference circuit, and then the current mode summation band gap reference circuit is utilized to generate negative temperature coefficient current and positive temperature coefficient current, the sum of the temperature coefficient current and the positive temperature coefficient current is temperature stabilization current, the temperature stabilization current has low sensitivity to temperature change and is not easily influenced by the temperature change, the temperature stabilization current is used as charging current of the RC oscillator core circuit, the defect that charging and discharging time of the RC oscillator core circuit is difficult to control is avoided, the oscillation frequency of periodic signals output by the RC oscillator core circuit has high robustness to the temperature change, the influence of the temperature change on the current of the oscillator circuit is reduced, and the stability of the oscillation frequency is ensured.
Preferably, the RC oscillator core circuit includes a first NAND gate NAND 1 Second NAND gate NAND 2 A first capacitance control unit, a second capacitance control unit, a first inverter INV 1 Second inverter INV 2 First transmission gate TG 1 Second transmission gate TG 2 First PMOS tube Mp 1 Second PMOS tube Mp 2 MP of the third PMOS tube 3 MP of fourth PMOS tube 4 Fifth PMOS tube Mp 5 First push-pull comparator CAMP 1 Second push-pull comparator CAMP 2 First NMOS tube Mn 1 Second NMOS tube Mn 2 A first resistor R 2，1 A second resistor R 2，2 And a third resistor R 0 ；
First NAND gate NAND 1 A first input end of the first push-pull comparator is connected with 1 Is an output end of a first NAND gate NAND 1 Is connected to the oscillator enable terminal OSC_EN, the first NAND gate 1 A third input end of (2) is connected with the second NAND gate NAND 2 Is an output end of a first NAND gate NAND 1 The output ends of the (A) are respectively connected with the first NMOS tube Mn 1 Gate of (a) first PMOS tube Mp 1 Gate of (a), first transmission gate TG 1 Low level control bit of (a) and first inverter INV 1 Is provided; first NMOS tube Mn 1 Is a source of (a)The electrode is grounded; first PMOS tube Mp 1 The source electrode of the (E) is connected with a third PMOS tube MP 3 Drain electrode of the first PMOS tube Mp 1 The drain electrode of (a) is connected with the first resistor R 2，1 Is a first resistor R 2，1 The other end of the first capacitor is connected with a first capacitor control unit; first inverter INV 1 The output end is connected with the first transmission gate TG 1 High level control bit of (1), first transmission gate TG 1 The input ends of the first NMOS tube Mn are respectively connected with 1 Drain of (c) and first push-pull comparator CAMP 1 Is connected with the negative input end of the circuit board;
second NAND gate NAND 2 A first input end of the second push-pull comparator is connected with 2 Is an output end of a second NAND gate NAND 2 A second NAND gate connected to the second input terminal of the oscillator enable terminal OSC_EN 2 A third input end of (a) is connected with the first NAND gate NAND 1 Is an output end of a second NAND gate NAND 2 The output ends of the (A) are respectively connected with a second NMOS tube Mn 2 Gate of (2), second PMOS tube Mp 2 Gate of (2), second transmission gate TG 2 Low level control bit of (2) and second inverter INV 2 Is provided; second NMOS tube Mn 2 The source electrode of the second PMOS tube MP is grounded 2 The source electrode of the (E) is connected with the fourth PMOS tube MP 4 Drain electrode of the fourth PMOS tube Mp 4 The drain electrode of (a) is connected with the second resistor R 2，2 One end of (2) a second resistor R 2，2 The other end of the first capacitor is connected with a second capacitor control unit; second inverter INV 2 The output end is connected with the second transmission gate TG 2 High level control bit of (1), second transmission gate TG 2 The input ends of the second NMOS tube Mn are respectively connected with 2 Drain of (c) and second push-pull comparator CAMP 2 Is connected with the negative input end of the circuit board;
first push-pull comparator CAMP 1 The positive input ends of (1) are respectively connected with a third resistor R 0 Is arranged at one end of the fifth PMOS tube Mp 5 Drain electrode of the second push-pull comparator CAMP 2 The positive input ends of (1) are respectively connected with a third resistor R 0 One end of the fifth PMOS tube Mp 5 Drain of (c) and first push-pull comparator CAMP 1 A positive input terminal of (2), a third resistor R 0 The other end of the third PMOS tube Mp 3 Is a source of (a)Pole, fourth PMOS tube Mp 4 Source electrode of (C) and fifth PMOS tube Mp 5 The source electrodes of the third PMOS tube Mp are commonly connected with the power input end VDD 3 Grid electrode of the (C) PMOS tube Mp 4 Gate of (c) and fifth PMOS tube Mp 5 The gates of the voltage source circuit are connected with the grid electrode of the current mode summation band gap reference circuit;
first NAND gate NAND 1 And a second NAND gate NAND 2 The output signal of (a) is a square wave signal with opposite phase.
Preferably, the first capacitance control unit includes a first capacitance C 2,1 A second capacitor C 1,1 Third capacitor C 0,1 Third NMOS tube Mn 3 Fourth NMOS tube Mn 4 And a fifth NMOS tube Mn 5 First capacitor C 2,1 One end polar plate of (C) a second capacitor 1,1 And a third capacitor C 0,1 One end polar plate of the first PMOS tube Mp is commonly connected with 1 Drain electrode of (C), first capacitor C 2,1 The other end polar plate of the (B) is connected with a third NMOS tube Mn 3 Drain electrode of the third NMOS transistor Mn 3 The grid electrode of the first BIT2 is connected with the source electrode of the first BIT; second capacitor C 1,1 The other end polar plate of the (B) is connected with a fourth NMOS tube Mn 4 Drain electrode of the fourth NMOS transistor Mn 4 The gate of the second NMOS transistor is connected with the second BIT1, the fourth NMOS transistor Mn 4 The source electrode of the transistor is grounded; third capacitor C 0,1 The other end polar plate of the (B) is connected with a fifth NMOS tube Mn 5 Drain electrode of fifth NMOS transistor Mn 5 The gate of (2) is connected to BIT0 of the third BIT and the source is grounded.
Preferably, the second capacitance control unit includes a fourth capacitance C 2,2 Fifth capacitor C 1,2 Sixth capacitor C 0,2 Mn of sixth NMOS tube 6 Seventh NMOS tube Mn 7 And an eighth NMOS transistor Mn 8 Fourth capacitor C 2,2 Fifth capacitor C 1,2 And a sixth capacitance C 0,2 One end polar plate of the first PMOS tube is commonly connected with the second PMOS tube Mp 2 Drain electrode of (C), fourth capacitor C 2,2 The other end polar plate of the (B) is connected with a sixth NMOS tube Mn 6 Drain electrode of the sixth NMOS transistor Mn 6 The grid electrode of the first BIT2 is connected with the source electrode of the first BIT; fifth capacitor C 1,2 The other end polar plate of (C) is connected with a seventh NMOS tube Mn 7 Drain electrode of the seventh NMOS transistor Mn 7 The grid electrode of the first BIT is connected with the second BIT1, and the source electrode is grounded; sixth capacitor C 0,2 The other end polar plate of the (B) is connected with an eighth NMOS tube Mn 8 Drain electrode of eighth NMOS transistor Mn 8 The gate of (2) is connected to BIT0 of the third BIT and the source is grounded.
Preferably, the first push-pull comparator CAMP 1 And a second push-pull comparator CAMP 2 Push-pull comparator circuits are arranged in the two transistors, and each push-pull comparator circuit comprises a sixth PMOS tube Mp 6 Seventh PMOS tube Mp 7 Eighth PMOS tube Mp 8 Ninth PMOS tube Mp 9 Tenth PMOS tube Mp 10 Eleventh PMOS tube Mp 11 Twelfth PMOS tube Mp 12 Ninth NMOS tube Mn 9 Tenth NMOS tube Mn 10 Eleventh NMOS tube Mn 11 Twelfth NMOS transistor Mn 12 Thirteenth NMOS tube Mn 13 Fourteenth NMOS tube Mn 14 And a fifteenth NMOS transistor Mn 15 The method comprises the steps of carrying out a first treatment on the surface of the The sixth PMOS tube Mp 6 Seventh PMOS tube Mp 7 Eighth PMOS tube Mp 8 And a ninth PMOS tube Mp 9 The source electrode of the power supply is connected with the power supply input end VDD; the sixth PMOS tube Mp 6 The grid electrodes of the P-channel metal oxide semiconductor (PMOS) transistors are respectively connected with a seventh PMOS tube Mp 7 Grid electrode of (C) and seventh PMOS tube Mp 7 Drain electrode of (d), ninth NMOS transistor Mn 9 Drain electrode of (d) and twelfth NMOS transistor Mn 12 A drain electrode of (2); the ninth PMOS tube Mp 9 The grid electrodes of the P-channel metal oxide semiconductor (PMOS) transistors are respectively connected with an eighth P-channel metal oxide semiconductor (MP) 8 Grid electrode of (V) and eighth PMOS tube Mp 8 Drain electrode of (c) and tenth NMOS transistor Mn 10 A drain electrode of (2); the ninth NMOS tube Mn 9 And a tenth NMOS transistor Mn 10 Is commonly connected with an eleventh NMOS tube Mn 11 Drain electrode of the eleventh NMOS transistor Mn 11 The source electrode of (1) is grounded, the gate electrode is connected to the first bias voltage Vb 1 The method comprises the steps of carrying out a first treatment on the surface of the The tenth PMOS tube Mp 10 The source electrode of (2) is connected with the power input end VDD, and the gate electrode is connected with the second bias voltage Vb 2 Drain electrodes are respectively connected with an eleventh PMOS tube Mp 11 And a twelfth PMOS tube Mp 12 A source of (a); the eleventh PMOS tube Mp 11 And a ninth NMOS transistor Mn 9 The gates of (a) are commonly connected to the VIN _ N terminal,twelfth PMOS tube Mp 12 And a tenth NMOS transistor Mn 10 The grid electrode of the first transistor is commonly connected with the VIN_P end; the eleventh PMOS tube Mp 11 The drain electrodes of the N-channel metal oxide semiconductor (NMOS) transistors are respectively connected with a twelfth NMOS transistor Mn 12 Gate electrode of thirteenth NMOS transistor Mn 13 Gate of (c) and thirteenth NMOS transistor Mn 13 Drain electrode of the twelfth PMOS tube Mp 12 The drain electrodes of the N-channel metal oxide semiconductor (NMOS) transistors are respectively connected with a fifteenth NMOS transistor Mn 15 Gate of (d), fourteenth NMOS transistor Mn 14 Gate of (d), fourteenth NMOS transistor Mn 14 Drain electrode of (C) and sixth PMOS tube Mp 6 A drain electrode of (2); the fifteenth NMOS tube Mn 15 Drain electrode of (C) and ninth PMOS tube Mp 9 The drain electrodes of the first and second transistors are commonly connected with the VOUT terminal; the twelfth NMOS transistor Mn 12 Thirteenth NMOS tube Mn 13 Fourteenth NMOS tube Mn 14 And a fifteenth NMOS transistor Mn 15 The source of (c) is grounded.
Preferably, the current-mode summing bandgap reference circuit includes a thirteenth PMOS tube Mp 13 Fourteenth PMOS tube Mp 14 Fifteenth PMOS tube Mp 15 Sixteenth PMOS tube Mp 16 Seventeenth PMOS tube Mp 17 Eighteenth PMOS tube Mp 18 Seventh capacitor C m Fourth resistor R 1,1 Fifth resistor R 3 Sixth resistor R 1,2 Seventh resistor R Z BJT of first BJT tube 1 BJT of second BJT tube 2 Sixteenth NMOS tube Mn 16 Seventeenth NMOS tube Mn 17 And an eighteenth NMOS tube Mn 18 The method comprises the steps of carrying out a first treatment on the surface of the The thirteenth PMOS tube Mp 13 Fourteenth PMOS tube Mp 14 Fifteenth PMOS tube Mp 15 And a sixteenth PMOS tube Mp 16 The sources of the power supply voltage source are commonly connected with a power supply input end VDD; the thirteenth PMOS tube Mp 13 The drains of the transistors are respectively connected with a fourth resistor R 1,1 Is connected with the first BJT tube BJT 1 Emitter of seventeenth PMOS tube Mp 17 Gate of (d), fourth resistor R 1,1 Is grounded at the other end of the first BJT tube BJT 1 The base and the collector of the transistor are grounded, and the thirteenth PMOS transistor Mp 13 The grid electrodes of the first PMOS tube are respectively connected with a third PMOS tube Mp 3 Grid electrode of the (C) PMOS tube Mp 4 Grid electrode of (C) and fifth PMOS tube Mp 5 Gate of fourteenth PMOS tube Mp 14 A grid electrode,Sixteenth PMOS tube Mp 16 Drain electrode of (d), seventh resistor R Z One end of (2) and an eighteenth NMOS tube Mn 18 A drain electrode of (2); the fourteenth PMOS tube Mp 14 The drain electrodes of the first and second transistors are respectively connected with an eighteenth PMOS tube Mp 18 Gate of (d), fifth resistor R 3 And a sixth resistor R 1,2 A fifth resistor R 3 The other end of the second BJT tube is connected with the BJT 2 Emitter of the second BJT tube BJT 2 The base and collector of (2) are grounded, a sixth resistor R 1,2 The other end of the first electrode is grounded; the fifteenth PMOS tube Mp 15 The drain electrodes of the first and the second PMOS tubes are respectively connected with a seventeenth PMOS tube Mp 17 And an eighteenth PMOS tube Mp 18 A fifteenth PMOS tube Mp 15 Is connected with a sixteenth PMOS tube Mp 16 A seventeenth PMOS tube Mp 17 The drain electrodes of the N-channel metal oxide semiconductor (NMOS) transistors are respectively connected with a sixteenth NMOS transistor Mn 16 Drain electrode of sixteenth NMOS transistor Mn 16 Gate of (c) and seventeenth NMOS transistor Mn 17 Gate electrode of eighteenth PMOS tube Mp 18 The drains of the capacitors are respectively connected with a seventh capacitor C m One end polar plate and seventeenth NMOS tube Mn 17 Drain electrode of (c) and eighteenth NMOS transistor Mn 18 Gate of (C), seventh capacitor C m The other end polar plate is connected with a seventh resistor R Z Is the other end of the sixteenth NMOS tube Mn 16 Seventeenth NMOS tube Mn 17 And an eighteenth NMOS tube Mn 18 The source of (c) is grounded.
Preferably, the first BJT tube BJT 1 Emitter voltage of (1) and second BJT tube BJT 2 Is equal.
Preferably, the circuit also comprises a bias circuit, wherein the bias circuit comprises a nineteenth PMOS tube Mp 19 And a bias current source, nineteenth PMOS tube Mp 19 The source electrode of the (B) is connected with the power input end VDD, and the bias current sources are respectively connected with the fifteenth PMOS tube Mp 15 Grid electrode of sixteenth PMOS tube Mp 16 Gate of nineteenth PMOS tube Mp 19 Is connected to the gate and drain of the transistor.
Preferably, the application chip is provided with a temperature compensated RC oscillator circuit as claimed in any one of claims 1 to 9.
Compared with the prior art, the technical scheme of the invention has the beneficial effects that:
The invention provides a temperature compensation RC oscillator circuit and an application chip thereof, wherein the temperature compensation RC oscillator circuit comprises an RC oscillator core circuit and a current mode summation band gap reference circuit, and then the current mode summation band gap reference circuit is utilized to generate negative temperature coefficient current and positive temperature coefficient current, the sum of the temperature coefficient current and the positive temperature coefficient current is temperature stable current, the temperature stable current has low sensitivity to temperature change and is not easily influenced by the temperature change, the temperature stable current is used as charging current of the RC oscillator core circuit, the defect that the charging and discharging time of the RC oscillator core circuit is difficult to control is avoided, the oscillation frequency of a periodic signal output by the RC oscillator core circuit has high robustness to the temperature change, the influence of the current of the oscillator circuit on the temperature change is reduced, and the stability of the oscillation frequency is ensured.
Drawings
FIG. 1 shows a circuit diagram of a temperature compensated RC oscillator circuit according to an embodiment of the present invention;
FIG. 2 is a waveform diagram of an output signal of an oscillator circuit according to an embodiment of the present invention;
FIG. 3 shows a graph of output frequency simulation results for a temperature change from-40 degrees Celsius to 120 degrees Celsius;
FIG. 4 is a graph showing the results of duty cycle simulation of the output signal of the oscillator circuit;
FIG. 5 is a graph showing the results of frequency simulation of the output signal of the oscillator circuit;
FIG. 6 is a graph showing the results of current simulation in the operating state of an oscillator circuit;
FIG. 7 shows an overall circuit layout of an oscillator;
FIG. 8 shows a circuit diagram of a push-pull comparator;
an RC oscillator core circuit; 11. a first capacitance control unit; 12. a second capacitance control unit; 2. a current-mode summing bandgap reference circuit; 3. and a bias circuit.
Detailed Description
The drawings are for illustrative purposes only and are not to be construed as limiting the present patent;
for better illustrating the present embodiment, some parts of the drawings may be omitted, enlarged or reduced, and do not represent actual dimensions, and the description of the directions of the parts such as "up" and "down" is not limiting of the present patent;
it will be appreciated by those skilled in the art that some well known descriptions in the figures may be omitted;
the positional relationship depicted in the drawings is for illustrative purposes only and is not to be construed as limiting the present patent;
the technical scheme of the invention is further described below with reference to the accompanying drawings and examples.
Example 1
As shown in fig. 1, a temperature compensated RC oscillator circuit, comprising: the RC oscillator comprises an RC oscillator core circuit 1 and a current-mode summing band-gap reference circuit 2, wherein the current-mode summing band-gap reference circuit 2 generates a negative temperature coefficient current and a positive temperature coefficient current, and the negative temperature coefficient current and the positive temperature coefficient current are overlapped to form a temperature stabilizing current to be used as a charging current of the RC oscillator core circuit 1; the temperature compensation RC oscillator circuit comprises an RC oscillator core circuit and a current mode summation band gap reference circuit, and then the current mode summation band gap reference circuit is utilized to generate negative temperature coefficient current and positive temperature coefficient current, the sum of the temperature coefficient current and the positive temperature coefficient current is temperature stabilization current, the temperature stabilization current has low sensitivity to temperature variation and is not easily influenced by the temperature variation, the temperature stabilization current is used as charging current of the RC oscillator core circuit, the defect that the charging and discharging time of the RC oscillator core circuit is difficult to control is avoided, the oscillation frequency of periodic signals output by the RC oscillator core circuit has high robustness to the temperature variation, the influence of the temperature variation on the current of the oscillator circuit is reduced, the stability of the oscillation frequency is ensured, and the temperature compensation RC oscillator circuit is arranged on an application chip and is suitable for the requirements of low power consumption and quick response of various application scenes of the Internet of things.
The RC oscillatorThe core circuit 1 includes a first NAND gate NAND 1 Second NAND gate NAND 2 A first capacitance control unit 11, a second capacitance control unit 12, a first inverter INV 1 Second inverter INV 2 First transmission gate TG 1 Second transmission gate TG 2 First PMOS tube Mp 1 Second PMOS tube Mp 2 MP of the third PMOS tube 3 MP of fourth PMOS tube 4 Fifth PMOS tube Mp 5 First push-pull comparator CAMP 1 Second push-pull comparator CAMP 2 First NMOS tube Mn 1 Second NMOS tube Mn 2 A first resistor R 2，1 A second resistor R 2，2 And a third resistor R 0 ；
First NAND gate NAND 1 A first input end of the first push-pull comparator is connected with 1 Is an output end of a first NAND gate NAND 1 Is connected to the oscillator enable terminal OSC_EN, the first NAND gate 1 A third input end of (2) is connected with the second NAND gate NAND 2 Is an output end of a first NAND gate NAND 1 The output ends of the (A) are respectively connected with the first NMOS tube Mn 1 Gate of (a) first PMOS tube Mp 1 Gate of (a), first transmission gate TG 1 Low level control bit of (a) and first inverter INV 1 Is provided; first NMOS tube Mn 1 The source electrode of the transistor is grounded; first PMOS tube Mp 1 The source electrode of the (E) is connected with a third PMOS tube MP 3 Drain electrode of the first PMOS tube Mp 1 The drain electrode of (a) is connected with the first resistor R 2，1 Is a first resistor R 2，1 The other end of the first capacitor control unit 11 is connected; first inverter INV 1 The output end is connected with the first transmission gate TG 1 High level control bit of (1), first transmission gate TG 1 The input ends of the first NMOS tube Mn are respectively connected with 1 Drain of (c) and first push-pull comparator CAMP 1 Is connected with the negative input end of the circuit board;
second NAND gate NAND 2 A first input end of the second push-pull comparator is connected with 2 Is an output end of a second NAND gate NAND 2 A second NAND gate connected to the second input terminal of the oscillator enable terminal OSC_EN 2 The third input end of (2) is connected with the first and secondNOT NAND 1 Is an output end of a second NAND gate NAND 2 The output ends of the (A) are respectively connected with a second NMOS tube Mn 2 Gate of (2), second PMOS tube Mp 2 Gate of (2), second transmission gate TG 2 Low level control bit of (2) and second inverter INV 2 Is provided; second NMOS tube Mn 2 The source electrode of the second PMOS tube MP is grounded 2 The source electrode of the (E) is connected with the fourth PMOS tube MP 4 Drain electrode of the fourth PMOS tube Mp 4 The drain electrode of (a) is connected with the second resistor R 2，2 One end of (2) a second resistor R 2，2 The other end of the first capacitor is connected with a second capacitor control unit 12; second inverter INV 2 The output end is connected with the second transmission gate TG 2 High level control bit of (1), second transmission gate TG 2 The input ends of the second NMOS tube Mn are respectively connected with 2 Drain of (c) and second push-pull comparator CAMP 2 Is connected with the negative input end of the circuit board;
first push-pull comparator CAMP 1 The positive input ends of (1) are respectively connected with a third resistor R 0 Is arranged at one end of the fifth PMOS tube Mp 5 Drain electrode of the second push-pull comparator CAMP 2 The positive input ends of (1) are respectively connected with a third resistor R 0 One end of the fifth PMOS tube Mp 5 Drain of (c) and first push-pull comparator CAMP 1 A positive input terminal of (2), a third resistor R 0 The other end of the third PMOS tube Mp 3 Source electrode of the fourth PMOS tube Mp 4 Source electrode of (C) and fifth PMOS tube Mp 5 The source electrodes of the third PMOS tube Mp are commonly connected with the power input end VDD 3 Grid electrode of the (C) PMOS tube Mp 4 Gate of (c) and fifth PMOS tube Mp 5 Is connected with the grid electrode of the current mode summation band gap reference circuit 2;
referring to FIG. 2, a first NAND gate NAND 1 And a second NAND gate NAND 2 The output signal of (a) is a square wave signal with opposite phase.
Referring to fig. 1, the first capacitance control unit 11 includes a first capacitance C 2,1 A second capacitor C 1,1 Third capacitor C 0,1 Third NMOS tube Mn 3 Fourth NMOS tube Mn 4 And a fifth NMOS tube Mn 5 First capacitor C 2,1 One end polar plate of (a) and a second capacitorC 1,1 And a third capacitor C 0,1 One end polar plate of the first PMOS tube Mp is commonly connected with 1 Drain electrode of (C), first capacitor C 2,1 The other end polar plate of the (B) is connected with a third NMOS tube Mn 3 Drain electrode of the third NMOS transistor Mn 3 The grid electrode of the first BIT2 is connected with the source electrode of the first BIT; second capacitor C 1,1 The other end polar plate of the (B) is connected with a fourth NMOS tube Mn 4 Drain electrode of the fourth NMOS transistor Mn 4 The gate of the second NMOS transistor is connected with the second BIT1, the fourth NMOS transistor Mn 4 The source electrode of the transistor is grounded; third capacitor C 0,1 The other end polar plate of the (B) is connected with a fifth NMOS tube Mn 5 Drain electrode of fifth NMOS transistor Mn 5 The gate of the first BIT is connected with the third BIT0, and the source is grounded; the second capacitance control unit 12 includes a fourth capacitance C 2,2 Fifth capacitor C 1,2 Sixth capacitor C 0,2 Mn of sixth NMOS tube 6 Seventh NMOS tube Mn 7 And an eighth NMOS transistor Mn 8 Fourth capacitor C 2,2 Fifth capacitor C 1,2 And a sixth capacitance C 0,2 One end polar plate of the first PMOS tube is commonly connected with the second PMOS tube Mp 2 Drain electrode of (C), fourth capacitor C 2,2 The other end polar plate of the (B) is connected with a sixth NMOS tube Mn 6 Drain electrode of the sixth NMOS transistor Mn 6 The grid electrode of the first BIT2 is connected with the source electrode of the first BIT; fifth capacitor C 1,2 The other end polar plate of (C) is connected with a seventh NMOS tube Mn 7 Drain electrode of the seventh NMOS transistor Mn 7 The grid electrode of the first BIT is connected with the second BIT1, and the source electrode is grounded; sixth capacitor C 0,2 The other end polar plate of the (B) is connected with an eighth NMOS tube Mn 8 Drain electrode of eighth NMOS transistor Mn 8 The gate of the first BIT is connected with the third BIT0, and the source is grounded; BITs BIT2, BIT1 and BIT0 play a role in frequency trimming.
Specifically, the working process of the RC oscillator core circuit is as follows:
referring to fig. 1, when the oscillator driving signal osc_en is 0, the first NAND gate NAND 1 The output ends of the second NAND gate NAND are all output as high level 2 The output ends of the first NAND gate NAND are all output as high level 1 The output high level is input into the first inverter INV 1 Second NAND gate NAND 2 High level outputInto a second inverter INV 2 Input end of the first inverter INV 1 The output end of the second inverter INV is low level 2 The output terminals of the first transmission are all output as low level 1 And first transmission of TG 2 Turn off, the first NMOS transistor Mn 1 And a second NMOS transistor Mn 2 On, the oscillating voltage VOSC1 and the oscillating voltage VOSC2 are discharged to a low level, and the RC oscillator is in an off state.
When the oscillator driving signal osc_en is 1, the left and right circuits of the oscillator are in an alternate operation state, and the specific operation state is as follows: when the oscillating voltage VOSC1 is smaller than VC, the first push-pull comparator CAMP 1 Output a high level, a first NAND gate NAND 1 Outputs a low level when the second NAND gate NAND 2 Outputting a high level, a first PMOS tube Mp 1 And a second NMOS transistor Mn 2 First capacitor C in the left half circuit 2,1 A second capacitor C 1,1 And a third capacitor C 0,1 The upper polar plate of the capacitor (C) is in a charging state, the oscillating voltage VOSC1 is gradually increased, and the fourth capacitor (C) in the right half circuit 2,2 Fifth capacitor C 1,2 And a sixth capacitance C 0,2 The upper polar plate of the capacitor is in a discharge state, and the oscillating voltage VOSC2 is pulled down to a low level; wherein VC is the current flowing through the third resistor R 0 Current I_MP of (2) 5 And resistance R 0 Multiplying;
when the oscillating voltage VOSC1 rises to be higher than VC, the first push-pull comparator CAMP1 outputs a low level, the first NAND gate NAND1 outputs a high level, the oscillating voltage VOSC2 is still at a low level, the second push-pull comparator CAMP2 outputs a high level, and the second NAND gate NAND 2 Outputting a low level, a first NMOS transistor Mn 1 And a second PMOS tube Mp 2 Fourth capacitor C in the right half circuit 2,2 Fifth capacitor C 1,2 And a sixth capacitance C 0,2 The upper polar plate of the circuit is in a charging state, the oscillating voltage VOSC2 is gradually increased, and the first capacitor C in the left half circuit 2,1 A second capacitor C 1,1 And a third capacitor C 0,1 The upper polar plate of (1) is in a discharge state, and the oscillating voltage VOSC1 is pulled down to a low level;
when the oscillating voltage VOSC2 is smaller than VC, the second push-pull comparator CAMP2 outputs a high level, and the second NAND gate NAND 2 Outputs a low level when the first NAND gate NAND 1 Outputting a high level, a second PMOS tube Mp 2 And a first NMOS tube Mn 1 Fourth capacitor C in the right half circuit 2,2 Fifth capacitor C 1,2 And a sixth capacitance C 0,2 The upper polar plate of the circuit is in a charging state, the oscillating voltage VOSC2 is gradually increased, and the first capacitor C in the left half circuit 2,1 A second capacitor C 1,1 And a third capacitor C 0,1 The upper polar plate of (1) is in a discharge state, and the oscillating voltage VOSC1 is pulled down to a low level;
when the oscillating voltage VOSC2 rises to be higher than VC, the second push-pull comparator CAMP2 outputs a low level, and the second NAND gate NAND 2 Outputting a high level while the oscillating voltage VOSC1 is still at a low level, the first push-pull comparator CAMP1 outputs a high level, and the first NAND gate 1 Outputting a low level, a second NMOS transistor Mn 2 And a first PMOS tube Mp 1 First capacitor C in the left half circuit 2,1 A second capacitor C 1,1 And a third capacitor C 0,1 The upper polar plate of the capacitor (C) is in a charging state, the oscillating voltage VOSC1 is gradually increased, and the fourth capacitor (C) in the right half circuit 2,2 Fifth capacitor C 1,2 And a sixth capacitance C 0,2 The upper polar plate of the capacitor is in a discharge state, and the oscillating voltage VOSC2 is pulled down to a low level; referring to fig. 1 and 2, the left and right circuits of the rc oscillator core circuit are alternately operated repeatedly by the above operation process, the first NAND gate NAND 1 Is Fout1, and a second NAND gate NAND 2 The output signal of (2) is Fout2, fout1 and Fout2 are square wave signals with opposite phases.
The quiescent current of the temperature compensated RC oscillator circuit based on the bandgap reference in this embodiment is only 65.015uA at a typical supply voltage of 4V, and supports complete shutdown, and zero power consumption is achieved in the shutdown state, thus having the advantage of low power consumption. Further, in this embodiment, experimental results are obtained by using TSMC 180nm process simulation, and referring to FIG. 2, a waveform diagram of an output signal of an oscillator circuit is obtainedThe output signals Fout1 and Fout2 are square wave signals with opposite phases; fig. 3 shows a graph of simulation results of output frequency at a temperature ranging from-40 ℃ to 120 ℃, and from fig. 3, it is known that, at a power supply voltage of 4V and a temperature of 27 ℃, the output signal frequency of the temperature compensation RC oscillator circuit of the embodiment is 2.0025MHz, the maximum output signal frequency is 2.0038MHz and the minimum output signal frequency is 1.9874MHz at a temperature ranging from-40 ℃ to 120 ℃, the frequency variation degree is 0.811%, as shown in the above data, the effect of temperature variation on the output frequency is greatly compensated by adding the temperature compensation circuit, after adding the temperature compensation circuit, the frequency variation of the output frequency of the oscillator circuit does not exceed 1% of a typical value at a temperature ranging from-40 ℃ to 120 ℃, and the requirement of clock signals of an application scene of the internet of things on the temperature stability is met; as shown in fig. 4, the duty ratio simulation result diagram of the output signal of the oscillator circuit shows that, as shown in fig. 4, the duty ratio of the output signal of the temperature compensation RC oscillator circuit of the present embodiment is 50.021%; as shown in fig. 5, the embodiment obtains a frequency simulation result diagram of the output signal of the oscillator circuit, and as can be seen from fig. 5, the stability time of the temperature compensation RC oscillator circuit of the embodiment is lower than 25us, so that the temperature compensation RC oscillator circuit is suitable for the requirements of low power consumption and quick response of various application scenes of the internet of things; at the power supply voltage of 4V and the temperature of 27 ℃, the current in the working state of the circuit is shown in figure 6, and the average current is 65.015uA; FIG. 7 shows an overall circuit layout of an oscillator with a size of 231.309um by 373.91um and a final layout area of 0.0865mm 2 It can be derived that the overall circuit occupies only a small part of the area.
Example 2
Referring to fig. 8, the first push-pull comparator CAMP 1 And a second push-pull comparator CAMP 2 Push-pull comparator circuits are arranged in the two transistors, and each push-pull comparator circuit comprises a sixth PMOS tube Mp 6 Seventh PMOS tube Mp 7 Eighth PMOS tube Mp 8 Ninth PMOS tube Mp 9 Tenth PMOS tube Mp 10 Eleventh PMOS tube Mp 11 Twelfth PMOS tube Mp 12 Ninth NMOS tube Mn 9 Tenth NMOS tube Mn 10 Eleventh NMOS tube Mn 11 Twelfth ofNMOS tube Mn 12 Thirteenth NMOS tube Mn 13 Fourteenth NMOS tube Mn 14 And a fifteenth NMOS transistor Mn 15 The method comprises the steps of carrying out a first treatment on the surface of the The sixth PMOS tube Mp 6 Seventh PMOS tube Mp 7 Eighth PMOS tube Mp 8 And a ninth PMOS tube Mp 9 The source electrode of the power supply is connected with the power supply input end VDD; the sixth PMOS tube Mp 6 The grid electrodes of the P-channel metal oxide semiconductor (PMOS) transistors are respectively connected with a seventh PMOS tube Mp 7 Grid electrode of (C) and seventh PMOS tube Mp 7 Drain electrode of (d), ninth NMOS transistor Mn 9 Drain electrode of (d) and twelfth NMOS transistor Mn 12 A drain electrode of (2); the ninth PMOS tube Mp 9 The grid electrodes of the P-channel metal oxide semiconductor (PMOS) transistors are respectively connected with an eighth P-channel metal oxide semiconductor (MP) 8 Grid electrode of (V) and eighth PMOS tube Mp 8 Drain electrode of (c) and tenth NMOS transistor Mn 10 A drain electrode of (2); the ninth NMOS tube Mn 9 And a tenth NMOS transistor Mn 10 Is commonly connected with an eleventh NMOS tube Mn 11 Drain electrode of the eleventh NMOS transistor Mn 11 The source electrode of (1) is grounded, the gate electrode is connected to the first bias voltage Vb 1 The method comprises the steps of carrying out a first treatment on the surface of the The tenth PMOS tube Mp 10 The source electrode of (2) is connected with the power input end VDD, and the gate electrode is connected with the second bias voltage Vb 2 Drain electrodes are respectively connected with an eleventh PMOS tube Mp 11 And a twelfth PMOS tube Mp 12 A source of (a); the eleventh PMOS tube Mp 11 And a ninth NMOS transistor Mn 9 The grid electrode of the twelfth PMOS tube Mp is commonly connected with the VIN-N end 12 And a tenth NMOS transistor Mn 10 The grid electrode of the first transistor is commonly connected with the VIN_P end; the eleventh PMOS tube Mp 11 The drain electrodes of the N-channel metal oxide semiconductor (NMOS) transistors are respectively connected with a twelfth NMOS transistor Mn 12 Gate electrode of thirteenth NMOS transistor Mn 13 Gate of (c) and thirteenth NMOS transistor Mn 13 Drain electrode of the twelfth PMOS tube Mp 12 The drain electrodes of the N-channel metal oxide semiconductor (NMOS) transistors are respectively connected with a fifteenth NMOS transistor Mn 15 Gate of (d), fourteenth NMOS transistor Mn 14 Gate of (d), fourteenth NMOS transistor Mn 14 Drain electrode of (C) and sixth PMOS tube Mp 6 A drain electrode of (2); the fifteenth NMOS tube Mn 15 Drain electrode of (C) and ninth PMOS tube Mp 9 The drain electrodes of the first and second transistors are commonly connected with the VOUT terminal; the twelfth NMOS transistor Mn 12 Thirteenth NMOS tube Mn 13 Fourteenth NMOS tube Mn 14 And a fifteenth NMOS transistor Mn 15 The source of (c) is grounded.
Specifically, the push-pull comparator circuit works as follows:
when VIN_P is higher than VIN_N, the eleventh PMOS transistor Mp 11 Is passed through the tenth NMOS transistor Mn 10 Ninth NMOS tube Mn 9 Turn off, tenth PMOS tube Mp 10 Leakage current flowing through eleventh PMOS tube Mp 11 Twelfth PMOS tube Mp 12 Turn-off, current flows through the twelfth NMOS transistor Mn 12 And thirteenth NMOS tube Mn 13 Normally work, flows through the eighth PMOS tube Mp 8 The current of the (E) is the twelfth NMOS tube Mn 12 Leakage current and tenth NMOS transistor Mn 10 The sum of leakage currents, the output voltage VOUT is determined by a ninth PMOS transistor Mp 9 Pulled up to VDD.
When VIN_N is higher than VIN_P, the eleventh NMOS transistor Mn 11 Is passed through the ninth NMOS transistor Mn 9 Tenth NMOS tube Mn 10 Turn off, tenth PMOS tube Mp 10 Leakage current flowing through twelfth PMOS tube Mp 12 Eleventh PMOS tube Mp 11 Cut-off, the current passes through the sixth PMOS tube Mp 6 And a seventh PMOS tube Mp 7 Normally work and flow through the fourteenth NMOS tube Mn 14 The current of the transistor is a sixth PMOS transistor Mp 6 Leakage current and twelfth PMOS tube Mp 12 The sum of leakage currents, the output voltage VOUT is obtained by a fifteenth NMOS transistor Mn 15 Pulled down to VSS.
Example 3
Referring to fig. 1, the current-mode summing bandgap reference circuit 2 includes a thirteenth PMOS transistor Mp 13 Fourteenth PMOS tube Mp 14 Fifteenth PMOS tube Mp 15 Sixteenth PMOS tube Mp 16 Seventeenth PMOS tube Mp 17 Eighteenth PMOS tube Mp 18 Seventh capacitor C m Fourth resistor R 1,1 Fifth resistor R 3 Sixth resistor R 1,2 Seventh resistor R Z BJT of first BJT tube 1 BJT of second BJT tube 2 Sixteenth NMOS tube Mn 16 Seventeenth NMOS tube Mn 17 And an eighteenth NMOS tube Mn 18 The method comprises the steps of carrying out a first treatment on the surface of the The thirteenth PMOS tube Mp 13 Fourteenth PMOS tube Mp 14 Fifteenth PMOS tube Mp 15 And a sixteenth PMOS tube Mp 16 The sources of the power supply voltage source are commonly connected with a power supply input end VDD; the thirteenth PMOS tube Mp 13 The drains of the transistors are respectively connected with a fourth resistor R 1,1 Is connected with the first BJT tube BJT 1 Emitter of seventeenth PMOS tube Mp 17 Gate of (d), fourth resistor R 1,1 Is grounded at the other end of the first BJT tube BJT 1 The base and the collector of the transistor are grounded, and the thirteenth PMOS transistor Mp 13 The grid electrodes of the first PMOS tube are respectively connected with a third PMOS tube Mp 3 Grid electrode of the (C) PMOS tube Mp 4 Grid electrode of (C) and fifth PMOS tube Mp 5 Gate of fourteenth PMOS tube Mp 14 Grid electrode of sixteenth PMOS tube Mp 16 Drain electrode of (d), seventh resistor R Z One end of (2) and an eighteenth NMOS tube Mn 18 A drain electrode of (2); the fourteenth PMOS tube Mp 14 The drain electrodes of the first and second transistors are respectively connected with an eighteenth PMOS tube Mp 18 Gate of (d), fifth resistor R 3 And a sixth resistor R 1,2 A fifth resistor R 3 The other end of the second BJT tube is connected with the BJT 2 Emitter of the second BJT tube BJT 2 The base and collector of (2) are grounded, a sixth resistor R 1,2 The other end of the first electrode is grounded; the fifteenth PMOS tube Mp 15 The drain electrodes of the first and the second PMOS tubes are respectively connected with a seventeenth PMOS tube Mp 17 And an eighteenth PMOS tube Mp 18 A fifteenth PMOS tube Mp 15 Is connected with a sixteenth PMOS tube Mp 16 A seventeenth PMOS tube Mp 17 The drain electrodes of the N-channel metal oxide semiconductor (NMOS) transistors are respectively connected with a sixteenth NMOS transistor Mn 16 Drain electrode of sixteenth NMOS transistor Mn 16 Gate of (c) and seventeenth NMOS transistor Mn 17 Gate electrode of eighteenth PMOS tube Mp 18 The drains of the capacitors are respectively connected with a seventh capacitor C m One end polar plate and seventeenth NMOS tube Mn 17 Drain electrode of (c) and eighteenth NMOS transistor Mn 18 Gate of (C), seventh capacitor C m The other end polar plate is connected with a seventh resistor R Z Is the other end of the sixteenth NMOS tube Mn 16 Seventeenth NMOS tube Mn 17 And an eighteenth NMOS tube Mn 18 The source electrode of the transistor is grounded; the first BJT tube BJT 1 Emitter voltage of (1) and second BJT tube BJT 2 Is equal.
The temperature compensation RC oscillator circuit of the embodiment further comprises a bias circuit 3, wherein the bias circuit 3 comprises a nineteenth PMOS tube Mp 19 And a bias current source, nineteenth PMOS tubeMp 19 The source electrode of the (B) is connected with the power input end VDD, and the bias current sources are respectively connected with the fifteenth PMOS tube Mp 15 Grid electrode of sixteenth PMOS tube Mp 16 Gate of nineteenth PMOS tube Mp 19 Is connected with the drain electrode; the negative temperature coefficient current flows through the sixth resistor R 1,2 The positive temperature coefficient current flows through the fifth resistor R 3 The temperature stabilizing current flows through the fourteenth PMOS tube Mp14, and is respectively used as the third PMOS tube Mp flowing through the RC oscillator core circuit 1 3 MP of fourth PMOS tube 4 And a fifth PMOS tube Mp 5 Is provided.
Specifically, the working process of the current-mode summing bandgap reference circuit is as follows:
in the current-mode summing band-gap reference circuit, a fifteenth PMOS tube Mp 15 Seventeenth PMOS tube Mp 17 Eighteenth PMOS tube Mp 18 Sixteenth NMOS tube Mn 16 Seventeenth NMOS tube Mn 17 Sixteenth PMOS tube Mp 16 Seventh capacitor C m Seventh resistor R Z And an eighteenth NMOS tube Mn 18 Forms a simple two-stage operational amplifier circuit to make the first BJT tube BJT 1 Emitter voltage of (1) and second BJT tube BJT 2 The emitter voltages of (1) are forced to be equal and flow through a sixth resistor R 1，2 Is I_R 1，2 Negative temperature coefficient current I_R 1，2 Is VEB1 divided by a sixth resistance R 1，2 The method comprises the steps of carrying out a first treatment on the surface of the Through a fifth resistor R 3 Is I_R 3 Positive temperature coefficient current i_r 3 Is obtained by dividing VEB1 minus VEB2 by the fifth resistance R 3 The method comprises the steps of carrying out a first treatment on the surface of the Wherein the temperature stabilizing current flowing through the fourteenth PMOS tube MP14 is I_MP 14 Temperature stabilizing current I_MP 14 Is a negative temperature coefficient current I_R 1，2 And positive temperature coefficient current I_R 3 A fifth resistor R 3 And a sixth resistor R 1，2 The ratio of the temperature stabilizing currents I_MP is reasonably selected according to actual practice 14 Is a current which does not change significantly with temperature changes; further, through a third PMOS tube MP with the same size as the fourteenth PMOS tube MP14 3 MP of fourth PMOS tube 4 And a fifth PMOS tube Mp 5 This temperature stabilizing current I_MP is set 14 Charging currents I_MP respectively used as left half circuits of core oscillating circuits 3 Charging current I_MP of right half circuit 4 And inflow resistance R 0 Current I_MP of (2) 5 The voltage VC with high relative temperature stability is the current I_MP 5 And resistance R 0 And multiplying to obtain the product.
It is to be understood that the above examples of the present invention are provided by way of illustration only and are not intended to limit the scope of the invention. Other variations or modifications of the above teachings will be apparent to those of ordinary skill in the art. It is not necessary here nor is it exhaustive of all embodiments. Any modification, equivalent replacement, improvement, etc. which come within the spirit and principles of the invention are desired to be protected by the following claims.

Claims (9)

1. A temperature compensated RC oscillator circuit comprising: the RC oscillator comprises an RC oscillator core circuit (1) and a current-mode summing band-gap reference circuit (2), wherein the current-mode summing band-gap reference circuit (2) generates a negative temperature coefficient current and a positive temperature coefficient current, and the negative temperature coefficient current and the positive temperature coefficient current are superposed to form a temperature stabilizing current to be used as a charging current of the RC oscillator core circuit (1);
The RC oscillator core circuit (1) comprises a first NAND gate NAND 1 Second NAND gate NAND 2 A first capacitance control unit (11), a second capacitance control unit (12), a first inverter INV 1 Second inverter INV 2 First transmission gate TG 1 Second transmission gate TG 2 First PMOS tube Mp 1 Second PMOS tube Mp 2 MP of the third PMOS tube 3 MP of fourth PMOS tube 4 Fifth PMOS tube Mp 5 First push-pull comparator CAMP 1 Second push-pull comparator CAMP 2 First NMOS tube Mn 1 Second NMOS tube Mn 2 A first resistor R 2，1 A second resistor R 2，2 And a third resistor R 0 ；
First NAND gate NAND 1 A first input end of the first push-pull comparator is connected with 1 Is an output end of a first NAND gate NAND 1 Is connected to the oscillator enable terminal OSC_EN, the first NAND gate 1 A third input end of (2) is connected with the second NAND gate NAND 2 Is an output end of a first NAND gate NAND 1 The output ends of the (A) are respectively connected with the first NMOS tube Mn 1 Gate of (a) first PMOS tube Mp 1 Gate of (a), first transmission gate TG 1 Low level control bit of (a) and first inverter INV 1 Is provided; first NMOS tube Mn 1 The source electrode of the transistor is grounded; first PMOS tube Mp 1 The source electrode of the (E) is connected with a third PMOS tube MP 3 Drain electrode of the first PMOS tube Mp 1 The drain electrode of (a) is connected with the first resistor R 2，1 Is a first resistor R 2，1 The other end of the first capacitor is connected with a first capacitor control unit (11); first inverter INV 1 The output end is connected with the first transmission gate TG 1 High level control bit of (1), first transmission gate TG 1 The input ends of the first NMOS tube Mn are respectively connected with 1 Drain of (c) and first push-pull comparator CAMP 1 Is connected with the negative input end of the circuit board;
second NAND gate NAND 2 A first input end of the second push-pull comparator is connected with 2 Is an output end of a second NAND gate NAND 2 A second NAND gate connected to the second input terminal of the oscillator enable terminal OSC_EN 2 A third input end of (a) is connected with the first NAND gate NAND 1 Is an output end of a second NAND gate NAND 2 The output ends of the (A) are respectively connected with a second NMOS tube Mn 2 Gate of (2), second PMOS tube Mp 2 Gate of (2), second transmission gate TG 2 Low level control bit of (2) and second inverter INV 2 Is provided; second NMOS tube Mn 2 The source electrode of the second PMOS tube MP is grounded 2 The source electrode of the (E) is connected with the fourth PMOS tube MP 4 Drain electrode of the fourth PMOS tube Mp 4 The drain electrode of (a) is connected with the second resistor R 2，2 One end of (2) a second resistor R 2，2 The other end of the first capacitor is connected with a second capacitor control unit (12); second inverter INV 2 The output end is connected with the second transmission gate TG 2 High level control bit of (1), second transmission gate TG 2 The input ends of the second NMOS tube Mn are respectively connected with 2 Drain of (c) and second push-pull comparator CAMP 2 Is connected with the negative input end of the circuit board;
first push-pull comparator CAMP 1 The positive input ends of (1) are respectively connected with a third resistor R 0 Is arranged at one end of the fifth PMOS tube Mp 5 Drain electrode of the second push-pull comparator CAMP 2 The positive input ends of (1) are respectively connected with a third resistor R 0 One end of the fifth PMOS tube Mp 5 Drain of (c) and first push-pull comparator CAMP 1 A positive input terminal of (2), a third resistor R 0 The other end of the third PMOS tube Mp 3 Source electrode of the fourth PMOS tube Mp 4 Source electrode of (C) and fifth PMOS tube Mp 5 The source electrodes of the third PMOS tube Mp are commonly connected with the power input end VDD 3 Grid electrode of the (C) PMOS tube Mp 4 Gate of (c) and fifth PMOS tube Mp 5 Is connected with the grid electrode of the current mode summation band gap reference circuit (2);
first NAND gate NAND 1 And a second NAND gate NAND 2 The output signal of (a) is a square wave signal with opposite phase.
2. Temperature compensated RC oscillator circuit according to claim 1, characterized in that the first capacitance control unit (11) comprises a first capacitance C 2,1 A second capacitor C 1,1 Third capacitor C 0,1 Third NMOS tube Mn 3 Fourth NMOS tube Mn 4 And a fifth NMOS tube Mn 5 First capacitor C 2,1 One end polar plate of (C) a second capacitor 1,1 And a third capacitor C 0,1 One end polar plate of the first PMOS tube Mp is commonly connected with 1 Drain electrode of (C), first capacitor C 2,1 The other end polar plate of the (B) is connected with a third NMOS tube Mn 3 Drain electrode of the third NMOS transistor Mn 3 The grid electrode of the first BIT2 is connected with the source electrode of the first BIT; second capacitor C 1,1 The other end polar plate of the (B) is connected with a fourth NMOS tube Mn 4 Drain electrode of the fourth NMOS transistor Mn 4 The gate of the second NMOS transistor is connected with the second BIT1, the fourth NMOS transistor Mn 4 The source electrode of the transistor is grounded; third capacitor C 0,1 The other end polar plate of the (B) is connected with a fifth NMOS tube Mn 5 Drain electrode of fifth NMOS transistor Mn 5 The gate of (2) is connected to BIT0 of the third BIT and the source is grounded.
3. Temperature compensated RC oscillator circuit according to claim 2, characterized in that the second capacitance control unit (12) comprises a fourth capacitance C 2,2 Fifth capacitor C 1,2 Sixth capacitor C 0,2 Mn of sixth NMOS tube 6 Seventh NMOS tube Mn 7 And an eighth NMOS transistor Mn 8 Fourth capacitor C 2,2 Fifth capacitor C 1,2 And a sixth capacitance C 0,2 One end polar plate of the first PMOS tube is commonly connected with the second PMOS tube Mp 2 Drain electrode of (C), fourth capacitor C 2,2 The other end polar plate of the (B) is connected with a sixth NMOS tube Mn 6 Drain electrode of the sixth NMOS transistor Mn 6 The grid electrode of the first BIT2 is connected with the source electrode of the first BIT; fifth capacitor C 1,2 The other end polar plate of (C) is connected with a seventh NMOS tube Mn 7 Drain electrode of the seventh NMOS transistor Mn 7 The grid electrode of the first BIT is connected with the second BIT1, and the source electrode is grounded; sixth capacitor C 0,2 The other end polar plate of the (B) is connected with an eighth NMOS tube Mn 8 Drain electrode of eighth NMOS transistor Mn 8 The gate of (2) is connected to BIT0 of the third BIT and the source is grounded.
4. A temperature compensated RC oscillator circuit according to claim 3, wherein the first push-pull comparator CAMP 1 And a second push-pull comparator CAMP 2 Push-pull comparator circuits are arranged in the two transistors, and each push-pull comparator circuit comprises a sixth PMOS tube Mp 6 Seventh PMOS tube Mp 7 Eighth PMOS tube Mp 8 Ninth PMOS tube Mp 9 Tenth PMOS tube Mp 10 Eleventh PMOS tube Mp 11 Twelfth PMOS tube Mp 12 Ninth NMOS tube Mn 9 Tenth NMOS tube Mn 10 Eleventh NMOS tube Mn 11 Twelfth NMOS transistor Mn 12 Thirteenth NMOS tube Mn 13 Fourteenth NMOS tube Mn 14 And a fifteenth NMOS transistor Mn 15 The method comprises the steps of carrying out a first treatment on the surface of the The sixth PMOS tube Mp 6 Seventh PMOS tube Mp 7 Eighth (eighth)PMOS tube Mp 8 And a ninth PMOS tube Mp 9 The source electrode of the power supply is connected with the power supply input end VDD; the sixth PMOS tube Mp 6 The grid electrodes of the P-channel metal oxide semiconductor (PMOS) transistors are respectively connected with a seventh PMOS tube Mp 7 Grid electrode of (C) and seventh PMOS tube Mp 7 Drain electrode of (d), ninth NMOS transistor Mn 9 Drain electrode of (d) and twelfth NMOS transistor Mn 12 A drain electrode of (2); the ninth PMOS tube Mp 9 The grid electrodes of the P-channel metal oxide semiconductor (PMOS) transistors are respectively connected with an eighth P-channel metal oxide semiconductor (MP) 8 Grid electrode of (V) and eighth PMOS tube Mp 8 Drain electrode of (c) and tenth NMOS transistor Mn 10 A drain electrode of (2); the ninth NMOS tube Mn 9 And a tenth NMOS transistor Mn 10 Is commonly connected with an eleventh NMOS tube Mn 11 Drain electrode of the eleventh NMOS transistor Mn 11 The source electrode of (1) is grounded, the gate electrode is connected to the first bias voltage Vb 1 The method comprises the steps of carrying out a first treatment on the surface of the The tenth PMOS tube Mp 10 The source electrode of (2) is connected with the power input end VDD, and the gate electrode is connected with the second bias voltage Vb 2 Drain electrodes are respectively connected with an eleventh PMOS tube Mp 11 And a twelfth PMOS tube Mp 12 A source of (a); the eleventh PMOS tube Mp 11 And a ninth NMOS transistor Mn 9 The grid electrode of the twelfth PMOS tube Mp is commonly connected with the VIN-N end 12 And a tenth NMOS transistor Mn 10 The grid electrode of the first transistor is commonly connected with the VIN_P end; the eleventh PMOS tube Mp 11 The drain electrodes of the N-channel metal oxide semiconductor (NMOS) transistors are respectively connected with a twelfth NMOS transistor Mn 12 Gate electrode of thirteenth NMOS transistor Mn 13 Gate of (c) and thirteenth NMOS transistor Mn 13 Drain electrode of the twelfth PMOS tube Mp 12 The drain electrodes of the N-channel metal oxide semiconductor (NMOS) transistors are respectively connected with a fifteenth NMOS transistor Mn 15 Gate of (d), fourteenth NMOS transistor Mn 14 Gate of (d), fourteenth NMOS transistor Mn 14 Drain electrode of (C) and sixth PMOS tube Mp 6 A drain electrode of (2); the fifteenth NMOS tube Mn 15 Drain electrode of (C) and ninth PMOS tube Mp 9 The drain electrodes of the first and second transistors are commonly connected with the VOUT terminal; the twelfth NMOS transistor Mn 12 Thirteenth NMOS tube Mn 13 Fourteenth NMOS tube Mn 14 And a fifteenth NMOS transistor Mn 15 The source of (c) is grounded.
5. The temperature compensated RC oscillator circuit of claim 4, wherein the current-mode summing bandgap reference circuit (2) comprises a thirteenth PMOS transistor Mp 13 Fourteenth PMOS tube Mp 14 Fifteenth PMOS tube Mp 15 Sixteenth PMOS tube Mp 16 Seventeenth PMOS tube Mp 17 Eighteenth PMOS tube Mp 18 Seventh capacitor C m Fourth resistor R 1,1 Fifth resistor R 3 Sixth resistor R 1,2 Seventh resistor R Z BJT of first BJT tube 1 BJT of second BJT tube 2 Sixteenth NMOS tube Mn 16 Seventeenth NMOS tube Mn 17 And an eighteenth NMOS tube Mn 18 The method comprises the steps of carrying out a first treatment on the surface of the The thirteenth PMOS tube Mp 13 Fourteenth PMOS tube Mp 14 Fifteenth PMOS tube Mp 15 And a sixteenth PMOS tube Mp 16 The sources of the power supply voltage source are commonly connected with a power supply input end VDD; the thirteenth PMOS tube Mp 13 The drains of the transistors are respectively connected with a fourth resistor R 1,1 Is connected with the first BJT tube BJT 1 Emitter of seventeenth PMOS tube Mp 17 Gate of (d), fourth resistor R 1,1 Is grounded at the other end of the first BJT tube BJT 1 The base and the collector of the transistor are grounded, and the thirteenth PMOS transistor Mp 13 The grid electrodes of the first PMOS tube are respectively connected with a third PMOS tube Mp 3 Grid electrode of the (C) PMOS tube Mp 4 Grid electrode of (C) and fifth PMOS tube Mp 5 Gate of fourteenth PMOS tube Mp 14 Grid electrode of sixteenth PMOS tube Mp 16 Drain electrode of (d), seventh resistor R Z One end of (2) and an eighteenth NMOS tube Mn 18 A drain electrode of (2); the fourteenth PMOS tube Mp 14 The drain electrodes of the first and second transistors are respectively connected with an eighteenth PMOS tube Mp 18 Gate of (d), fifth resistor R 3 And a sixth resistor R 1,2 A fifth resistor R 3 The other end of the second BJT tube is connected with the BJT 2 Emitter of the second BJT tube BJT 2 The base and collector of (2) are grounded, a sixth resistor R 1,2 The other end of the first electrode is grounded; the fifteenth PMOS tube Mp 15 The drain electrodes of the first and the second PMOS tubes are respectively connected with a seventeenth PMOS tube Mp 17 And an eighteenth PMOS tube Mp 18 A fifteenth PMOS tube Mp 15 Is connected with a sixteenth PMOS tube Mp 16 A seventeenth PMOS tube Mp 17 The drain electrodes of the N-channel metal oxide semiconductor (NMOS) transistors are respectively connected with a sixteenth NMOS transistor Mn 16 Drain electrode of sixteenth NMOS transistor Mn 16 Gate of (c) and seventeenth NMOS transistor Mn 17 Gate electrode of eighteenth PMOS tube Mp 18 The drains of the capacitors are respectively connected with a seventh capacitor C m One end polar plate and seventeenth NMOS tube Mn 17 Drain electrode of (c) and eighteenth NMOS transistor Mn 18 Gate of (C), seventh capacitor C m The other end polar plate is connected with a seventh resistor R Z Is the other end of the sixteenth NMOS tube Mn 16 Seventeenth NMOS tube Mn 17 And an eighteenth NMOS tube Mn 18 The source of (c) is grounded.
6. The temperature compensated RC oscillator circuit of claim 5, wherein the first BJT tube BJT 1 Emitter voltage of (1) and second BJT tube BJT 2 Is equal.
7. The temperature-compensated RC oscillator circuit of claim 6, further comprising a bias circuit (3), the bias circuit (3) comprising a nineteenth PMOS transistor Mp 19 And a bias current source, nineteenth PMOS tube Mp 19 The source electrode of the (B) is connected with the power input end VDD, and the bias current sources are respectively connected with the fifteenth PMOS tube Mp 15 Grid electrode of sixteenth PMOS tube Mp 16 Gate of nineteenth PMOS tube Mp 19 Is connected to the gate and drain of the transistor.
8. The temperature-compensated RC oscillator circuit of claim 7, wherein the negative temperature coefficient current flows through a sixth resistor R 1,2 The positive temperature coefficient current flows through the fifth resistor R 3 The temperature stabilizing current flows through a fourteenth PMOS tube Mp14, and is respectively used as a third PMOS tube Mp flowing through the RC oscillator core circuit (1) 3 MP of fourth PMOS tube 4 And a fifth PMOS tube Mp 5 Is provided.
9. An application chip of a temperature compensation RC oscillator circuit, wherein the application chip is provided with the temperature compensation RC oscillator circuit of any one of claims 1 to 8.
CN202211123848.4A 2022-09-15 2022-09-15 Temperature compensation RC oscillator circuit and application chip thereof Active CN115395890B (en)

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