CN115395198A - Multilayer ultra-wideband power divider and power dividing device comprising same - Google Patents
Multilayer ultra-wideband power divider and power dividing device comprising same Download PDFInfo
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Abstract
The invention discloses a multilayer ultra-wideband power divider and a power dividing device comprising the same, wherein the multilayer ultra-wideband power divider comprises: a laminate in which a plurality of signal layers are laminated, a ground layer is provided between the signal layers, and a dielectric layer is provided between the signal layers and the ground layer; a plurality of holes for connecting a plurality of signal layers; the stack comprises M-stage cascade-connected power dividers; the M-stage cascade-connected power dividers are arranged on at least two signal layers. The invention adopts a maze mode to shorten the transverse size of a quarter-wavelength line, adopts 45-degree oblique lines to isolate two branches after isolating resistors, improves the isolation degree of the power divider, utilizes multiple layers of vertically interconnected through holes to realize interconnection of more multilevel structures in the same area, and achieves the aim of designing a miniaturized, ultra-wideband and high-isolation power divider.
Description
Technical Field
The invention relates to the technical field of distributors, in particular to a multilayer ultra-wideband power distributor and a power distribution device comprising the same.
Background
The power distributor is a multi-port microwave device, can distribute one path of signal into multi-path signals with equal or unequal divisions, and is widely applied to various wireless passing equipment, various radar equipment, remote sensing equipment and microwave measuring equipment. The power divider can also be used in reverse as a power divider, which can combine signals transmitted from different devices into one signal, so the power divider is also called as a power divider.
In a microwave system, a power distributor needs to have the characteristics of small differential loss, high isolation, good amplitude-phase consistency and the like. This ensures efficient signal distribution and synthesis. The power divider plays a very important role in a simulation phased array system, with the development of software radio, the trend of wide-opening and integration of radio frequency circuits is more and more obvious, and the power divider serving as a key device of a microwave system is also developed towards the direction of broadband and miniaturization.
In order to implement a wide frequency band of the power divider, researchers have developed various broadband technologies to widen the frequency band. At present, the methods for realizing the broadband power divider mainly include increasing the order of the power divider, adopting a coupled three-wire structure, adopting a slot-wire coupling form, adopting a substrate integrated waveguide structure and the like. Wherein improve power divider's order, realize the ultra wide band easiest, wilkinson power divider has fine isolation, therefore multistage cascade Wilkinson power divider is the first choice of ultra wide band high isolation power divider structure.
For the miniaturization of the power divider, low temperature co-fired ceramic (LTCC) technology, microwave multilayer circuit technology, etc. are all effective methods for realizing the miniaturization of the device.
Disclosure of Invention
In view of the above, the present invention provides a multi-layer ultra-wideband power divider and a power dividing apparatus including the same, so as to solve the above technical problems.
The invention discloses a multilayer ultra-wideband power divider, which comprises:
a laminate in which a plurality of signal layers are laminated, a ground layer is provided between the signal layers, and a dielectric layer is provided between the signal layers and the ground layer;
a plurality of holes for connecting a plurality of the signal layers;
the stack comprises M-level cascade-connected power dividers;
the M-stage cascade-connected power dividers are arranged on at least two signal layers.
Further, the laminated body further comprises a signal input end and two signal output ends; the M-level cascade-connected power distributors form two branches; the two branches have the same structure and are symmetrically arranged;
one ends of the two branches are connected and are connected with the signal input end; the other ends of the two branches are respectively connected with a signal output end; and in the direction from signal input to signal output, a first-stage isolation resistor to an Mth-stage isolation resistor are sequentially arranged between the two branches.
Furthermore, each cascade-connected power divider comprises a plurality of symmetrically arranged U-shaped microstrip lines;
the (i + 1) th-level power divider also comprises two microstrip lines which are symmetrically distributed and vertical to each other and are used for dividing the input signal into two paths; the two microstrip lines are respectively connected with two ends of the U-shaped microstrip line; the value range of i is 1 to M-1;
a first-stage power divider is arranged between the signal input end and the first-stage isolation resistor;
an i +1 stage power divider is arranged between the i stage isolation resistor and the i +1 stage isolation resistor.
Further, the laminate comprises:
a first main surface and a second main surface which are surfaces orthogonal to the stacking direction and are arranged oppositely;
the first major surface and the second major surface are both signal layers, and a signal layer is disposed between the first major surface and the second major surface;
the power divider is characterized in that the first main surface is provided with L-level cascade-connected power dividers, the second main surface is provided with K-level cascade-connected power devices, and the sum of L and K is M.
Further, the signal input terminal is located on the first main face and connected with an input terminal of a first-stage power divider of the L-stage cascade-connected power dividers;
the last-stage power divider of the L-stage cascade-connected power divider is connected with the first-stage power divider of the K-stage cascade-connected power device through a through hole;
the output end of the final power divider of the K-stage cascade-connected power device is connected with one end of a strip line on a signal layer between the first main surface and the second main surface through a first blind hole;
the other end of the strip line is connected with the two signal output ends on the first main surface through a second blind hole;
the plurality of holes includes the first blind hole, the second blind hole, and the through hole.
Furthermore, two first microstrip lines are arranged on the first main surface; one ends of the two first microstrip lines are intersected and connected with a final-stage power divider of the power divider in the L-stage cascade connection, and the other ends of the two first microstrip lines are respectively provided with the through holes;
two second microstrip lines are arranged on the second main surface; one ends of the two second microstrip lines are intersected and connected with the first-stage power divider of the K-stage cascade-connected power device, and the other ends of the two second microstrip lines are respectively provided with the through hole;
and one end of a final power divider of the K-stage cascade-connected power device is connected with a third microstrip line with first blind holes at two ends.
Further, the two first microstrip lines are symmetrically distributed; the two second microstrip lines are symmetrically distributed;
the through hole penetrates through the stacked layers.
Furthermore, grounding holes are formed around the through hole, the first blind hole and the second blind hole.
Further, in the direction from signal input to signal output of the M-stage cascade-connected power dividers, the line widths of the power dividers are sequentially increased.
The invention also discloses a multi-layer ultra-wideband power distribution device, which comprises: a plurality of multi-layer ultra-wideband power dividers are connected in sequence; the multi-layer ultra-wideband power distribution device is provided with a signal input end and a plurality of signal output ends; the output end of each multilayer ultra-wideband power divider is connected with one multilayer ultra-wideband power divider.
Due to the adoption of the technical scheme, the invention has the following advantages: the transverse size of a quarter-wave line is shortened in a maze mode, two branches are isolated by 45-degree oblique lines behind an isolation resistor, the isolation degree of the power divider is improved, and interconnection of a multi-level structure is achieved in the same area by utilizing multiple layers of vertically interconnected through holes. The purpose of designing a miniaturized, ultra-wideband and high-isolation power divider is achieved.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments described in the embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings.
Fig. 1 is a schematic structural diagram of a multi-layer ultra-wideband power divider according to an embodiment of the present invention;
fig. 2 (a) is a schematic structural diagram of a signal layer in a five-layer-two-by-one ultra wide band Wilkinson power divider stack structure according to an embodiment of the present invention;
FIG. 2 (b) is a schematic diagram of a further signal layer in a five-layer-two-ultra wide band Wilkinson power divider stack according to an embodiment of the present invention;
FIG. 2 (c) is a schematic diagram of another signal layer of a five-layer-two-by-one ultra wide band Wilkinson power divider stack structure according to an embodiment of the present invention;
FIG. 2 (d) is a three-dimensional schematic diagram of a signal line of a five-layer-two-by-two ultra wide band Wilkinson power divider stack structure according to an embodiment of the present invention;
fig. 2 (e) is a schematic diagram of a five-layer-one-two ultra wide band Wilkinson power divider stack structure according to an embodiment of the present invention;
FIG. 3 is a schematic diagram showing the dimension of a five-layer-one-two ultra wide band Wilkinson power divider in a planar structure according to an embodiment of the present invention;
FIG. 4 is a diagram showing simulation results of the difference loss and the return loss of a five-layer one-to-two ultra wide band Wilkinson power divider according to an embodiment of the present invention;
fig. 5 is a diagram showing a simulation result of isolation of a five-layer-one-to-two ultra wide band Wilkinson power divider according to an embodiment of the present invention;
fig. 6 is a diagram of a standing wave simulation result of a five-layer-one-two ultra wide band Wilkinson power divider according to an embodiment of the present invention;
FIG. 7 is a three-dimensional schematic diagram of a one-to-four power divider according to an embodiment of the present invention;
fig. 8 is a three-dimensional schematic diagram of an one-to-eight power divider according to an embodiment of the present invention.
Detailed Description
The present invention will be further described with reference to the accompanying drawings and examples, it being understood that the examples described are only some of the examples and are not intended to limit the invention to the embodiments described herein. All other embodiments available to those of ordinary skill in the art are intended to be within the scope of the embodiments of the present invention.
The invention provides an embodiment of a multi-layer ultra-wideband power divider, comprising:
a laminate in which a plurality of signal layers are laminated, a ground layer is provided between the signal layers, and a dielectric layer is provided between the signal layers and the ground layer;
a plurality of holes for connecting a plurality of signal layers;
the stack comprises M-stage cascade-connected power dividers; m is a positive integer;
the M-stage cascade-connected power dividers are arranged on at least two signal layers.
In this embodiment, the stacked body further includes a signal input end and two signal output ends; the M-level cascade-connected power distributors form two branches; the two branches have the same structure and are symmetrically arranged;
one end of each of the two branches is connected with the signal input end; the other ends of the two branches are respectively connected with a signal output end; and a first-stage isolation resistor to an Mth-stage isolation resistor are sequentially arranged between the two branches in the direction from signal input to signal output.
In this embodiment, each power divider connected in cascade includes a plurality of symmetrically arranged U-shaped microstrip lines;
the (i + 1) th-level power divider also comprises two microstrip lines which are symmetrically distributed and perpendicular to each other and are used for dividing the input signal into two paths; the two microstrip lines are respectively connected with two ends of the U-shaped microstrip line; the value range of i is 1-M-1, i is a positive integer;
a first-stage power divider is arranged between the signal input end and the first-stage isolation resistor;
an i +1 stage power divider is arranged between the i stage isolation resistor and the i +1 stage isolation resistor.
In this embodiment, the laminate includes:
a first main surface and a second main surface which are surfaces orthogonal to the stacking direction and are arranged oppositely;
the first main surface and the second main surface are both signal layers, and the signal layers are arranged between the first main surface and the second main surface;
l-level cascade-connected power dividers are arranged on the first main face, K-level cascade-connected power devices are arranged on the second main face, and the sum of L and K is M.
In this embodiment, the signal input terminal is located on the first main surface and is connected to the input terminal of the first-stage power divider of the L-stage cascade-connected power divider;
the last-stage power divider of the L-stage cascade-connected power divider is connected with the first-stage power divider of the K-stage cascade-connected power divider through a through hole;
the output end of a final power divider of the K-level cascade-connected power device is connected with one end of a strip line on a signal layer between a first main surface and a second main surface through a first blind hole;
the other end of the strip line is connected with the two signal output ends on the first main surface through the second blind hole;
the plurality of holes include a first blind hole, a second blind hole, and a through hole.
In this embodiment, two first microstrip lines are disposed on the first main surface; one ends of the two first microstrip lines are intersected and connected with a final power divider of the L-stage cascade-connected power divider, and the other ends of the two first microstrip lines are respectively provided with a through hole;
two second microstrip lines are arranged on the second main surface; one ends of the two second microstrip lines are intersected and connected with a first-stage power divider of the K-stage cascade-connected power device, and the other ends of the two second microstrip lines are respectively provided with a through hole;
one end of a final power divider of the K-stage cascade-connected power device is connected with a third microstrip line with first blind holes at two ends.
In this embodiment, the two first microstrip lines are symmetrically distributed; the two second microstrip lines are symmetrically distributed;
a via extends through the stack.
In this embodiment, ground vias are disposed around the through hole, the first blind via, and the second blind via.
In this embodiment, in a direction from signal input to signal output of the M-stage cascade-connected power divider, line widths of the power dividers are sequentially increased.
The invention also provides a more specific embodiment, according to the theory of the broadband cascade Wilkinson power divider, the frequency band of the power divider which needs to be covered defines the cascade stage number, and the characteristic impedance and the isolation resistor resistance value of each stage of transmission line are determined.
And selecting a proper plate, and designing the line width and the line length of each level of transmission line according to the characteristic impedance.
The invention adopts a maze mode to shorten the transverse size of a quarter-wave line, and is characterized in that a 45-degree oblique line is designed, two branches are separated, and the isolation of the power divider is increased.
In addition, the invention designs the through holes and blind holes which are vertically interconnected in multiple layers corresponding to the frequency range, thereby realizing the cascade intercommunication of the multilayer network and reducing the plane size of the circuit board; and the grounding holes are designed around the through holes and the blind holes, so that the effects of improving the signal isolation and port standing waves are realized.
And establishing a complete multilayer power divider model, optimizing the width and length of each stage of transmission line, and realizing the design of the power divider of the target frequency band.
The invention takes a halving power divider of 0.2-2 GHz frequency band as an example, referring to fig. 1, the frequency band of the designed power divider spans 10 octaves, and 7-stage Wilkinson power divider cascade design is needed. The impedance of each stage and the corresponding isolation resistance are shown in table 1.
TABLE 1 impedance and corresponding isolation resistance for each stage of a power divider
Selecting Rogers 4350 plates, each having a thickness of 20mil, each layer pattern of the power divider was designed according to the stacked structure of FIGS. 2 (a) to 2 (e). The invented power divider has 5 layers in total, the first layer, the third layer and the fifth layer are signal layers, and the second layer and the fourth layer are grounds.
The pattern size of each signal layer is shown in fig. 3, wherein, viewed from the direction from the signal input end to the signal output end, the line widths of the 7-stage cascade-connected power dividers are sequentially increased; the pattern of the first layer comprises a four-level cascade structure, and the pattern of the fifth layer comprises a three-level cascade connection structure; the third layer pattern comprises two microstrip lines which are distributed in a flat mode, and the line widths of the microstrip lines are the same. The cascade connection between every two stages adopts 45-degree oblique lines to separate two branches so as to improve the isolation. The first layer of final stage is designed with radio frequency through holes, the power divider structure is transited to the fifth layer, the fifth layer comprises a three-stage cascade structure, and the cascade between every two stages still adopts 45-degree oblique lines to separate two branches so as to improve the isolation. And designing radio frequency blind holes from the fifth layer to the third layer at the last stage of the fifth layer, transferring the power divider structure to the third layer, walking a strip line with a certain length on the third layer, and then designing the blind holes to connect the strip line on the third layer with the microstrip line on the first layer.
Fig. 4, fig. 5 and fig. 6 show the performance of the invented 0.2-2 GHz multilayer Wilkinson power divider, and simulation results show that the insertion loss is between 3.2 and 3.8dB, the return loss is less than-18 dB, and the isolation is greater than 20dB.
The design example is a five-layer one-by-two ultra-wideband power divider, and the power divider with more layers, such as eight layers and ten layers, can still be designed by the method of the invention.
The present invention also provides an embodiment of a multi-layer ultra-wideband power distribution apparatus, comprising: a plurality of multi-layer ultra-wideband power dividers connected in sequence as shown in the above embodiments; the multi-layer ultra-wideband power distribution device is provided with a signal input end and a plurality of signal output ends; the output end of each multilayer ultra-wideband power divider is connected with one multilayer ultra-wideband power divider. More branches, such as a four-to-four, an eight-to-eight, and a sixteen-to-six power divider, may be provided in this embodiment. Fig. 7 and 8 show a one-to-four and one-to-eight power splitter based on a 0.2-2 GHz one-to-two power splitter design, respectively.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solutions of the present invention and not for limiting the same, and although the present invention is described in detail with reference to the above embodiments, those of ordinary skill in the art should understand that: modifications and equivalents may be made to the embodiments of the invention without departing from the spirit and scope of the invention, which is to be covered by the claims.
Claims (10)
1. A multi-layer ultra-wideband power divider, comprising:
a laminate in which a plurality of signal layers are laminated, a ground layer is provided between the signal layers, and a dielectric layer is provided between the signal layers and the ground layer;
a plurality of holes for connecting a plurality of the signal layers;
the stack comprises M-level cascade-connected power dividers;
the M-stage cascade-connected power dividers are arranged on at least two signal layers.
2. The multi-layer ultra-wideband power divider of claim 1, wherein the stack further comprises a signal input, two signal outputs; the M-level cascade-connected power distributors form two branches; the two branches have the same structure and are symmetrically arranged;
one end of each of the two branches is connected with the signal input end; the other ends of the two branches are respectively connected with a signal output end; and in the direction from signal input to signal output, a first-stage isolation resistor to an Mth-stage isolation resistor are sequentially arranged between the two branches.
3. The multi-layer ultra-wideband power divider of claim 2, wherein each cascade-connected power divider comprises a plurality of symmetrically arranged U-shaped microstrip lines;
the (i + 1) th-level power divider also comprises two microstrip lines which are symmetrically distributed and perpendicular to each other and are used for dividing the input signal into two paths; the two microstrip lines are respectively connected with two ends of the U-shaped microstrip line; the value range of i is 1 to M-1;
a first-stage power divider is arranged between the signal input end and the first-stage isolation resistor;
an i +1 stage power divider is arranged between the i stage isolation resistor and the i +1 stage isolation resistor.
4. The multi-layer ultra-wideband power divider of claim 2, wherein the stack comprises:
a first main surface and a second main surface which are surfaces orthogonal to the stacking direction and are arranged oppositely;
the first major surface and the second major surface are both signal layers, and a signal layer is disposed between the first major surface and the second major surface;
the power divider is characterized in that L-level cascade connection power dividers are arranged on the first main face, K-level cascade connection power devices are arranged on the second main face, and the sum of L and K is M.
5. The multi-layer ultra-wideband power divider of claim 4, wherein the signal input is located on the first major face and is connected to an input of a first-stage power divider of the L-stage cascade-connected power dividers;
the last-stage power divider of the L-stage cascade-connected power divider is connected with the first-stage power divider of the K-stage cascade-connected power device through a through hole;
the output end of a final power divider of the K-stage cascade-connected power device is connected with one end of a strip line on a signal layer between the first main surface and the second main surface through a first blind hole;
the other end of the strip line is connected with the two signal output ends on the first main surface through a second blind hole;
the plurality of holes include the first blind hole, the second blind hole, and the through hole.
6. The multi-layer ultra-wideband power divider of claim 5, wherein two first microstrip lines are disposed on the first major face; one ends of the two first microstrip lines are intersected and connected with a final power divider of the L-stage cascade-connected power divider, and the other ends of the two first microstrip lines are respectively provided with the through holes;
two second microstrip lines are arranged on the second main surface; one ends of the two second microstrip lines are intersected and connected with the first-stage power divider of the K-stage cascade-connected power device, and the other ends of the two second microstrip lines are respectively provided with the through holes;
one end of a final-stage power divider of the K-stage cascade-connected power device is connected with a third microstrip line with first blind holes at two ends.
7. The multi-layer ultra-wideband power divider of claim 6, wherein the two first microstrip lines are symmetrically distributed; the two second microstrip lines are symmetrically distributed;
the through hole penetrates through the stacked layers.
8. The multi-layer ultra-wideband power divider of claim 5, wherein ground vias are provided around the through via, the first blind via, and the second blind via.
9. The multi-layer ultra-wideband power divider of claim 1, wherein the line widths of the M-stage cascade-connected power dividers increase in sequence from signal input to signal output.
10. A multi-layer ultra-wideband power distribution apparatus, comprising: a plurality of sequentially connected multi-layer ultra-wideband power dividers as claimed in any one of claims 1 to 9; the multilayer ultra-wideband power distribution device is provided with a signal input end and a plurality of signal output ends; the output end of each multilayer ultra-wideband power divider is connected with one multilayer ultra-wideband power divider.
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| TWI845198B (en) * | 2023-02-23 | 2024-06-11 | 大陸商鵬鼎控股（深圳）股份有限公司 | Power divider and method for making it |
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| CN116387787B (en) * | 2023-05-04 | 2024-05-17 | 石家庄烽瓷电子技术有限公司 | Three-dimensional structured miniature Wilkinson power divider |
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