CN115376597A

CN115376597A - Programming method of memory, memory and storage system

Info

Publication number: CN115376597A
Application number: CN202210842664.7A
Authority: CN
Inventors: 万维俊
Original assignee: Yangtze Memory Technologies Co Ltd
Current assignee: Yangtze Memory Technologies Co Ltd
Priority date: 2022-07-18
Filing date: 2022-07-18
Publication date: 2022-11-22

Abstract

The application provides a programming method of a memory, the memory and a storage system, and relates to the technical field of storage. The method comprises the following steps: in the programming verification process of synchronously programming at least two memory units, obtaining the programming verification result of the m-th data state of the at least two memory units in the nth programming pulse cycle phase; in response to the presence of a memory cell that fails program verify of the at least two memory cells and the number of verify times reaching the maximum number of verify times, the memory cell that failed program verify is disabled and the (m + 1) th data state is verified in the nth program pulse cycle phase. In the process of programming verification, when a bad block is forbidden after the maximum verification times, the program verification is performed after the program does not need to enter the next programming pulse cycle stage, and the subsequent data state programming verification is directly performed in the current programming pulse cycle stage, so that the efficiency of the programming verification is improved.

Description

Programming method of memory, memory and storage system

Technical Field

The present disclosure relates to the field of memory technologies, and in particular, to a programming method for a memory, a memory and a memory system.

Background

A three-dimensional (3D) memory supports multi-plane programming when programming, i.e., memory cells in different memory blocks can be programmed simultaneously.

The programming process is realized by an Increment Step Pulse Program (ISPP) mode, a programming voltage with a certain Pulse width is applied to each Pulse stage in the ISPP for programming, and the programming voltage is applied and then verified by a verification voltage.

However, when there is a damaged Bad Block (GBB) in the plurality of memory blocks, the verification process of the Bad Block may affect the programming process of the normal memory Block, thereby causing a problem of low programming efficiency.

Disclosure of Invention

The application provides a programming method of a memory, the memory and a storage system, which can improve the programming verification efficiency. The technical scheme is as follows:

in one aspect, a method for programming a memory is provided, the method comprising:

in the programming verification process of synchronously programming a plurality of memory blocks, obtaining the programming verification result of the memory blocks on the mth data state in the nth programming pulse cycle phase, wherein n and m are positive integers;

in response to the existence of a memory block which fails in program verification among the plurality of memory blocks and the verification number for the mth data state reaching the maximum verification number, disabling the memory block which fails in program verification and verifying the (m + 1) th data state in the nth program pulse cycle phase.

In an alternative embodiment, the verifying the (m + 1) th data state in the nth programming pulse cycle phase includes:

acquiring a programming threshold voltage corresponding to the (m + 1) th data state in the nth programming pulse cycle phase;

determining programming pulse voltages corresponding to other memory blocks except the forbidden memory block in the plurality of memory blocks;

comparing the programming pulse voltage with a programming threshold voltage corresponding to the (m + 1) th data state;

and verifying the (m + 1) th data state based on the comparison condition of the programming pulse voltage and the programming threshold voltage corresponding to the (m + 1) th data state.

In an optional embodiment, the method further comprises:

in response to the presence of a memory block in the plurality of memory blocks that fails the program verify and the number of verifies for the mth data state not reaching the maximum number of verifies, verifying the mth data state at the (n + 1) th program pulse cycle phase.

In an optional embodiment, the method further comprises:

in response to the plurality of memory blocks passing program verification and a current program verify process being a non-first verify process in the nth program pulse cycle phase, verifying a subsequent data state of a current data state in the nth program pulse cycle phase.

In an optional embodiment, the method further comprises:

in response to the plurality of memory blocks passing program verification and a current program verify process being a first verify process in the nth program pulse cycle phase, verifying the m +1 th data state in the n +1 th program pulse cycle phase.

In an alternative embodiment, the verifying the (m + 1) th data state in the (n + 1) th program pulse cycle phase includes:

acquiring a data state verification threshold value, wherein the data state verification threshold value is used for representing the total number of data states required to be programmed and reached by the plurality of memory blocks;

in response to the m +1 th data state not reaching the data state verify threshold, the m +1 th data state is verified in the n +1 th program pulse cycle phase.

In an optional embodiment, the method further comprises:

in response to the m +1 th data state reaching the data state verify threshold, ending the program pulse cycle.

In an optional embodiment, the method further comprises:

in response to the memory blocks which do not reach the programming threshold voltage corresponding to the mth data state existing in the plurality of memory blocks, determining that the memory blocks which fail to be programmed and verified exist in the plurality of memory blocks;

determining that the plurality of memory blocks are program verified in response to the plurality of memory blocks reaching the program threshold voltage corresponding to the mth data state.

In an optional embodiment, the method further comprises:

and determining that the program verification of the target storage block fails in response to the fact that the storage unit of the target storage block in the plurality of storage blocks does not reach the program threshold voltage corresponding to the mth data state after programming.

In another aspect, a memory is provided, the memory including: the memory comprises a memory array unit and a peripheral logic unit, wherein the memory array unit comprises a plurality of memory blocks, and the peripheral logic unit comprises a control circuit;

the control circuit is configured to obtain a program verification result of the multiple memory blocks on an m-th data state in an nth program pulse cycle stage in a program verification process of synchronously programming the multiple memory blocks, wherein n and m are positive integers;

the control circuit is further configured to respond to the memory blocks with program verification failure in the plurality of memory blocks and the verification times of the mth data state reach the maximum verification times, disable the memory blocks with program verification failure and verify the (m + 1) th data state in the nth program pulse cycle phase.

In an optional embodiment, the control circuit is further configured to obtain a programming threshold voltage corresponding to the (m + 1) th data state in the nth programming pulse cycle phase; determining programming pulse voltages corresponding to other memory blocks except the forbidden memory block in the plurality of memory blocks; comparing the programming pulse voltage with a programming threshold voltage corresponding to the (m + 1) th data state; and verifying the (m + 1) th data state based on the comparison condition of the programming pulse voltage and the programming threshold voltage corresponding to the (m + 1) th data state.

In an optional embodiment, the control circuit is further configured to verify the mth data state in the (n + 1) th program pulse cycle phase in response to a memory block of the plurality of memory blocks having failed the program verification and the verification number for the mth data state does not reach the maximum verification number.

In an optional embodiment, the control circuit is further configured to verify a subsequent data state of the current data state in the nth program pulse cycle phase in response to the plurality of memory blocks program verifying passing and a current program verifying process not being the first verifying process in the nth program pulse cycle phase.

In an optional embodiment, the control circuit is further configured to verify the m +1 th data state in the n +1 th program pulse cycle phase in response to the plurality of memory blocks passing program verification and a current program verification process being a first verification process in the nth program pulse cycle phase.

In an optional embodiment, the control circuit is further configured to obtain a data state verification threshold, where the data state verification threshold is used to represent a total number of data states required to be programmed by the plurality of memory blocks; in response to the m +1 th data state not reaching the data state verify threshold, the m +1 th data state is verified in the n +1 th program pulse cycle phase.

In an optional embodiment, the control circuitry is further configured to end the program pulse cycle in response to the m +1 th data state reaching the data state verify threshold.

In an optional embodiment, the control circuit is further configured to determine that a memory block which fails to program verification exists in the plurality of memory blocks in response to a memory block which does not reach a program threshold voltage corresponding to an mth data state existing in the plurality of memory blocks; determining that the plurality of memory blocks are program verified in response to the plurality of memory blocks reaching the program threshold voltage corresponding to the mth data state.

In an optional embodiment, the control circuit is further configured to determine that the target memory block of the plurality of memory blocks fails program verification in response to the memory cells of the target memory block not reaching a program threshold voltage corresponding to the mth data state after programming.

In another aspect, a storage system is provided, the storage system including:

one or more memories as described in the above embodiments, and,

a memory controller coupled to the memory and configured to control the storing.

In another aspect, there is provided a computer readable storage medium having stored therein instructions which, when run on control circuitry, implement a method of programming a memory as in any one of the above embodiments.

The technical scheme provided by the application can comprise the following beneficial effects:

in the process of programming verification, when a bad block is forbidden after the maximum verification times, the program verification is directly performed in the current programming pulse cycle stage without entering the next programming pulse cycle stage for programming and then performing the programming verification, so that the efficiency of the programming verification is improved, the increase of the times of the programming pulse cycle stages is avoided, the time consumption of programming is reduced, and the programming speed is improved.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the description below are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings without creative efforts.

FIG. 1 is a schematic diagram of a 3D memory according to an exemplary embodiment of the present application;

FIG. 2 is a schematic diagram of stepped pulse voltage programming provided by an exemplary embodiment of the present application;

FIG. 3 is a flow chart of a multi-faceted programming and verification process provided by an exemplary embodiment of the present application;

FIG. 4 is a schematic diagram of a program verification process provided in the related art;

FIG. 5 is a flow chart of a method for programming a memory provided by an exemplary embodiment of the present application;

FIG. 6 is a flow chart of a method for programming a memory provided by another exemplary embodiment of the present application;

FIG. 7 is a flow chart of a method for programming a memory provided by another exemplary embodiment of the present application;

FIG. 8 is a schematic diagram of a memory provided in an exemplary embodiment of the present application;

fig. 9 is a schematic structural diagram of a storage system according to an exemplary embodiment of the present application.

Detailed Description

Embodiments of the present application are described in further detail below with reference to the accompanying drawings.

The programming method of the memory provided by the embodiment of the application can be applied to the memory. The memory may be a 3D memory, for example, a 3D NAND gate flash (NAND flash).

A three-dimensional (3D) memory is a multi-layer stacked memory, illustratively, a 3D NAND flash (NAND flash). As shown in fig. 1, a plurality of memory strings 110 (string) included in the 3D memory 100 are arranged in a direction parallel to a carrying surface of a substrate, and a plurality of memory cells 120 in each memory string 110 are arranged in a direction perpendicular to the carrying surface of the substrate. That is, the 3D memory includes a plurality of memory cells arranged in a three-dimensional array on a substrate and forming a memory array (array).

One end of the memory string 110 is connected to a Bit Line (BL), and the other end is connected to a Source Line (SL).

The memory cells in each memory string are also connected to memory cells in other memory strings by Word Lines (WL). Such as: each memory string may include 64 memory cells, and the 3D memory may include 64 word lines WL <63:0>, each word line is connected to a portion of the memory cells located at the same level (i.e., at the same height relative to the substrate). It should be noted that 64 memory cells are only one specific example, and the application is not limited thereto, and in some embodiments, each memory string may include more than 64 memory cells, such as 128, 196, and the like. In a 3D memory, each memory cell connected to the same word line is referred to as a page (page), and all memory strings sharing a group of word lines are referred to as a block (block).

The memory string 110 further includes an upper select transistor connected to the drain of the first memory cell and a lower select transistor connected to the source of the last memory cell. Among them, the upper selection tube is also called Top Select Gate (TSG) or drain selection tube. The lower selection Gate is also called a Bottom Select Gate (BSG) or a source selection Gate.

The gate of the TSG is connected to a Drain Select Line (DSL), the source of the TSG is connected to the Drain of the first memory cell, and the Drain of the TSG is connected to the bit Line.

The gate of the BSG is connected to a Source Select Line (SSL), the drain of the BSG is connected to the Source of the last memory cell, and the Source of the BSG is connected to the Source Line.

As can be seen in fig. 1, memory cells in memory string 110 share a set of WLs with memory cells in other memory strings. Assuming that each memory string includes m +1 memory cells, the 3D memory may include m +1 WL: WL0 to WLm, m being an integer greater than 1. Each WL is connected to a respective memory cell on the same level (i.e., at the same height with respect to the carrying surface of the substrate). Alternatively, it can be understood that: the control gates of the memory cells on the same layer and the gate connection lines between the control gates form a WL.

The types of the memory cells may be divided into single-level cells (SLC), double-level cells (MLC), triple-level cells (TLC), four-level cells (QLC), and the like according to the amount of data that can be stored in the memory cells. Wherein, each SLC can store 1 bit (bit) data, each MLC can store 2bit data, each TLC can store 3bit data, each QLC can store 4bit data. In the 3D memory, data stored in respective memory cells located at the same layer may constitute k memory pages (pages). And k is the number of bits of data which can be stored in each storage unit.

In the embodiment of the present application, the storage unit in the 3D memory may be a floating gate fet or a charge trap (charge trap) fet, which is capable of storing data. The TSG and BSG may be ordinary fets or may be fets capable of storing data. The floating gate field effect transistor comprises a source electrode, a drain electrode and two grid electrodes. The two gates are both conductors, one of the two gates is a Control Gate (CG), and the other gate is a Floating Gate (FG), which is referred to as a floating gate for short. The control gate is used to connect to a word line and the floating gate is used to store a cell of data. The charge trap type field effect transistor includes a source electrode, a drain electrode, a control gate, and a charge trap layer, which is a cell for storing data, and is made of an insulating material such as silicon nitride. The following description will be made on the data writing principle of the memory cell by taking a floating gate field effect transistor as an example.

In writing data into the memory cell, a programming voltage may be applied to the control gate of the floating gate fet to cause electrons in the channel of the floating gate fet to tunnel to the floating gate. The quantity of electrons tunneled to the floating gate can be controlled by controlling the magnitude of the programming voltage, and further the magnitude of the threshold voltage Vth of the floating gate field effect tube is controlled. In general, the higher the amount of charge stored in the floating gate, the higher the threshold voltage Vth of the floating gate field effect transistor. It can be understood that when the threshold voltage Vth of the floating gate field effect transistor is different, the voltage which is required to be loaded on the control gate of the floating gate field effect transistor when the floating gate field effect transistor is controlled to be conducted is different. Therefore, the threshold voltage Vth of the floating gate fet can reflect the content of the data stored therein.

It should be understood that in a 3D memory, the channels of the individual memory cells in each memory string can be connected in sequence and form a pillar structure perpendicular to the substrate.

At present, the programming mode mainly used in the memory programming is an incremental Pulse voltage programming (ISPP) mode, and when the programming voltage is applied in the programming process, the voltage is not applied in place at one time, but the programming voltage is incrementally increased Step by Step until the voltage reaches the programming requirement.

Referring to fig. 2, schematically, an ISPP programming diagram provided by an exemplary embodiment of the present application is shown, as shown in fig. 2, in a programming process, a programming phase and a verification phase are included, first, an initial voltage is applied to a selected word line corresponding to a selected memory cell in a first pulse phase 210, which is the programming phase, then, whether the initial voltage reaches a required programming voltage is verified, which is the verification phase, if the initial voltage does not reach the required programming voltage, a voltage step size Δ Vpp is added on the basis of the initial voltage to obtain a second pulse voltage, and the second pulse voltage is applied to the selected word line corresponding to the selected memory cell in a second pulse phase 220, which is another programming phase of step programming, and whether the second pulse voltage reaches the required programming voltage, which is the verification phase corresponding to the another programming phase. The above process is cycled until the pulse voltage applied to the selected word line reaches the desired programming voltage, and programming is stopped.

In programming the memory, for example, MLC may be configured to store two data numbers per memory cell represented by four Vth ranges (data states), TLC may be configured to store three data numbers per memory cell represented by eight Vth ranges (data states), QLC may be configured to store four data numbers per memory cell represented by sixteen Vth ranges (data states), and so on.

For example, when the 3D NAND flash memory is an MLC flash memory, the memory cells of the 3D NAND flash memory may be programmed to four states corresponding to the bit codes 11, 10, 01, 00, i.e., a programmed state P0 (default to an erased state), P1, P2, P3, by the verifying voltages PV1, PV2, PV 3. In another embodiment, when the 3D NAND flash memory is the TLC 3D NAND flash memory, the memory cells of the 3D NAND flash memory may be programmed to eight data states corresponding to the

bit codes

111, 110, 010, 011, 001, 000, 100, 101 by the verify voltages PV1-PV7 based on the first verify process.

The 3D NAND supports multi-plane programming (multi-plane programming) when programming, and each plane (also called a memory block) includes a plurality of memory cells, and the memory cells in different memory blocks can be programmed synchronously. Illustratively, in multi-plane programming, memory cell 0 in memory block 0, memory cell 1 in memory block 1, and memory cell 2 in memory block 2 are programmed simultaneously.

Schematically, FIG. 3 is a flow chart of a multi-faceted programming and verification process provided by an exemplary embodiment of the present application. As shown in fig. 3, the process includes the following steps.

In step 301, a program pulse is applied.

That is, a programming pulse voltage is applied to a memory cell in a plurality of memory blocks to be programmed, and the voltage is applied to a word line corresponding to the memory cell when the programming pulse voltage is applied, thereby programming the memory cell.

Step 302, program verify and error bit count.

That is, whether the program pulse voltage reaches a program threshold voltage required for a data state is verified. The error bit count is to verify the number of programming threshold voltages corresponding to the data states in the memory block for each memory block in the multi-plane programming, so as to determine whether the memory block has not reached the current data state required to be reached. In some embodiments, it is determined whether a memory block reaches a desired data state by verifying whether memory cells in the memory block reach a programmed threshold voltage. Optionally, the number of memory cells in the memory block that do not reach the programming threshold voltage is determined, and when the number of memory cells that do not reach the programming threshold voltage reaches the number threshold, it is determined that the memory block does not reach the data state required to be reached, that is, the memory block is a bad block.

Step 303, determine whether the verified data state reaches the maximum data state.

When the data state reaches the maximum data state, the corresponding programming of all the current data states is successful; and when the data state does not reach the maximum data state, the verification of the currently existing data state is not completed.

At step 304, programming is terminated when the maximum data state is reached.

In some embodiments, the voltage threshold is reached by pulsing the voltage once, or by pulsing the voltage multiple times.

Illustratively, the type of the memory cell is TLC, which has 8 data states, wherein 1 data state (0 th state) is used as an erase state, and 7 data states (1 st to 7 th states) are used as program states, and the method adopts ISPP programming. The fact that the programming reaches the 1 st state can be obtained according to practical experience values, and program pulses are applied for about several times, namely, program verification is carried out for several times, for example, the programming reaches the 1 st state and the programming is completed within 6 times of program verification; programming to state 2 needs to be completed within 9 program verifications; generally, the higher the data state, the more program verify times are required. That is, the preset number of program-verify times is related to the number of bits of the data state, and generally, the higher the number of bits of the data state, the larger the preset number of program-verify times for the corresponding data state.

Optionally, if the maximum data state is not reached, continuing to apply the programming pulse, and gradually increasing the applied pulse voltage according to the pulse voltage application mode of the ISPP.

Fig. 4 is a schematic diagram of a program verification process provided in the related art, namely, an expanded description of the implementation of the above step 302 in the related art. As shown in fig. 4, in the related art, the program verification process includes the following steps.

In step 401, the error bit count is verified.

That is, in the program pulse cycle phase, after the program pulse voltage is applied to the memory cells in the plurality of memory blocks, the program verification is performed on the memory cells, and the program verification result of each of the memory cells in the plurality of memory blocks is determined.

Step 402, determine whether the plurality of memory blocks all pass the data state verification.

That is, it is determined whether there is a memory block that fails the verification of the current data state. In some embodiments, when a memory cell in a memory block fails data state verification, then the memory block fails data state verification; or, when the number of memory cells in the memory block which fail data state verification reaches the number threshold, the memory block fails data state verification.

In step 403, when the plurality of memory blocks pass the data state verification, the data state +1.

That is, the current data state +1 is used as the data state to be verified, and the next programming pulse cycle is performed, and the data state to be verified is verified.

When all the memory blocks pass the data state verification, the current data state programming is completed, and the verification can be performed on the next data state, so that the next programming pulse cycle is entered, and the programming verification is performed on the next data state.

In step 404, when a storage block in the plurality of storage blocks fails to pass the data state verification, it is determined whether the verification frequency for the current data state reaches the maximum frequency.

In step 405, when the number of verify times for the current data state has not reached the maximum number, the next program pulse cycle is performed.

Wherein the current data state continues to be verified in the next programming pulse cycle.

At step 406, when the number of times of verification for the current data state reaches the maximum number of times, the memory block that failed verification is disabled.

Optionally, after disabling the memory block which fails to verify, the next program pulse cycle is performed for the memory block which succeeds in verifying, and the next data state is verified.

Because the memory cell has a service life or other physical defects, which may cause a programming failure, when the verification times of the data state reach the maximum times and the memory block does not meet the programming voltage requirement, it is determined that the memory block is damaged, and the memory block is disabled. And continuing to perform the next programming pulse cycle for the successfully verified memory block, and verifying the next data state.

In the program verification process provided in the related art, when a bad block exists, the number of times of verification for the same data state is increased due to the influence of the bad block, and in the process of multiple pulse cycles, the program pulse voltages of other successfully verified memory blocks continue to be promoted to the subsequent data state, while the program verification process is still in the data state in which the bad block cannot pass, so that the program verification efficiency of a normal memory block is low, and thus the overall program verification efficiency is low and the program speed is low.

Illustratively, in multi-plane programming, synchronous programming is performed for memory blocks 0/1/2/3, where memory block 0 is a bad block, the maximum number of verify cycles is 10, and normally, the memory cells in memory block 0 can pass through data state 3 at the 5 th verify. While the memory cells in memory block 0 have not passed data state 3 by the 10 th cycle of the programming pulse, memory block 0 is determined to be a bad block and disabled, while the other memory blocks have passed data state 5 by the 10 th cycle of the programming pulse, while data states 4 and 5 have not been verified, thereby requiring an additional two additional cycles of programming pulses to pass the verification of data states 4 and 5.

Fig. 5 is a flowchart of a programming method of a memory according to an exemplary embodiment of the present application, for example, the method is applied to a 3D memory, as shown in fig. 5, and the method includes:

step 501, in the process of program verification for synchronous programming of a plurality of memory blocks, obtaining the program verification result of the m-th data state of the plurality of memory blocks in the nth program pulse cycle phase, where n and m are positive integers.

In some embodiments, the simultaneous programming of multiple memory blocks is typically implemented as multi-faceted programming, i.e., simultaneous programming for memory cells in different memory blocks. Optionally, at least two selected memory cells are programmed synchronously, wherein the selected memory cells are memory cells selected for data writing, and the memory cells other than the selected memory cells are deselected memory cells.

Optionally, a programming voltage V is applied to the selected word line _pgm Meanwhile, a conducting voltage V can be loaded on the unselected (unsel) WL _pass . The turn-on voltage V _pass The unselected memory cells connected with the unselected word lines (unsel WL) are all conducted to realize the connection of the selected memory cells and sel BL.

After the program voltage is applied, program verification is performed on the program of the selected memory cells in the plurality of memory blocks, and a program verification result of each selected memory cell is determined. The program verify result indicates whether the selected memory cell reaches a program voltage corresponding to the data state. And obtaining the program verification results of the plurality of memory blocks according to the program verification results of the selected memory cells.

Since there are at least two selected memory cells for programming synchronously, each programming pulse cycle is that at least two selected memory cells apply programming pulse voltages synchronously and perform program verification synchronously, that is, at least two selected memory cells perform program verification for the same data state in the same programming pulse cycle, such as: in this embodiment, at least two selected memory cells in the plurality of memory blocks perform program verification on the mth data state in the nth program pulse cycle, and obtain a program verification result.

The program verification result of the m-th data state of the at least two memory cells in the nth program pulse cycle phase comprises: 1. all pass; 2. none of them pass; 3. any of which is partially passed.

It will be appreciated that the programming voltage V _pgm Generally higher, a larger voltage difference can be formed between the control gate and the channel of the selected memory cell, and electrons in the channel tunnel to the floating gate of the selected memory cell, so as to realize the storage of data. And, by adjusting the programming voltage V _pgm I.e., the number of electrons stored in the floating gate, and thus the threshold voltage Vth of the selected memory cell.

Due to the on-voltage V _pass Usually lower than the programming voltage V _pgm Therefore, the voltage difference between the control gate and the channel of the deselected memory cell connected by the unsel WL is relatively small, so that the electrons in the channel can be prevented from tunneling to the floating gate. For the deselected memory cells connected with the sel WL in the deselected memory string, because the channel of the deselected memory string is floating, the voltage difference between the control gate and the channel of the deselected memory cells connected with the sel WL is relatively small, and electrons in the channel can be prevented from tunneling to the floating gate. That is, when programming a selected memory cell, the unselected memory cell to which the unsel WL is connected, and the unselected memory cell to which the sel WL is connected, are not programmed, i.e., programming of the unselected memory cell is inhibited.

Step 502, in response to the memory block with program verification failure existing in the plurality of memory blocks and the verification frequency for the mth data state reaching the maximum verification frequency, disabling the memory block with program verification failure and verifying the (m + 1) th data state in the nth program pulse cycle phase.

In some embodiments, the verifying for the mth data state reaching the maximum verifying number refers to verifying the mth data state through the programming pulse cycle phase of the maximum verifying number, and the memory block still fails to verify the mth data state, that is, the verifying for the mth data state reaching the maximum verifying number.

When the verification frequency aiming at the mth data state reaches the maximum verification frequency, the memory block which is not verified cannot be normally programmed, the bad block which cannot be verified is forbidden due to the fact that the memory block is a bad block due to service life or other physical defects, and the verification of the (m + 1) th data state is carried out in the current nth programming pulse circulation phase aiming at other memory blocks which are verified.

That is, the subsequent data state of the normal memory block can be verified continuously in the current programming pulse cycle stage without entering the (n + 1) th programming pulse cycle stage to continue the promotion and application of the programming voltage until the data state that the normal memory block has not been programmed is verified, and the subsequent programming pulse cycle process is continued.

In some embodiments, in response to a memory block not reaching a program threshold voltage corresponding to the mth data state being present in the at least two memory blocks, determining that a memory block which failed the program verification is present in the at least two memory blocks; in response to the at least two memory blocks reaching the programmed threshold voltage corresponding to the mth data state, it is determined that the at least two memory blocks were successfully program verified.

In some embodiments, the program verification of the target memory block is determined to fail in response to the memory cells of the target memory block of the plurality of memory blocks not reaching the program threshold voltage corresponding to the mth data state after programming.

In summary, in the method provided in this embodiment, in the process of program verification, when a bad block is disabled after the maximum verification number of times, program verification is performed after programming without entering the next program pulse cycle stage, and program verification of subsequent data states is performed directly in the current program pulse cycle stage, so that the efficiency of program verification is improved, the increase of the number of times of the program pulse cycle stage is avoided, the time consumed by programming is reduced, and the programming speed is improved.

In an alternative embodiment, the branches followed are different for the program verify results of at least two memory blocks. Fig. 6 is a flowchart of a programming method provided in another exemplary embodiment of the present application, as shown in fig. 6, the method including:

step 601, in the process of program verification for synchronously programming a plurality of memory blocks, obtaining the program verification result of the m-th data state of the plurality of memory blocks in the nth program pulse cycle phase, wherein n and m are positive integers.

After the program voltage is applied, program verification is performed on the program of selected memory cells in the plurality of memory blocks, and a program verification result of each memory cell is determined. The program verification result is used for indicating whether the memory cells in the plurality of memory blocks reach the program voltage corresponding to the data state.

Step 602, in response to the memory block with program verification failure existing in the plurality of memory blocks and the verification time for the mth data state reaching the maximum verification time, disabling the memory block with program verification failure and verifying the (m + 1) th data state in the nth program pulse loop phase.

The maximum verification times are preset, and illustratively, the maximum verification times are set to be 5 for the data state 1, 7 for the data state 2, and 8 for the data state 3.

Step 603, in response to that there is a memory block in the plurality of memory blocks that fails to perform program verification and the verification frequency for the mth data state does not reach the maximum verification frequency, verifying the mth data state in the (n + 1) th program pulse cycle stage.

Since the data state is not necessarily reached directly by the single program voltage, and may need to be reached by the multiple program voltage step-up, when the verification time for the mth data state does not reach the maximum verification time, and the memory block program verification fails, the possible situations include at least one of the following situations: 1. the storage block is a bad block and cannot reach the mth data state; 2. the memory cells in the plurality of memory blocks are gradually boosted to the mth data state by the application of the program pulse voltage.

In order to identify a bad block from the plurality of memory blocks and ensure that the program pulse voltage is not gradually increased to the mth data state, when the verification frequency for the mth data state does not reach the maximum verification frequency, the next program pulse cycle phase, namely the (n + 1) th program pulse cycle phase, is continuously entered, and after the application of the program pulse voltage is completed in the (n + 1) th program pulse cycle phase, the verification is continuously performed on the mth data state until the verification of the mth data state is successful, or until the verification frequency for the mth data state reaches the maximum verification frequency.

In step 604, in response to the plurality of memory blocks passing the program-verify and the current program-verify process not being the first-verify process in the nth program pulse cycle, a subsequent data state of the current data state is verified in the nth program pulse cycle.

When the plurality of memory blocks verify in the nth program pulse cycle phase, any one of the following cases is included: 1. the multiple memory blocks are verified directly in the nth programming pulse cycle phase, namely in the nth programming pulse cycle phase, selected memory cells in the multiple memory blocks are verified directly through the mth data state after the programming pulse voltage is applied, namely in the first verification in the nth programming pulse cycle phase, the multiple memory blocks are verified through the mth data state; 2. and in the nth programming pulse cycle phase, the memory blocks fail to verify the mth data state when verified for the first time, and after the memory blocks which fail to verify the mth data state are forbidden, other memory blocks continue to verify the (m + 1) th data state and pass the verification of the (m + 1) th data state, so that the verification of the (m + 1) th data state by other memory blocks is not in the first verification process in the nth programming pulse cycle phase.

Because the other memory blocks are applied with the programming pulse voltage through the multiple programming pulse cycle phase while the bad block is applied with the programming pulse voltage through the multiple programming pulse cycle phase, that is, when the memory block is disabled in the nth programming pulse cycle phase because the memory block is not identified as the bad block through the verification of the mth data state, the selected memory cells in the other memory blocks may have reached the (m + k) th data state, where k is a positive integer, in the nth programming pulse cycle phase, when the other memory blocks pass the verification of the (m + 1) th data state, the verification of the (m + 2) th data state may be continued, until the memory blocks which do not pass the verification exist in the other memory blocks, and then the subsequent programming pulse cycle phase is continued to be performed to perform the programming pulse voltage boosting and verification.

In step 605, in response to the multiple memory blocks passing program verification and the current program verification process is the first verification process in the nth program pulse cycle, the (m + 1) th data state is verified in the (n + 1) th program pulse cycle.

When the program verification of the plurality of memory blocks passes and the plurality of memory blocks directly pass the verification of the mth data state in the nth program pulse cycle phase, the program of the plurality of memory blocks for the mth data state is normal, so that the next program pulse cycle phase, namely the (n + 1) th program pulse cycle phase, is entered, and the verification of the next data state, namely the verification of the (m + 1) th data state is performed.

In some embodiments, before verifying the (m + 1) th data state in the (n + 1) th programming pulse cycle phase, a data state verification threshold is first obtained, and the data state verification threshold is used to indicate the total number of data states to which the memory cells in the plurality of memory blocks need to be programmed, such as: TLC has 8 data states, wherein 1 data state (0 th state) is used as an erased state, and 7 data states (1 st to 7 th states) are used as programmed states, so that at least two memory cells need to be programmed to reach the 7 programmed states, and the 0 th state is a data state reached by default.

And verifying the (m + 1) th data state in the (n + 1) th programming pulse cycle stage in response to the (m + 1) th data state not reaching the data state verification threshold, and indicating that all data states are programmed and verified successfully in response to the (m + 1) th data state reaching the data state verification threshold, so that the programming pulse cycle is ended. In some embodiments, it is determined whether the starting verify level reaches the maximum verify level, and when the starting verify level reaches the maximum verify level, it indicates that the (m + 1) th data state reaches the data state verify threshold, the program pulse cycle is ended.

In summary, in the method provided by this embodiment, in the program verification process, when a bad block is disabled after the maximum verification number, the program verification is performed after the program is performed without entering the next program pulse cycle stage, and the program verification of the subsequent data state is performed directly in the current program pulse cycle stage, so that the program verification efficiency is improved, the increase of the number of program pulse cycle stages is avoided, the time consumed by the program is reduced, and the program speed is improved.

In the method provided by this embodiment, when the program verification of the plurality of memory blocks passes, it is first determined whether the program verification process is the first verification process in the nth program pulse cycle, so as to determine whether the plurality of memory blocks directly pass the verification of the mth data state, or after the bad block is disabled, the verification of the subsequent data state is passed by other memory blocks, so that the verification of other memory blocks on the data state which is not verified is completed in the nth program pulse cycle, thereby avoiding the time consumption of the redundant program pulse cycle phase and improving the program efficiency.

Fig. 7 is a flowchart of an overall scheme provided by an exemplary embodiment of the present application, and as shown in fig. 7, the programming method includes the following steps.

In step 701, the error bit count is verified.

Namely verification check (VFC check), which is used to statistically summarize the verification results of each memory block in the multi-surface programming, for example: in the multi-face programming, four memory blocks of 0/1/2/3 exist for synchronous programming, wherein verification results corresponding to the four memory blocks are counted in the VFC check, for example: the verification result of the data state 3 and block 0 is 0, which indicates that the verification is passed, the verification result of block 1 is 0, which indicates that the verification is passed, the verification result of block 2 is 1, which indicates that the verification is not passed, and the verification result of block 3 is 0, which indicates that the verification is passed. When the selected memory cells fail to verify, the memory block fails to verify; alternatively, when the selected memory cells that fail verification get the number threshold, then the memory block fails verification.

At step 702, it is determined whether all of the plurality of memory blocks pass verification.

For data state 3, it is determined whether all memory cells in the plurality of memory blocks reach the programming threshold voltage corresponding to data state 3, and if all memory cells in the plurality of memory blocks reach the programming threshold voltage corresponding to data state 3, it indicates that all memory blocks pass verification, and if memory cells in the memory blocks do not reach data state 3, it indicates that all memory blocks in the plurality of memory blocks do not pass verification.

Illustratively, the verification result of block 0 for data state 3 is 0, which indicates that the verification is passed, the verification result of block 1 is 0, which indicates that the verification is passed, the verification result of block 2 is 1, which indicates that the verification is not passed, and the verification result of block 3 is 0, which indicates that the verification is passed. Since the verification result of block 2 is 1, a memory block that has failed in verification exists among the plurality of memory blocks.

In step 703, if all of the memory blocks pass verification, it is determined whether the verification process is the first verification of the current programming pulse cycle.

When multiple memory blocks are all verified, there is a possible scenario 1: the plurality of memory blocks normally pass verification directly; possible case 2: in the current programming pulse cycle phase, a plurality of memory blocks disable the bad blocks due to reaching the maximum verification times, and other memory blocks pass the verification of the subsequent data state. In the possible case 1, the plurality of memory blocks directly pass the first verification of the current programming pulse cycle phase, and in the possible case 2, the plurality of memory blocks disable the bad block and pass the subsequent data state verification by other memory blocks in the subsequent verification after the first verification of the current programming pulse cycle phase fails, so that whether the memory block belongs to the possible case 1 or the possible case 2 can be determined according to whether the verification process is the first verification of the current programming pulse cycle phase, and different subsequent processing is performed for the possible case 1 and the possible case 2.

In step 704, if the verification process is the first verification of the current program pulse cycle, the current program pulse cycle is ended, and the next program pulse cycle is entered for verifying the next data state.

If the verification process is the first verification of the current programming pulse cycle phase, that is, corresponding to the above possible case 1, it indicates that the plurality of memory blocks directly pass the first verification of the current programming pulse cycle phase, the current programming pulse cycle phase is ended, and the current data state is incremented by one, and the next programming pulse cycle phase is entered for verifying the next data state.

In step 705, if the verification process is not the first verification of the current program pulse cycle phase, the next data state is verified in the current program pulse cycle phase.

If the verification process is not the first verification of the current programming pulse cycle phase, that is, corresponding to the above possible case 2, it indicates that the plurality of memory blocks are disabled after the first verification of the current programming pulse cycle phase fails and pass the subsequent data state verification by other memory blocks in the subsequent verification, then for other memory blocks, when passing the one-time data state verification, the next data state verification may be passed, so that the next data state verification is continued in the current programming pulse cycle phase.

Illustratively, four memory blocks are programmed and programmed synchronously, in the verification for the data state 3, block 2 fails the verification for the data state 3, and the verification frequency reaches the maximum frequency of 7, so block 2 is disabled, while block 0/1/3 may pass the data state 3 at the verification of the 2 nd time, and in the programming pulse cycle phase of the next 5 times, block 0/1/3 continues to raise the programming pulse voltage 5 times and stays in the verification for the data state 3 all the time, after the verification of the 7 th time, block 2 is disabled, and block 0/1/3 continues to verify the data state 4 at the current programming pulse cycle phase, and when block 0/1/3 passes the verification of the data state 4, since block 0/1/3 is not the first verification at the current programming pulse cycle phase, the data state 5 may continue to be verified at the current programming pulse cycle phase until a subsequent data state of the data state 0/1/3 which has failed the verification, reaches the maximum data state of 0/3 or the subsequent data state of the data state 0/1/3.

In step 706, if there is a storage block in the plurality of storage blocks that is not verified, it is determined whether the verification number reaches the maximum verification number.

When a storage block in a plurality of storage blocks is not verified, the following corresponding situations 1 exist: the plurality of memory blocks are in the process of gradually increasing the programming pulse voltage to reach the programming threshold voltage; case 2: a bad block exists in the plurality of memory blocks, and the programmed threshold voltage cannot be reached.

In order to distinguish the above case 1 from the above case 2, a maximum verification frequency is set for judgment, where when the verification frequency for the current data state does not reach the maximum verification frequency, it indicates that the plurality of memory blocks are in the process of gradually raising the programming pulse voltage to reach the programming threshold voltage, corresponding to the above case 1, and when the verification frequency for the current data state reaches the maximum verification frequency, it indicates that a bad block exists in the plurality of memory blocks, and the programming threshold voltage cannot be reached, corresponding to the above case 2.

Step 707, if the verification frequency does not reach the maximum verification frequency, ending the current programming pulse cycle stage, and entering the next programming pulse cycle stage to verify the current data state.

When the verification times of the plurality of memory blocks for the current data state do not reach the maximum verification times, which corresponds to the above case 1, it indicates that the plurality of memory blocks are in the process of gradually increasing the programming pulse voltage to reach the programming threshold voltage.

Illustratively, the four memory blocks are programmed and program-verified synchronously, the four memory blocks need to pass through two programming pulse cycle phases to reach the programming threshold voltage corresponding to the data state 1, and in the first programming pulse cycle phase, the four memory blocks do not pass through the program-verification aiming at the data state 1, so the four memory blocks continue to enter the second programming pulse cycle phase, and after the programming voltage is increased and applied in the second programming pulse cycle phase, the four memory blocks continue to program and verify the data state 1.

In step 708, if the verification times reach the maximum verification times, the storage blocks which fail verification are disabled.

When the verification times of the plurality of memory blocks for the current data state reach the maximum verification times, that is, corresponding to the above-mentioned case 2, it indicates that a bad block exists in the plurality of memory blocks, and the programming threshold voltage corresponding to the current data state cannot be reached.

Illustratively, four memory blocks are programmed and verified synchronously, the four memory blocks need to pass through two programming pulse cycle phases to reach the programming threshold voltage corresponding to the data state 1, and the maximum verification time for the data state 1 is 3 times, then in the second programming pulse cycle phase, block 0/1/3 passes the verification of the data state 1, while block 2 does not pass the verification of the data state 1, so the third programming pulse cycle phase is continued, while block 2 still does not pass the verification of the data state 1 in the third programming pulse cycle phase, and the verification for the data state 1 reaches the maximum verification time, so block 2 is disabled.

In some embodiments, after disabling the memory blocks which fail to verify, the programming is continued to be completed through the remaining memory blocks, or, after disabling the memory blocks which fail to verify, one memory block is newly determined from the memory cell array for reprogramming the programming contents of the disabled memory block.

Wherein after disabling the memory block that failed verification, the next data state is verified at the current programming pulse cycle phase.

And aiming at other memory blocks which are not forbidden in the current programming pulse cycle stage, continuously verifying the subsequent data state of the verified data state until the memory block cannot pass the verification of a certain subsequent data state or all data states are verified.

Illustratively, block 2 still fails to pass the verification of the data state 1 in the third programming pulse cycle, and the verification for the data state 1 has reached the maximum verification number, so block 2 is disabled, and block 0/1/3 passes the verification for the data state 1, so whether block 0/1/3 passes the verification for the data state 2 in the third programming pulse cycle is continued, and if the data state 2 also passes, whether block 0/1/3 passes the verification for the data state 3 in the third programming pulse cycle is continued, and so on.

Fig. 8 is a schematic structural diagram of a memory according to an embodiment of the present application. As shown in fig. 8, the memory includes a peripheral circuit 800 and a memory cell array 810;

the peripheral circuit 800 is used for writing data into the memory cell array 810 and reading data from the memory cell array 810.

The peripheral circuit 800 includes: voltage generator 802, page buffer/sense amplifier 804, column decoder/Bit Line (BL) driver/806, row decoder/Word Line (WL) driver 808, peripheral logic unit 812, register 814, input-output circuitry 816, and data bus 818. It should be understood that in some examples, additional peripheral circuitry not shown in fig. 8 may also be included.

The page buffer/sense amplifier 804 may be configured to read data from the memory cell array 810 and program (write) data to the memory cell array 810 according to a control signal from the peripheral logic unit 812. In one example, the page buffer/sense amplifier 804 can store a page of program data (write data) to be programmed into one page of the memory cell array 810. In another example, page buffer/sense amplifiers 804 can perform a program verify operation to ensure that data has been properly programmed into the memory cells coupled to the selected word line. In yet another example, page buffer/sense amplifier 804 can also sense low power signals from bit lines representing data bits stored in the memory cells and amplify small voltage swings to recognizable logic levels in a read operation.

The column decoder/bit line driver 806 may be configured to be controlled by the peripheral logic unit 812 and select one or more NAND memory strings by applying the bit line voltages generated from the voltage generator 802.

The row decoder/word line drivers 808 may be configured to be controlled by the peripheral logic cells 812 and select/deselect blocks of the memory cell array 810 and select/deselect word lines of the blocks. The row decoder/word line drivers 808 may also be configured to use the word line voltage (V) generated from the voltage generator 802 _WL ) To drive the word lines. In some embodiments, the row decoder/word line driver 808 may also select/deselect and drive source and drain select gate lines. Illustratively, the row decoder/word line drivers 808 are configured to perform erase operations on memory cells coupled to a selected word line(s).

The voltage generator 802 may be configured to be controlled by the peripheral logic unit 812 and generate a word line voltage (e.g., a read voltage, a program voltage, a pass voltage, a local voltage, a verify voltage, etc.), a bit line voltage, and a source line voltage to be supplied to the memory cell array 810.

A peripheral logic unit 812 may be coupled to each of the peripheral circuits described above and configured to control the operation of each peripheral circuit. The control circuitry shown in fig. 8 above is included in the peripheral logic unit 812.

Registers 814 may be coupled to peripheral logic unit 812 and include status, command, and address registers for storing status information, command operation codes (OP codes), and command addresses for controlling the operation of each peripheral circuit. Input-output circuitry 816 may be coupled to peripheral logic unit 812 and act as a control buffer to buffer and relay control commands received from a host (not shown) to peripheral logic unit 812, and to buffer and relay status information received from peripheral logic unit 812 to the host. The input-output circuitry 816 may also be coupled to the column decoder/bit line drivers 806 via a data bus 818 and act as a data input-output interface and data buffer to buffer data and relay it to or from the memory cell array 810.

It is emphasized that the peripheral circuitry 800 is configured to perform the programming method of the memory provided by the embodiments of the present disclosure on a selected memory cell row of the plurality of memory cell rows.

Fig. 9 is a block diagram of a memory system according to an exemplary embodiment of the present application, and as shown in fig. 9, the memory system 900 includes: one or more memories 910 and, optionally,

a memory controller 920 coupled to the memory 910 and configured to control the memory 910.

The storage system 900 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual Reality (VR) device, augmented Reality (AR) device, or any other suitable electronic device having storage therein.

Optionally, the storage system 900 may include a host and a storage subsystem having one or more memories 910 and a memory controller 920. The host may be a processor (e.g., a Central Processing Unit (CPU)) or a system on chip (SoC) (e.g., an Application Processor (AP)) of the electronic device. The host may be configured to send data to the memory 910. Alternatively, the host may be configured to receive data from the memory 910.

According to some embodiments, memory controller 920 is also coupled to a host. Memory controller 920 may manage data stored in memory 910 and communicate with a host.

In some implementations, the memory controller 920 is designed for operation in low duty cycle environments, such as a Secure Digital (SD) card, compact Flash (CF) card, universal Serial Bus (USB) flash drive, or other media for use in electronic devices such as personal computers, digital cameras, mobile phones, and so forth.

In some implementations, the memory controller 920 is designed for operation in a high duty cycle environment Solid State Drive (SSD) or embedded multimedia card (eMMC) that serves as a data storage and enterprise storage array for mobile devices such as smart phones, tablet computers, laptop computers, and the like.

The memory controller 920 may be configured to control operations of the memory 910, such as read, erase, and program operations. The memory controller 920 may also be configured to manage various functions with respect to data stored or to be stored in the memory 910, including but not limited to bad block management, garbage collection, logical to physical address translation, wear leveling, and the like. In some embodiments, memory controller 920 is also configured to process Error Correction Codes (ECC) with respect to data read from memory 910 or written to memory 910.

Memory controller 920 may also perform any other suitable functions, such as formatting memory 910. The memory controller 920 may communicate with external devices according to a particular communication protocol.

The memory controller 920 and the one or more memories 910 may be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Storage (UFS) package or an eMMC package). That is, the memory system 900 can be implemented and packaged into different types of terminal electronics.

Illustratively, the memory controller 920 and the single memory 910 may be integrated into a memory card. The memory card may include a PC card (PCMCIA), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), a UFS, and the like. The memory card may also include a memory card connector that couples the memory card with a host.

Illustratively, the memory controller 920 and the plurality of memories 910 may be integrated into a Solid State Drive (SSD). In some implementations, the storage capacity and/or operating speed of the solid state drive is greater than the storage capacity and/or operating speed of the memory card.

It is understood that the memory controller 920 may perform a programming method of the memory as provided in any of the embodiments of the present disclosure.

Embodiments of the present application provide a control circuit, which includes a programmable logic circuit and/or program instructions, and which can be used to implement the programming method of the memory provided in the foregoing embodiments of the present application.

Illustratively, the memory 910 shown in FIG. 9 includes: the memory array unit comprises a plurality of memory blocks, each memory block comprises a memory unit, and the peripheral logic unit comprises a control circuit;

In an optional embodiment, the control circuit is further configured to obtain a programming threshold voltage corresponding to the (m + 1) th data state in the nth programming pulse cycle phase; determining programming pulse voltages corresponding to other memory blocks except the disabled memory block in the plurality of memory blocks; and comparing the programming pulse voltage with a programming threshold voltage corresponding to the (m + 1) th data state, and verifying the (m + 1) th data state based on the comparison condition of the programming pulse voltage and the programming threshold voltage corresponding to the (m + 1) th data state.

In an optional embodiment, the control circuit is further configured to verify the mth data state in the (n + 1) th program pulse cycle phase in response to the plurality of memory blocks having a memory block program verify failure and the verification count for the mth data state not reaching the maximum verification count.

In an optional embodiment, the control circuitry is further configured to end the program pulse cycle in response to the (m + 1) th data state reaching the data state verify threshold.

In summary, in the memory provided in this embodiment, in the program verification process, when a bad block is disabled after the maximum verification number, the program verification is performed after the program is performed without entering the next program pulse cycle stage, and the program verification of the subsequent data state is performed directly in the current program pulse cycle stage, so that the efficiency of the program verification is improved, the increase of the number of program pulse cycle stages is avoided, the time consumed by the program is reduced, and the program speed is improved.

Embodiments of the present application provide a computer-readable storage medium, in which instructions are stored, and when the instructions are executed on a control circuit, the instructions implement the programming method of the memory provided in the foregoing embodiments of the present application.

In this application, the terms "first" and "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance. The term "at least one" means one or more, and the term "plurality" means two or more, unless expressly defined otherwise.

The term "and/or" in this application is only one kind of association relationship describing the associated object, and means that there may be three kinds of relationships, for example, a and/or B, which may mean: a exists alone, A and B exist simultaneously, and B exists alone. In addition, the character "/" herein generally indicates that the former and latter related objects are in an "or" relationship.

The above description is only exemplary of the application and should not be taken as limiting the application, and any modifications, equivalents, improvements and the like that are made within the spirit and principle of the application should be included in the protection scope of the application.

Claims

1. A method of programming a memory, the method comprising:

in the programming verification process of programming a plurality of memory blocks, obtaining the programming verification result of the m-th data state of the plurality of memory blocks in the nth programming pulse cycle stage, wherein n and m are positive integers;

in response to the presence of a memory block with program verify failure among the plurality of memory blocks and the number of verify times for the mth data state reaching the maximum number of verify times, disabling the memory block with program verify failure and verifying the m +1 th data state in the nth program pulse cycle phase.

2. The method of claim 1, wherein verifying the (m + 1) th data state during the nth programming pulse cycle comprises:

determining programming pulse voltages corresponding to other memory blocks except the disabled memory block in the plurality of memory blocks;

3. The method of claim 1, further comprising:

in response to the memory block which fails in the program verification existing in the plurality of memory blocks and the verification time of the mth data state does not reach the maximum verification time, verifying the mth data state in the (n + 1) th programming pulse cycle phase.

4. The method of claim 1, further comprising:

5. The method of claim 1, further comprising:

in response to the plurality of memory blocks program verifying passing and a current program verify process being a first verify process in the nth program pulse cycle phase, verifying the m +1 th data state in the n +1 th program pulse cycle phase.

6. The method of claim 5, wherein verifying the (m + 1) th data state during the (n + 1) th programming pulse cycle comprises:

acquiring a data state verification threshold, wherein the data state verification threshold is used for representing the total number of data states required to be programmed and reached by the plurality of memory blocks;

7. The method of claim 6, further comprising:

8. The method of any of claims 1 to 7, further comprising:

9. The method of any of claims 1 to 7, further comprising:

10. A memory, the memory comprising: the memory array unit comprises a plurality of memory blocks, each memory block comprises a memory unit, and the peripheral logic unit comprises a control circuit;

the control circuit is configured to obtain a program verification result of the multiple memory blocks on the mth data state in the nth program pulse cycle stage in a program verification process of synchronously programming the multiple memory blocks, wherein n and m are positive integers;

the control circuit is further configured to respond to the memory cells with program verification failure in the plurality of memory blocks and the verification times of the mth data state reach the maximum verification times, disable the memory blocks with program verification failure and verify the (m + 1) th data state in the nth program pulse cycle phase.

11. The method of claim 10, wherein the control circuit is further configured to obtain a programmed threshold voltage corresponding to the (m + 1) th data state during the nth programming pulse cycle; determining programming pulse voltages corresponding to other memory blocks except the forbidden memory block in the plurality of memory blocks; comparing the programming pulse voltage with a programming threshold voltage corresponding to the (m + 1) th data state; and verifying the (m + 1) th data state based on the comparison condition of the programming pulse voltage and the programming threshold voltage corresponding to the (m + 1) th data state.

12. The memory of claim 10, wherein the control circuit is further configured to verify the mth data state at the (n + 1) th program pulse cycle phase in response to a memory block of the plurality of memory blocks having failed program verification and the verification count for the mth data state not reaching the maximum verification count.

13. The memory of claim 10, wherein the control circuit is further configured to verify a subsequent data state of the current data state during the nth program pulse cycle in response to the plurality of memory blocks passing program verification and a current program verify process being a non-first verify process during the nth program pulse cycle.

14. The memory of claim 10, wherein the control circuit is further configured to verify the m +1 th data state in the n +1 th program pulse cycle phase in response to the plurality of memory blocks program verify passing and a current program verify process being a first verify process in the n-th program pulse cycle phase.

15. The memory of claim 14, wherein the control circuit is further configured to obtain a data state verify threshold value, the data state verify threshold value being used to represent a total number of data states required to be programmed into the plurality of memory blocks; in response to the m +1 th data state not reaching the data state verify threshold, the m +1 th data state is verified in the n +1 th program pulse cycle phase.

16. The memory of claim 15, wherein the control circuit is further configured to end the program pulse cycle in response to the m +1 th data state reaching the data state verify threshold.

17. The memory of any of claims 10 to 16, wherein the control circuit is further configured to determine that a memory block that fails program verification exists in the plurality of memory blocks in response to a memory block that does not reach a program threshold voltage corresponding to the mth data state being present in the plurality of memory blocks; determining that the plurality of memory blocks are program verified in response to the plurality of memory blocks reaching the program threshold voltage corresponding to the mth data state.

18. The memory of any of claims 10 to 16, wherein the control circuit is further configured to determine that the target memory block of the plurality of memory blocks has failed program verification in response to memory cells of the target memory block not reaching a program threshold voltage corresponding to the mth data state after programming.

19. A storage system, comprising:

one or more memories as claimed in any one of claims 10 to 18, and,

a memory controller coupled to the memory and configured to control the memory.