CN115333538A - Signal detection circuit - Google Patents

Abstract

The invention discloses a signal detection circuit, which comprises an input switch circuit, an amplitude detection circuit, a clock generation circuit and an integration circuit. The input switch circuit receives a reference voltage and an input voltage, and is controlled by the switching signal group to selectively output the reference voltage or the input voltage. The amplitude detection circuit detects the output of the input switch circuit to correspondingly generate an amplitude voltage. The clock generating circuit generates a switching signal group for controlling the input switch circuit to alternately enter a first stage and a second stage, and the input switch circuit is controlled to output the reference voltage in the first stage and output the input voltage in the second stage. The integration circuit is configured to take the amplitude voltage as an input and accumulate the amplitude voltage, and generate an integration voltage corresponding to the accumulation result within a predetermined time interval. The predetermined time interval includes a plurality of cycles in which the first phase and the second phase are cycled.

Description

Signal detection circuit

Technical Field

The present invention relates to a signal detection circuit, and more particularly, to a signal detection circuit capable of reducing the influence of process shift.

Background

In the conventional signal detection circuit, in order to detect the magnitude of a signal to be detected, two independent current paths are often provided for the signal to be detected and a reference voltage, and the signal magnitude is compared by a comparator after being filtered into direct current voltages by an amplitude detector.

However, in the above-mentioned structure, when two independent current paths are fabricated, the error of the comparator after comparison is large due to the difference of the process offset.

Therefore, it is an important issue to be solved in the art how to overcome the above-mentioned drawbacks by improving the circuit design to reduce the influence of process shift.

Disclosure of Invention

The present invention is directed to a signal detection circuit capable of reducing the influence of process drift.

In order to solve the above technical problem, an embodiment of the present invention provides a signal detection circuit, which includes an input switch circuit, an amplitude detection circuit, a clock generation circuit, and an integration circuit. The input switch circuit is configured to receive a reference voltage and an input voltage, and is controlled by a switching signal group to selectively output the reference voltage or the input voltage. The amplitude detection circuit is configured to detect an output of the input switch circuit to correspondingly generate an amplitude voltage. The clock generation circuit is configured to generate the switching signal group. The switching signal group is used for controlling the input switch circuit to alternately enter a first stage and a second stage, and the input switch circuit is controlled to output the reference voltage in the first stage and output the input voltage in the second stage. The integrating circuit is configured to take the amplitude voltage as input and accumulate the amplitude voltage, and generate an integrating voltage corresponding to an accumulation result in a preset time interval. The predetermined time interval includes a plurality of cycles in which the first phase and the second phase are cycled.

The signal detection circuit provided by the invention has the beneficial effects that the input switch circuit is used for selecting to enable the input signal and the reference voltage to enter the amplitude detection circuit and the integrating circuit at different stages, and the input signal and the reference voltage experience the same circuit offset because of sharing a rear-end circuit, so that the error caused by process bias when different paths are adopted can be reduced.

For a better understanding of the features and technical aspects of the present invention, reference should be made to the following detailed description and accompanying drawings, which are provided for purposes of illustration and description, and are not intended to limit the invention.

Drawings

Fig. 1 is a functional block diagram of a signal detection circuit according to an embodiment of the present invention.

Fig. 2 is a circuit layout diagram of a signal detection circuit according to an embodiment of the invention.

Fig. 3 is a first signal timing diagram of the signal detection circuit according to the embodiment of the invention.

FIG. 4 is a second signal timing diagram of the signal detection circuit according to the embodiment of the present invention.

Fig. 5 is a circuit layout diagram of a signal detection circuit according to another embodiment of the invention.

Detailed Description

The following description is provided for the embodiments of the present invention relating to a "signal detection circuit" by specific embodiments, and those skilled in the art can understand the advantages and effects of the present invention from the disclosure of the present specification. The invention is capable of other and different embodiments and its several details are capable of modifications and various changes in detail without departing from the spirit and scope of the invention. It should be noted that the drawings of the present invention are only for a simple schematic description and are not drawn to actual dimensions. The following examples further illustrate the related art of the present invention in detail, but the disclosure is not intended to limit the scope of the present invention. In addition, the term "or" as used herein should be taken to include any one or combination of more of the associated listed items as the case may be.

Fig. 1 is a functional block diagram of a signal detection circuit according to an embodiment of the present invention. Referring to fig. 1, an embodiment of the invention provides a signal detection circuit 1, which includes an input switch circuit 10, an amplitude detection circuit 12, a clock generation circuit 14, and an integration circuit 16.

The input switch circuit 10 is configured to receive a reference voltage VREF and an input voltage VIN, and is controlled by a switching signal set SS to selectively output the reference voltage VREF or the input voltage VIN.

Referring to fig. 2, fig. 2 is a circuit layout diagram of a signal detection circuit according to an embodiment of the invention. For example, the reference voltage VREF is a pair of differential reference voltages including a first reference voltage VREFP and a second reference voltage VREFN, and the input voltage VIN is a pair of differential input voltages including a first input voltage VINP and a second input voltage VINN.

In the embodiment of fig. 2, in response to the input voltage VIN being a differential signal, the input switch circuit 10 may be, for example, a multiplexer, which may include, for simplification, a first switch S1, a second switch S2, a third switch S3 and a fourth switch S4 as shown in fig. 2, and has a first output o1 and a second output o2. The first switch S1, the second switch S2, the third switch S3 and the fourth switch S4 may be N-type or P-type Metal Oxide Semiconductor Field Effect Transistors (MOSFETs), respectively, but the invention is not limited thereto.

The first switch S1 is connected to the first output terminal o1 and receives the first reference voltage VREFP, the second switch S2 is connected to the first output terminal o1 and receives the first input voltage VINP, the third switch S3 is connected to the second output terminal o2 and receives the second input voltage VINN, and the fourth switch S4 is connected to the second input terminal o2 and receives the second reference voltage VREFN.

Referring to fig. 1 again, the amplitude detection circuit 12 is used for detecting the output of the input switch circuit 10 to correspondingly generate the amplitude voltage VA. For example, the amplitude detection circuit 12 can be the rectifier 120 of fig. 2, or any circuit capable of converting the input signal into a high voltage or a low voltage according to the magnitude of the input signal, but the invention is not limited thereto.

As shown in fig. 2, the rectifier 120 may have a first detection output do1 and a second detection output do2, and is configured to generate an amplitude voltage Va including a first amplitude voltage Va1 and a second amplitude voltage Va2 at the first detection output do1 and the second detection output do2 corresponding to the outputs of the first output o1 and the second output o2.

On the other hand, the clock generation circuit 14 is used to generate the switching signal group SS (as shown in fig. 1). The switching signal group SS is mainly used to control the input switch circuit 10 to alternately enter the first stage and the second stage. In detail, the input switch circuit 10 is controlled to output the reference voltage VREF in the first phase and output the input voltage VIN in the second phase.

In addition, when the above-mentioned switching manner is applied to the embodiment of fig. 2, the switching signal set SS may include a first switching signal Φ 1 and a second switching signal Φ 2, and the first switching signal Φ 1 is used for controlling the first switch S1 and the fourth switch S4 to be turned on in the first stage, and the second switching signal Φ 2 is used for controlling the second switch S2 and the third switch S3 to be turned on in the second stage, so that the input switch circuit 10 respectively outputs the first reference voltage VREFP and the second reference voltage VREFN at the first output end o1 and the second output end o2 in the first stage, and respectively outputs the first input voltage VINP and the second input voltage VINN at the first output end o1 and the second output end o2 in the second stage.

Referring to fig. 1 again, the integrating circuit 16 is configured to integrate the amplitude voltage VA as an input and generate an integrating voltage VINT corresponding to the integration result within a predetermined time interval. The predetermined time interval covers a plurality of cycles taking the first stage and the second stage as cycles.

For example, the integrating circuit 16 may perform the subtraction after sampling the amplitude voltage VA in the first stage (generated according to the reference voltage VREF) and the amplitude voltage VA in the second stage (generated according to the input voltage VIN) in a single cycle. Therefore, after a plurality of cycles corresponding to the predetermined time interval, the input voltage VIN can be determined to be higher or lower than the reference voltage VREF according to the accumulated integrated voltage VINT.

In this manner, referring to fig. 2, integrating circuit 16 may include sampling circuit 160 and integrating amplifier 162. The sampling circuit 160 is configured to sample the first amplitude voltage Va1 and the second amplitude voltage Va2 in the first phase.

As shown in fig. 2, the sampling circuit 160 may include a first sampling capacitor C1, a second sampling capacitor C2, a fifth switch S5, a sixth switch S6, a seventh switch S7, and an eighth switch S8. The fifth switch S5, the sixth switch S6, the seventh switch S7 and the eighth switch S8 may be respectively an N-type or a P-type Metal Oxide Semiconductor Field Effect Transistor (MOSFET), but the invention is not limited thereto.

The first sampling capacitor C1 is connected between the first detection output terminal do1 and the first node N1, and the second sampling capacitor C2 is connected between the second detection output terminal do2 and the second node N2. One end of the fifth switch S5 is connected to the first node N1, and the other end receives the common mode voltage Vcm. One end of the sixth switch S6 is connected to the second node N2, and the other end receives the common mode voltage Vcm. The seventh switch S7 is connected between the first node N1 and the third node N3, and the eighth switch S8 is connected between the second node N2 and the fourth node N4.

On the other hand, the integrating amplifier 162 holds the first amplitude voltage Va1 and the second amplitude voltage Va2 sampled by the sampling circuit 160 in the second stage to integrate them.

Accordingly, as shown in fig. 2, the integrating amplifier 162 may include a fully differential amplifier FDA, a first feedback capacitor Cfb1 and a second feedback capacitor Cfb2.

The fully differential amplifier FDA has a non-inverting input terminal (left + terminal), an inverting input terminal (left-terminal), an inverting output terminal (right + terminal), and a non-inverting output terminal (right-terminal), wherein the non-inverting input terminal is connected to the third node N3, and the inverting input terminal is connected to the fourth node N4. The first feedback capacitor Cfb1 is connected between the non-inverting input terminal and the inverting output terminal, and the second feedback capacitor Cfb2 is connected between the inverting input terminal and the non-inverting output terminal.

As shown in fig. 2, the fifth switch S5 and the sixth switch S6 are controlled by the first switching signal Φ 1 to be turned on in the first stage and turned off in the second stage, and the seventh switch S7 and the eighth switch S8 are controlled by the second switching signal Φ 2 to be turned on in the second stage and turned off in the first stage. In the embodiment of the present invention, the integrating circuit 16 may be replaced by a low-pass filter or a capacitor, but the present invention is not limited thereto.

The detection mechanism of the signal detection circuit of fig. 2 will be described with reference to fig. 3. Fig. 3 is a first signal timing diagram of the signal detection circuit according to the embodiment of the invention. As shown, a timing chart including a time point t1 to a time point t9 is shown. In the embodiment of fig. 3, the reference voltage VREF is smaller than the input voltage VIN in the interval from the time point t1 to the time point t5, and is larger than the input voltage VIN in the interval from the time point t5 to the time point t 9.

In the following description, the time point t2 is taken as an initial point, and a first stage is entered between the time points t2 and t3, where the first switching signal Φ 1 is at a high potential, the second switching signal Φ 2 is at a low potential, which means that the first switch S1, the fourth switch S4, the fifth switch S5, and the sixth switch S6 are all turned on, the second switch S2, the third switch S3, the seventh switch S7, and the eighth switch S8 are all turned off, and at this time, the reference voltage VREF is input to the rectifier 120, and the amplitude voltage VA at the low potential is generated. For the amplitude voltage VA, the first sampling capacitor C1 samples the difference between the first amplitude voltage VA1 and the common mode voltage Vcm, and the second sampling capacitor C2 samples the difference between the second amplitude voltage VA2 and the common mode voltage Vcm, so that the amplitude voltage VA can be sampled.

Then, during a period from time t3 to time t4, a second phase is entered, where the first switching signal Φ 1 is at a low potential, the second switching signal Φ 2 is at a high potential, which means that the first switch S1, the fourth switch S4, the fifth switch S5, and the sixth switch S6 are all turned off, the second switch S2, the third switch S3, the seventh switch S7, and the eighth switch S8 are all turned on, and at this time, the input voltage VIN is input into the rectifier 120 to generate an amplitude voltage VA at a high potential. The high-level amplitude voltage VA is subtracted from the low-level amplitude voltage VA sampled in the first stage, and the subtracted result is amplified by the fully differential amplifier FDA and then retained in the first feedback capacitor Cfb1 and the second feedback capacitor Cfb2, so as to generate the integrated voltage VINT.

As can be seen from fig. 3, since the reference voltage VREF is smaller than the input voltage VIN in the interval from time t2 to time t5, the integral voltage VINT gradually decreases from time t2 to time t5, and accordingly, after a plurality of cycles that use the first and second phases as cycles, for example, at time t5, the integral voltage VINT can be output as an accumulation result, so as to determine the magnitude relationship between the reference voltage VREF and the input voltage VIN.

On the other hand, since the reference voltage VREF is greater than the input voltage VIN in the interval from time t6 to t9, the integrated voltage VINT gradually increases from time t6 to t9, and the increased integrated voltage VINT may be output as an integration result after a plurality of cycles.

The integrating amplifier 162 of fig. 2 further includes a first reset switch Sr1, a second reset switch Sr2, and a third reset switch Sr3. The first reset switch Sr1 is connected between the non-inverting input terminal and the inverting output terminal of the fully differential amplifier FDA, the second reset switch Sr2 is connected between the inverting input terminal and the non-inverting output terminal of the fully differential amplifier FDA, and the third reset switch Sr3 is connected between the third node N3 and the fourth node N4.

Accordingly, the clock generating circuit 14 also generates a reset signal Rst to control the first reset switch Sr1, the second reset switch Sr2 and the third reset switch Sr3 to be turned on during a reset time interval before and after the predetermined time interval and to be turned off during the predetermined time interval. For example, the reset time interval may be between time points t1 and t2 and t5 and t6 of fig. 3, and the predetermined time interval may be between time points t2 and t5, for example. After the first, second, and third reset switches Sr1, sr2, and Sr3 are turned on, the held integrated voltage VINT is reset to perform the detection again.

Referring to fig. 4, a detection mechanism of the signal detection circuit of fig. 2 will be described in another embodiment. FIG. 4 is a second signal timing diagram of the signal detection circuit according to the embodiment of the invention. As shown, a timing chart including a time point t1 to a time point t9 is shown. In the embodiment of fig. 4, the reference voltage VREF is not changed, and the input voltage is smaller than the reference voltage VREF in the interval from time t1 to t5 and larger than the reference voltage VREF in the interval from time t5 to t 9.

In the following, the time point t2 is taken as a starting point, and the first stage is started between the time points t2 and t3, where the first switching signal Φ 1 is at a high potential, the second switching signal Φ 2 is at a low potential, which means that the first switch S1, the fourth switch S4, the fifth switch S5, and the sixth switch S6 are all turned on, the second switch S2, the third switch S3, the seventh switch S7, and the eighth switch S8 are all turned off, and at this time, the reference voltage VREF is input to the rectifier 120, so as to generate the amplitude voltage VA at a high potential. For the amplitude voltage VA, the first sampling capacitor C1 samples the difference between the first amplitude voltage VA1 and the common mode voltage Vcm, and the second sampling capacitor C2 samples the difference between the second amplitude voltage VA2 and the common mode voltage Vcm, thereby sampling the amplitude voltage VA.

Then, during a period from time t3 to time t4, a second phase is entered, where the first switching signal Φ 1 is at a low potential, the second switching signal Φ 2 is at a high potential, which means that the first switch S1, the fourth switch S4, the fifth switch S5, and the sixth switch S6 are all turned off, the second switch S2, the third switch S3, the seventh switch S7, and the eighth switch S8 are all turned on, and at this time, the input voltage VIN is input into the rectifier 120 to generate an amplitude voltage VA at a low potential. The low-level amplitude voltage VA is subtracted from the high-level amplitude voltage VA sampled in the first stage, and the subtracted result is amplified by the fully differential amplifier FDA and then retained in the first feedback capacitor Cfb1 and the second feedback capacitor Cfb2, so as to generate the integrated voltage VINT.

As can be seen from fig. 4, since the reference voltage VREF is greater than the input voltage VIN in the interval from time t2 to time t5, the integral voltage VINT gradually increases from time t2 to time t5, and accordingly, after a plurality of cycles in which the first phase and the second phase are cyclic, for example, at time t5, the integral voltage VINT can be output as an accumulation result, so as to determine the magnitude relationship between the reference voltage VREF and the input voltage VIN.

Therefore, the above embodiment uses the input switch circuit 10 to select the input voltage VIN and the reference voltage VREF to enter the amplitude detection circuit 12 and the integration circuit 16 at different stages, and since the input voltage VIN and the reference voltage VREF will experience the same circuit offset due to the shared back-end circuit, the error caused by the process bias when different paths are adopted can be reduced.

In some embodiments, the signal detection circuit 1 further optionally includes a comparator circuit 18 configured to receive the integration voltage VINT (i.e., the voltages at the inverted output terminal and the non-inverted output terminal in fig. 2) generated by the integration circuit 16 through a first input terminal and a second input terminal thereof and compare the received integration voltage VINT to generate a comparison result signal Vcomp as an accumulation result. Accordingly, in this embodiment, the clock generating circuit 14 is further configured to generate the comparison clock signal comclk to control the comparator circuit 18 to generate and output the comparison result signal Vcomp at the end of the predetermined time interval (e.g., time points t2 to t5 in fig. 3 and 4).

Referring to fig. 5, fig. 5 is a circuit layout diagram of a signal detection circuit according to another embodiment of the invention. In another embodiment, the integrating amplifier 162 further optionally includes a chopper circuit (chopping circuit), such as a first chopper circuit CC1 and a second chopper circuit CC2 respectively connected to the input and output of the fully differential amplifier FDA, which may be designed to be activated at a specific time. The first chopper circuit CC1 has two input terminals connected to the third node N3 and the fourth node N4, respectively, and two output terminals connected to the non-inverting input terminal (left + terminal) and the inverting input terminal (left-terminal), respectively. The second chopper circuit CC2 has two input terminals connected to the inverting output terminal (right-side terminal) and the non-inverting output terminal (right-side + terminal), respectively, and two output terminals connected to the first input terminal and the second input terminal of the comparator circuit 18, respectively.

For example, the first chopper circuit CC1 and the second chopper circuit CC2 may operate together for a predetermined number of cycles, so that the comparator circuit 18 may cancel the offset on the signal transmission path, and optimize the comparison result signal Vcomp.

For example, the offset may be an offset generated by the fully differential amplifier FDA, and the specific number of the plurality of cycles may be 4 cycles. In a first interval of 4 cycles, for example, the first two cycles, the first chopper circuit CC1 and the second chopper circuit CC2 may be configured to enable the comparator circuit 18 to compare the signal at the inverted output terminal (right-side terminal) with the signal at the non-inverted output terminal (right + terminal) according to the first switching signal Φ 1 and the second switching signal Φ 2, and in a second interval of 4 cycles, for example, the second two cycles, the first chopper circuit CC1 and the second chopper circuit CC2 may be configured to enable the comparator circuit 18 to compare the signal at the non-inverted output terminal (right + terminal) with the signal at the inverted output terminal (right-side terminal) according to the first switching signal Φ 1 and the second switching signal Φ 2, so as to achieve the effect of averagely canceling the offset between the two output terminals and optimize the comparison result signal Vcomp.

The beneficial effects of the embodiment:

the signal detection circuit provided by the invention has the beneficial effects that the input switch circuit is used for selecting the input signal and the reference voltage to enter the amplitude detection circuit and the integrating circuit at different stages, and the input signal and the reference voltage experience the same circuit offset due to the sharing of the circuit at the rear end, so that the error caused by process bias when different paths are adopted can be reduced.

On the other hand, the signal detection circuit provided by the invention can selectively comprise a comparator circuit and a chopper circuit so as to realize the effect of averagely offsetting the offset of the two output ends and generate an optimized comparison result signal Vcomp as an accumulation result.

The disclosure above is only a preferred embodiment of the present invention, and the claimed patent protection scope is not limited thereto, so that all the technical changes equivalent to the description and drawings of the present invention are within the claimed patent protection scope.

Description of reference numerals:

1: signal detection circuit

10: input switch circuit

12: amplitude detection circuit

120: rectifier

14: clock generation circuit

16: integrating circuit

18: comparator circuit

160: sampling circuit

162: integrating amplifier

C1: first sampling capacitor

C2: second sampling capacitor

CC1: first chopper circuit

And (C2): second chopper circuit

Cfb1: a first feedback capacitor

Cfb2: second feedback capacitor

comclk: comparing clock signals

do1: first detection output end

And do2: second detection output terminal

FDA: fully differential amplifier

N1: first node

N2: second node

N3: third node

N4: the fourth node

o1: a first output terminal

o2: second output terminal

Rst: reset signal

S1: first switch

S2: second switch

S3: third switch

S4: the fourth switch

S5: the fifth switch

S6: sixth switch

S7: seventh switch

S8: the eighth switch

Sr1: first reset switch

Sr2: second reset switch

Sr3: third reset switch

And SS: switching signal group

t1 to t9: time of day

VA: amplitude voltage

Va1: voltage of first amplitude

Va2: voltage of second amplitude

Vcm: common mode voltage

Vcomp: comparing the resultant signals

VIN: input voltage

VINN: second input voltage

And (3) VINP: first input voltage

VINT: integral voltage

VREF: reference voltage

VREFN: second reference voltage

VREFP: a first reference voltage

Phi 1: first switching signal

Phi 2: second switching signal

Claims (10)

1. A signal detection circuit, comprising:

an input switch circuit configured to receive a reference voltage and an input voltage and controlled by a switching signal group to selectively output the reference voltage or the input voltage;

an amplitude detection circuit configured to detect an output of the input switch circuit to correspondingly generate an amplitude voltage;

a clock generating circuit configured to generate the switching signal group, wherein the switching signal group is used to control the input switch circuit to alternately enter a first phase and a second phase, and the input switch circuit is controlled to output the reference voltage in the first phase and output the input voltage in the second phase;

an integrating circuit configured to take the amplitude voltage as an input and accumulate the amplitude voltage, and generate an integrating voltage corresponding to an accumulation result within a predetermined time interval;

wherein the predetermined time interval includes at least one cycle that is cycled through the first phase and the second phase.

2. The signal detection circuit of claim 1, wherein the reference voltages are a pair of differential reference voltages comprising a first reference voltage and a second reference voltage, and the input voltages are a pair of differential input voltages comprising a first input voltage and a second input voltage.

3. The signal detection circuit of claim 2, wherein the input switch circuit has a first output terminal and a second output terminal, and comprises:

a first switch connected to the first output terminal and receiving the first reference voltage;

the second switch is connected to the first output end and receives the first input voltage;

a third switch connected to the second output terminal and receiving the second input voltage;

a fourth switch connected to the second input terminal and receiving the second reference voltage.

4. The signal detection circuit of claim 3, wherein the switching signal set comprises a first switching signal and a second switching signal, and the first switching signal is used to control the first switch and the fourth switch to be turned on in the first phase, and the second switching signal is used to control the second switch and the fourth switch to be turned on in the second phase, so that the input switch circuit outputs the first reference voltage and the second reference voltage at the first output terminal and the second output terminal respectively in the first phase, and outputs the first input voltage and the second input voltage at the first output terminal and the second output terminal respectively in the second phase.

5. The signal detection circuit of claim 4, wherein the amplitude detection circuit has a first detection output and a second detection output, and is configured to generate the amplitude voltages comprising a first amplitude voltage and a second amplitude voltage at the first detection output and the second detection output corresponding to the outputs of the first output and the second output, respectively,

wherein the integration circuit comprises:

a sampling circuit configured to sample the first amplitude voltage and the second amplitude voltage at the first stage; and

an integrating amplifier configured to hold the first amplitude voltage and the second amplitude voltage sampled by the sampling circuit for accumulation respectively in the second stage.

6. The signal detection circuit of claim 5, wherein the sampling circuit comprises:

the first sampling capacitor is connected between the first detection output end and a first node;

the second sampling capacitor is connected between the second detection output end and a second node;

a fifth switch, one end of which is connected to the first node and the other end of which receives a common mode voltage;

one end of the sixth switch is connected to the second node, and the other end of the sixth switch receives the common-mode voltage;

a seventh switch connected between the first node and a third node; and

an eighth switch connected between the second node and a fourth node;

wherein the integrating amplifier comprises:

a fully differential amplifier having a non-inverting input terminal, an inverting output terminal, and a non-inverting output terminal, wherein the non-inverting input terminal is connected to the third node, and the inverting input terminal is connected to the fourth node;

the first feedback capacitor is connected between the non-inverting input end and the inverting output end; and

and the second feedback capacitor is connected between the inverting input end and the non-inverting output end.

7. The signal detection circuit of claim 6, wherein the fifth switch and the sixth switch are configured to be controlled by the first switching signal to turn on during the first phase and turn off during the second phase, and wherein the seventh switch and the eighth switch are configured to be controlled by the second switching signal to turn on during the second phase and turn off during the first phase.

8. The signal detection circuit of claim 7, wherein the integrating amplifier further comprises:

the first reset switch is connected between the non-inversion input end and the inversion output end;

the second reset switch is connected between the reverse input end and the non-reverse output end; and

a third reset switch connected between the third node and the fourth node,

the clock generation circuit is also configured to generate a reset signal to control the first reset switch, the second reset switch and the third reset switch to be turned on in a reset time interval before and after the preset time interval and to be turned off in the preset time interval.

9. The signal detection circuit of claim 8, further comprising a comparator circuit configured to receive and compare the voltages of the inverted output terminal and the non-inverted output terminal through a first input terminal and a second input terminal of the comparator circuit, respectively, to generate a comparison result signal as the accumulation result, wherein the clock generation circuit is further configured to generate a comparison clock signal to control the comparator circuit to generate and output the comparison result signal at the end of the predetermined time interval.

10. The signal detection circuit of claim 9, further comprising:

a first chopper circuit having two input terminals connected to the third node and the fourth node, respectively, and two output terminals connected to the non-inverting input terminal and the inverting input terminal, respectively;

a second chopper circuit having two input terminals connected to the inverting output terminal and the non-inverting output terminal, respectively, and two output terminals connected to the first input terminal and the second input terminal of the comparator circuit, respectively,

wherein the first chopper circuit and the second chopper circuit are configured to cause the comparator circuit to compare the voltage of the inverted output terminal with the voltage of the non-inverted output terminal for a first interval during a predetermined number of the at least one period, and to cause the comparator circuit to convert to compare the voltage of the non-inverted output terminal with the voltage of the inverted output terminal for a second interval during the predetermined number of the at least one period.

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