CN115333538A - Signal detection circuit - Google Patents

Abstract

The invention discloses a signal detection circuit, which comprises an input switch circuit, an amplitude detection circuit, a clock generation circuit and an integration circuit. The input switch circuit receives the reference voltage and the input voltage, and is controlled by the switch signal group to selectively output the reference voltage or the input voltage. The amplitude detection circuit detects the output of the input switch circuit to generate an amplitude voltage correspondingly. The clock generation circuit generates a switch signal group for controlling the input switch circuit to alternately enter the first stage and the second stage, and the input switch circuit is controlled to output the reference voltage in the first stage and output the input voltage in the second stage. The integrating circuit is configured to take the amplitude voltage as an input and accumulate, and generate an integrated voltage corresponding to the accumulated result within a predetermined time interval. Wherein, the predetermined time interval includes a plurality of cycles with the first stage and the second stage as a cycle.

Description

signal detection circuit

technical field

The invention relates to a signal detection circuit, in particular to a signal detection circuit capable of reducing the influence of process deviation.

Background technique

In the existing detection signal circuit, in order to detect the magnitude of the signal to be measured, two independent current paths are often set up for the signal to be measured and the reference voltage, which are filtered into DC voltages by the amplitude detector, and then compared by a comparator signal size.

However, in the above architecture, when manufacturing two independent current paths, the difference in process offset often causes a problem that the comparator has a relatively large error after comparison.

Therefore, how to reduce the influence of process skew by improving the circuit design to overcome the above defects has become one of the important issues to be solved in this field.

Contents of the invention

The technical problem to be solved by the present invention is to provide a signal detection circuit capable of reducing the influence of manufacturing process deviation in view of the deficiencies of the prior art.

In order to solve the above technical problems, a technical solution adopted by the present invention is to provide a signal detection circuit, which includes an input switch circuit, an amplitude detection circuit, a clock generation circuit and an integration circuit. The input switch circuit is configured to receive a reference voltage and an input voltage, and is controlled by a switching signal group to selectively output the reference voltage or the input voltage. The amplitude detection circuit is configured to detect the output of the input switch circuit to generate an amplitude voltage correspondingly. The clock generation circuit is configured to generate the set of switching signals. Wherein, the switch signal group is used to control the input switch circuit to alternately enter a first stage and a second stage, and the input switch circuit is controlled to output the reference voltage in the first stage, and output the reference voltage in the second stage the input voltage. The integration circuit is configured to take the amplitude voltage as an input and accumulate it, and generate an integration voltage corresponding to an accumulation result within a predetermined time interval. Wherein, the predetermined time interval includes a plurality of cycles with the first stage and the second stage as cycles.

A beneficial effect of the present invention is that the signal detection circuit provided by the present invention uses the input switch circuit to select the input signal and the reference voltage to enter the amplitude detection circuit and the integration circuit at different stages. The voltages will experience the same amount of circuit offset, thus reducing errors due to process biasing when different paths are taken.

In order to further understand the features and technical contents of the present invention, please refer to the following detailed description and illustrations of the present invention, however, the provided illustrations are only for reference and illustration, and are not intended to limit the present invention.

Description of drawings

FIG. 1 is a functional block diagram of a signal detection circuit according to an embodiment of the present invention.

FIG. 2 is a circuit layout diagram of a signal detection circuit according to an embodiment of the present invention.

FIG. 3 is a first signal timing diagram of the signal detection circuit of the embodiment of the present invention.

FIG. 4 is a second signal timing diagram of the signal detection circuit of the embodiment of the present invention.

FIG. 5 is a circuit layout diagram of a signal detection circuit according to another embodiment of the present invention.

Detailed ways

The implementation of the "signal detection circuit" disclosed in the present invention will be described below through specific specific examples. Those skilled in the art can understand the advantages and effects of the present invention from the content disclosed in this specification. The present invention can be implemented or applied through other different specific embodiments, and various modifications and changes can be made to the details in this specification based on different viewpoints and applications without departing from the concept of the present invention. In addition, it is stated in advance that the drawings of the present invention are only for simple illustration, and are not drawn according to the actual size. The following examples will further describe the relevant technical content of the present invention in detail, but the disclosed content is not intended to limit the protection scope of the present invention. In addition, the term "or" used herein may include any one or a combination of more of the associated listed items depending on the actual situation.

FIG. 1 is a functional block diagram of a signal detection circuit according to an embodiment of the present invention. Referring to FIG. 1 , an embodiment of the present invention provides a signal detection circuit 1 , which includes an input switch circuit 10 , an amplitude detection circuit 12 , a clock generation circuit 14 and an integration circuit 16 .

The input switch circuit 10 is configured to receive the reference voltage VREF and the input voltage VIN, and is controlled by the switching signal set SS to selectively output the reference voltage VREF or the input voltage VIN.

Please refer to FIG. 2 first. FIG. 2 is a circuit layout diagram of a signal detection circuit according to an embodiment of the present invention. For example, the reference voltage VREF is a pair of differential reference voltages, including a first reference voltage VREFP and a second reference voltage VREFN, and the input voltage VIN is a pair of differential input voltages, including a first input voltage VINP and a second input voltage VINN .

In the embodiment of FIG. 2, in response to the input voltage VIN being a differential signal, the input switch circuit 10 can be, for example, a multiplexer, and its simplified circuit can include a first switch S1, a second switch S2, The third switch S3 and the fourth switch S4 have a first output terminal o1 and a second output terminal o2. The first switch S1, the second switch S2, the third switch S3, and the fourth switch S4 can be N-type or P-type metal oxide semiconductor field effect transistors (Metal Oxide Semiconductor Field Effect Transistor, MOSFET), but the present invention does not limited to this.

Wherein, the first switch S1 is connected to the first output terminal o1 and receives the first reference voltage VREFP, the second switch S2 is connected to the first output terminal o1 and receives the first input voltage VINP, and the third switch S3 is connected to the second output terminal o2 and receives the second input voltage VINN, the fourth switch S4 is connected to the second input terminal o2 and receives the second reference voltage VREFN.

Please refer to FIG. 1 again, the amplitude detection circuit 12 is used to detect the output of the input switch circuit 10 to generate an amplitude voltage VA correspondingly. For example, the amplitude detection circuit 12 can be the rectifier 120 in FIG. 2 , or any circuit capable of converting the input signal into a simple output high potential or low potential according to its magnitude, but the present invention is not limited thereto.

As shown in FIG. 2, the rectifier 120 may have a first detection output terminal do1 and a second detection output terminal do2, and is configured to correspond to the output of the first output terminal o1 and the second output terminal o2 at the first detection output terminal do1 and the second output terminal do1. The second detection output terminal do2 generates an amplitude voltage VA including a first amplitude voltage Va1 and a second amplitude voltage Va2.

On the other hand, the clock generation circuit 14 is used to generate the switching signal set SS (as shown in FIG. 1 ). The switch signal set SS is mainly used to control the input switch circuit 10 to alternately enter the first phase and the second phase. In detail, in the first stage, the input switch circuit 10 is controlled to output the reference voltage VREF, and in the second stage to output the input voltage VIN.

In addition, when the above switching method is applied to the embodiment of FIG. 2, the switching signal set SS may include a first switching signal φ1 and a second switching signal φ2, and the first switching signal φ1 is used to control the first switch S1 and the fourth switch S4 is turned on in the first stage, and the second switching signal φ2 is used to control the second switch S2 and the third switch S3 to be turned on in the second stage, so that the input switch circuit 10 is connected to the first output terminal o1 and the second switch in the first stage. The two output terminals o2 respectively output the first reference voltage VREFP and the second reference voltage VREFN, and output the first input voltage VINP and the second input voltage VINN respectively at the first output terminal o1 and the second output terminal o2 in the second stage.

Please refer to FIG. 1 again, the integrating circuit 16 is used for integrating the amplitude voltage VA as an input, and generating an integrated voltage VINT corresponding to the accumulated result within a predetermined time interval. Wherein, the predetermined time interval covers a plurality of cycles with the first stage and the second stage as cycles.

For example, the integrating circuit 16 can separately perform the amplitude voltage VA under the first stage (this stage is generated according to the reference voltage VREF) and the amplitude voltage VA under the second stage (this stage is generated according to the input voltage VIN) in a single cycle. Generated) after sampling, subtraction processing is performed. Therefore, after a plurality of periods corresponding to the predetermined time interval, it can be determined whether the input voltage VIN is higher or lower than the reference voltage VREF according to the accumulated integrated voltage VINT.

In this way, please refer to FIG. 2 , the integrating circuit 16 may include a sampling circuit 160 and an integrating amplifier 162 . Wherein, the sampling circuit 160 is used for sampling the first amplitude voltage Va1 and the second amplitude voltage Va2 in the first stage.

As shown in FIG. 2 , the sampling circuit 160 may include a first sampling capacitor C1 , a second sampling capacitor C2 , a fifth switch S5 , a sixth switch S6 , a seventh switch S7 and an eighth switch S8 . The fifth switch S5, the sixth switch S6, the seventh switch S7, and the eighth switch S8 may be N-type or P-type metal oxide semiconductor field effect transistors (Metal Oxide Semiconductor Field Effect Transistor, MOSFET), but the present invention does not limited to this.

The first sampling capacitor C1 is connected between the first detection output terminal do1 and the first node N1, and the second sampling capacitor C2 is connected between the second detection output terminal do2 and the second node N2. One end of the fifth switch S5 is connected to the first node N1, and the other end receives the common-mode voltage Vcm. One end of the sixth switch S6 is connected to the second node N2, and the other end receives the common-mode voltage Vcm. The seventh switch S7 is connected between the first node N1 and the third node N3, and the eighth switch S8 is connected between the second node N2 and the fourth node N4.

On the other hand, the integrating amplifier 162 is used to hold the first amplitude voltage Va1 and the second amplitude voltage Va2 sampled by the sampling circuit 160 in the second stage for accumulation respectively.

Therefore, as shown in FIG. 2 , the integrating amplifier 162 may include a fully differential amplifier FDA, a first feedback capacitor Cfb1 and a second feedback capacitor Cfb2 .

A fully differential amplifier FDA has a non-inverting input (left + terminal), an inverting input (left - terminal), an inverting output (right + terminal), and a non-inverting output (right side-terminal), wherein the non-inverting input terminal is connected to the third node N3, and the inverting input terminal is connected to the fourth node N4. The first feedback capacitor Cfb1 is connected between the non-inverting input terminal and the inverting output terminal, and the second feedback capacitor Cfb2 is connected between the inverting input terminal and the non-inverting output terminal.

As shown in Figure 2, the fifth switch S5 and the sixth switch S6 are controlled by the first switching signal φ1 to be turned on in the first stage and turned off in the second stage, and the seventh switch S7 and the eighth switch S8 are controlled by the second The switching signal φ2 is controlled to be turned on in the second stage and turned off in the first stage. In the embodiment of the present invention, the integrating circuit 16 can be replaced by a low-pass filter or a capacitor, but the present invention is not limited thereto.

The detection mechanism of the signal detection circuit in FIG. 2 will be described below with reference to FIG. 3 . FIG. 3 is a first signal timing diagram of the signal detection circuit of the embodiment of the present invention. As shown in the figure, a timing chart including time point t1 to time point t9 is shown. Wherein, in the embodiment of FIG. 3 , the reference voltage VREF is lower than the input voltage VIN during the interval from time point t1 to t5 , and greater than the input voltage VIN during the interval from time point t5 to time point t9 .

In the following, time point t2 is taken as the starting point, between time point t2 and t3, the first stage is entered, the first switching signal φ1 is high potential, and the second switching signal φ2 is low potential, representing the first switch S1, the fourth switch S4, the fifth switch S5, and the sixth switch S6 are all turned on, and the second switch S2, the third switch S3, the seventh switch S7, and the eighth switch S8 are all turned off. At this time, the reference voltage VREF is input into the rectifier 120 to generate a low The amplitude voltage VA of the potential. For this amplitude voltage VA, the first sampling capacitor C1 samples the difference between the first amplitude voltage Va1 and the common-mode voltage Vcm, and the second sampling capacitor C2 samples the difference between the second amplitude voltage Va2 and the common-mode voltage Vcm Sampling, according to which the amplitude voltage VA can be sampled.

Then, between the time point t3 and t4, enter the second stage, the first switching signal φ1 is low potential, the second switching signal φ2 is high potential, representing the first switch S1, the fourth switch S4, the fifth switch S5 and The sixth switch S6 is turned off, and the second switch S2 , the third switch S3 , the seventh switch S7 and the eighth switch S8 are all turned on. At this time, the input voltage VIN is input to the rectifier 120 to generate a high potential amplitude voltage VA. This high-potential amplitude voltage VA will be subtracted from the low-potential amplitude voltage VA sampled in the first stage, and then the result of the subtraction will be amplified by the fully differential amplifier FDA and held in the first feedback capacitor Cfb1 and the second feedback capacitor Cfb2 , to generate the integral voltage VINT.

It can be seen from Fig. 3 that since the reference voltage VREF is lower than the input voltage VIN during the period from time point t2 to t5, the integrated voltage VINT gradually decreases from time point t2 to t5. After several cycles, such as time point t5, the integrated voltage VINT can be output as the cumulative result, and the magnitude relationship between the reference voltage VREF and the input voltage VIN can be determined accordingly.

On the other hand, since the reference voltage VREF is greater than the input voltage VIN during the time point t6 to t9, the integrated voltage VINT gradually increases from the time point t6 to t9, and the increased integrated voltage VINT can also be output after several cycles. as a cumulative result.

In addition, it should be noted that the integrating amplifier 162 in FIG. 2 further includes a first reset switch Sr1 , a second reset switch Sr2 and a third reset switch Sr3 . The first reset switch Sr1 is connected between the non-inverting input terminal and the inverting output terminal of the fully differential amplifier FDA, and the second reset switch Sr2 is connected between the inverting input terminal and the non-inverting output terminal of the fully differential amplifier FDA. Between, the third reset switch Sr3 is connected between the third node N3 and the fourth node N4.

Correspondingly, the clock generation circuit 14 also generates a reset signal Rst to control the first reset switch Sr1, the second reset switch Sr2 and the third reset switch in a reset time interval before and after the predetermined time interval Sr3 is turned on and turned off within a predetermined time interval. For example, the reset time interval may be between time points t1 and t2 and between t5 and t6 in FIG. 3 , and the predetermined time interval may be, for example, between time points t2 and t5. After the first reset switch Sr1 , the second reset switch Sr2 and the third reset switch Sr3 are turned on, the retained integrated voltage VINT can be reset for re-detection.

Referring to FIG. 4 , the detection mechanism of the signal detection circuit in FIG. 2 will be described in another embodiment. FIG. 4 is a second signal timing diagram of the signal detection circuit of the embodiment of the present invention. As shown in the figure, a timing chart including time point t1 to time point t9 is shown. Wherein, in the embodiment of FIG. 4 , the reference voltage VREF remains unchanged, and the input voltage is lower than the reference voltage VREF during the interval from time point t1 to t5 , and greater than the reference voltage VREF during the interval from time point t5 to t9 .

In the following, time point t2 is taken as the starting point, between time point t2 and t3, the first stage is entered, the first switching signal φ1 is high potential, and the second switching signal φ2 is low potential, representing the first switch S1, the fourth switch S4, the fifth switch S5 and the sixth switch S6 are all turned on, and the second switch S2, the third switch S3, the seventh switch S7 and the eighth switch S8 are all turned off. At this time, the reference voltage VREF is input into the rectifier 120 to generate high The amplitude voltage VA of the potential. For this amplitude voltage VA, the first sampling capacitor C1 samples the difference between the first amplitude voltage Va1 and the common-mode voltage Vcm, and the second sampling capacitor C2 samples the difference between the second amplitude voltage Va2 and the common-mode voltage Vcm Sampling, according to which the amplitude voltage VA can be sampled.

Then, between the time point t3 and t4, enter the second stage, the first switching signal φ1 is low potential, the second switching signal φ2 is high potential, representing the first switch S1, the fourth switch S4, the fifth switch S5 and The sixth switch S6 is turned off, and the second switch S2 , the third switch S3 , the seventh switch S7 and the eighth switch S8 are all turned on. At this time, the input voltage VIN is input to the rectifier 120 to generate a low voltage amplitude voltage VA. This low-potential amplitude voltage VA will be subtracted from the high-potential amplitude voltage VA sampled in the first stage, and then the result of the subtraction will be amplified by the fully differential amplifier FDA and held in the first feedback capacitor Cfb1 and the second feedback capacitor Cfb2 , to generate the integral voltage VINT.

It can be seen from Figure 4 that since the reference voltage VREF is greater than the input voltage VIN during the period from time point t2 to t5, the integrated voltage VINT gradually increases from time point t2 to t5. After several cycles, such as time point t5, the integrated voltage VINT can be output as the accumulation result, and the magnitude relationship between the reference voltage VREF and the input voltage VIN can be determined accordingly.

Therefore, the above-mentioned embodiment uses the input switch circuit 10 to select the input voltage VIN and the reference voltage VREF to enter the amplitude detection circuit 12 and the integration circuit 16 at different stages. Since the back-end circuit is shared, the input voltage VIN and the reference voltage VREF will go through the same circuit. Offset, therefore, can reduce errors due to process bias when using different paths.

In some embodiments, the signal detection circuit 1 further optionally includes a comparator circuit 18 configured to receive the integrated voltage VINT generated by the integrating circuit 16 through its first input terminal and its second input terminal (that is, the inverse in FIG. 2 The voltages at the inverting output terminal and the non-inverting output terminal) are compared to generate a comparison result signal Vcomp as an accumulation result. Correspondingly, in this embodiment, the clock generation circuit 14 is also used to generate the comparison clock signal comclk, so as to control the comparator circuit 18 to generate and output The comparison result signal Vcomp.

Please refer to FIG. 5 first. FIG. 5 is a circuit layout diagram of a signal detection circuit according to another embodiment of the present invention. In another embodiment, the integrating amplifier 162 also optionally includes a chopping circuit, such as a first chopping circuit CC1 and a second chopping circuit CC2 respectively connected to the input end and the output end of the fully differential amplifier FDA. , which can be programmed to act at a specific point in time. The first chopper circuit CC1 has two input terminals respectively connected to the third node N3 and the fourth node N4, and two input terminals respectively connected to the non-inverting input terminal (left + terminal) and the inverting input terminal (left - terminal). output. The second chopper circuit CC2 has two input terminals connected to the inverting output terminal (right side - terminal) and non-inverting output terminal (right side + terminal) respectively, and the first input terminal and the second input terminal respectively connected to the comparator circuit 18. Input to two outputs.

For example, the first chopping circuit CC1 and the second chopping circuit CC2 can operate together within a predetermined number of cycles, so that the comparator circuit 18 can cancel the offset on the signal transmission path, so that the comparison result signal Vcomp optimize.

For example, the aforementioned offset may be the offset generated by the fully differential amplifier FDA, and the specific number of cycles may be 4 cycles. In the first interval of 4 cycles, for example, in the first two cycles, the first chopping circuit CC1 and the second chopping circuit CC2 can be configured to make the comparison according to the first switching signal φ1 and the second switching signal φ2 The converter circuit 18 compares the signal at the inverted output (right-side) with the signal at the non-inverted output (right-side), and in the second interval of the 4 cycles, for example, in the last two cycles, The first chopping circuit CC1 and the second chopping circuit CC2 are configured to make the comparator circuit 18 convert the signal of the comparison non-inverting output terminal (right side + terminal) according to the first switching signal φ1 and the second switching signal φ2 The signal at the inverting output terminal (right-terminal) can achieve the effect of canceling the offset of the two output terminals on average, so as to optimize the comparison result signal Vcomp.

The beneficial effect of embodiment:

A beneficial effect of the present invention is that the signal detection circuit provided by the present invention uses the input switch circuit to select the input signal and the reference voltage to enter the amplitude detection circuit and the integration circuit at different stages. The voltages will experience the same amount of circuit offset, thus reducing errors due to process biasing when different paths are taken.

On the other hand, the signal detection circuit provided by the present invention can optionally include a comparator circuit and a chopping circuit to achieve the effect of offsetting the offsets of the two output terminals on average, and generate an optimized comparison result signal Vcomp as an accumulated result.

The content disclosed above is only a preferred embodiment of the present invention, and the scope of patent protection required by the present invention is not limited thereto. Therefore, all equivalent technical changes made by using the description and illustrations of the present invention are included in this document. within the scope of patent protection required by the invention.

Explanation of reference signs:

1: Signal detection circuit

10: Input switch circuit

12: Amplitude detection circuit

120: rectifier

14: Clock generation circuit

16: Integrator circuit

18: Comparator circuit

160: Sampling circuit

162: Integral amplifier

C1: first sampling capacitor

C2: Second sampling capacitor

CC1: First chopper circuit

CC2: Second chopper circuit

Cfb1: first feedback capacitor

Cfb2: Second feedback capacitor

comclk: compare clock signal

do1: first detection output terminal

do2: the second detection output

FDA: Fully Differential Amplifier

N1: the first node

N2: second node

N3: the third node

N4: the fourth node

o1: first output terminal

o2: second output terminal

Rst: reset signal

S1: first switch

S2: second switch

S3: the third switch

S4: Fourth switch

S5: fifth switch

S6: Sixth switch

S7: Seventh switch

S8: Eighth switch

Sr1: First reset switch

Sr2: Second reset switch

Sr3: Third reset switch

SS: switch signal group

t1 to t9: time

VA: amplitude voltage

Va1: first amplitude voltage

Va2: second amplitude voltage

Vcm: common mode voltage

Vcomp: comparison result signal

VIN: input voltage

VINN: second input voltage

VINP: first input voltage

VINT: integral voltage

VREF: reference voltage

VREFN: second reference voltage

VREFP: first reference voltage

φ1: the first switching signal

φ2: Second switching signal

Claims (10)

1. A signal detection circuit, comprising: an input switch circuit configured to receive a reference voltage and an input voltage, and controlled by a set of switching signals to selectively output the reference voltage or the input voltage; An amplitude detection circuit configured to detect the output of the input switch circuit to generate an amplitude voltage correspondingly; a clock generating circuit configured to generate the set of switching signals, wherein the set of switching signals is used to control the input switching circuit to alternately enter a first phase and a second phase, and the input switching circuit is controlled to outputting the reference voltage during the first phase, and outputting the input voltage during the second phase; an integration circuit configured to take the amplitude voltage as an input and accumulate it, and generate an integration voltage corresponding to an accumulation result within a predetermined time interval; Wherein, the predetermined time interval includes at least one cycle with the first phase and the second phase as a cycle. 2. The signal detection circuit according to claim 1, wherein the reference voltage is a pair of differential reference voltages, including a first reference voltage and a second reference voltage, and the input voltage is a pair of differential The input voltage includes a first input voltage and a second input voltage. 3. The signal detection circuit according to claim 2, wherein the input switch circuit has a first output terminal and a second output terminal, and comprises: a first switch connected to the first output terminal and receiving the first reference voltage; a second switch connected to the first output terminal and receiving the first input voltage; a third switch connected to the second output terminal and receiving the second input voltage; A fourth switch is connected to the second input terminal and receives the second reference voltage. 4. The signal detection circuit according to claim 3, wherein the switching signal group includes a first switching signal and a second switching signal, and the first switching signal is used to control the first switch and the fourth switch is turned on in the first stage, and the second switching signal is used to control the second switch and the fourth switch to be turned on in the second stage, so that the input switch The circuit outputs the first reference voltage and the second reference voltage at the first output terminal and the second output terminal respectively in the first stage, and outputs the first reference voltage at the first output terminal in the second stage terminal and the second output terminal respectively output the first input voltage and the second input voltage. 5. The signal detection circuit according to claim 4, wherein the amplitude detection circuit has a first detection output terminal and a second detection output terminal, and is configured to correspond to the first output terminal and the The output of the second output end generates the amplitude voltage including a first amplitude voltage and a second amplitude voltage at the first detection output end and the second detection output end respectively, Wherein, the integration circuit includes: a sampling circuit configured to sample the first amplitude voltage and the second amplitude voltage during the first phase; and An integrating amplifier configured to hold the first amplitude voltage and the second amplitude voltage sampled by the sampling circuit in the second stage for accumulation respectively. 6. The signal detection circuit according to claim 5, wherein the sampling circuit comprises: a first sampling capacitor connected between the first detection output terminal and a first node; a second sampling capacitor connected between the second detection output terminal and a second node; a fifth switch, one end of which is connected to the first node, and the other end receives a common-mode voltage; a sixth switch, one end of which is connected to the second node, and the other end of which receives the common-mode voltage; a seventh switch connected between the first node and a third node; and an eighth switch connected between the second node and a fourth node; Wherein, the integrating amplifier includes: A fully differential amplifier having a non-inverting input terminal, an inverting input terminal, an inverting output terminal and a non-inverting output terminal, wherein the non-inverting input terminal is connected to the third node, and the The inverting input terminal is connected to the fourth node; a first feedback capacitor connected between the non-inverting input terminal and the inverting output terminal; and A second feedback capacitor connected between the inverting input terminal and the non-inverting output terminal. 7. The signal detection circuit according to claim 6, wherein the fifth switch and the sixth switch are configured to be controlled by the first switching signal to be turned on in the first phase, turned off in the second phase, the seventh switch and the eighth switch are configured to be controlled by the second switching signal to be turned on in the second phase and to be turned off in the first phase . 8. The signal detection circuit according to claim 7, wherein the integrating amplifier further comprises: a first reset switch connected between the non-inverting input terminal and the inverting output terminal; a second reset switch connected between the inverting input and the non-inverting output; and a third reset switch connected between the third node and the fourth node, Wherein, the clock generation circuit is also configured to generate a reset signal to control the first reset switch and the second reset switch in a reset time interval before and after the predetermined time interval And the third reset switch is turned on and turned off within the predetermined time interval. 9. The signal detection circuit according to claim 8, further comprising a comparator circuit configured to receive the feedback signal through a first input terminal and a second input terminal of the comparator circuit, respectively. The voltages of the inversion output terminal and the non-inverting output terminal are compared to generate a comparison result signal as the accumulation result, wherein the clock generation circuit is further configured to generate a comparison clock signal to generate a comparison clock signal at the predetermined time When the interval ends, the comparator circuit is controlled to generate and output the comparison result signal. 10. The signal detection circuit according to claim 9, further comprising: A first chopper circuit having two input terminals respectively connected to the third node and the fourth node and two output terminals respectively connected to the non-inverting input terminal and the inverting input terminal; A second chopper circuit, having two input terminals respectively connected to the inverting output terminal and the non-inverting output terminal and two input terminals respectively connected to the first input terminal and the second input terminal of the comparator circuit output terminal, Wherein, the first chopping circuit and the second chopping circuit are configured to make the comparator circuit compare the voltage of the inverted output terminal during a first interval of a predetermined number of the at least one cycle and the voltage at the non-inverting output terminal, and a second interval during the predetermined number of at least one period causes the comparator circuit to switch to compare the voltage at the non-inverting output terminal with the inverting voltage at the output.

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