CN115291176A - Digital frequency storage device with low stray large delay and application method thereof - Google Patents
Digital frequency storage device with low stray large delay and application method thereof Download PDFInfo
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S7/00—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
- G01S7/02—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S13/00
- G01S7/40—Means for monitoring or calibrating
- G01S7/4052—Means for monitoring or calibrating by simulation of echoes
- G01S7/406—Means for monitoring or calibrating by simulation of echoes using internally generated reference signals, e.g. via delay line, via RF or IF signal injection or via integrated reference reflector or transponder
- G01S7/4065—Means for monitoring or calibrating by simulation of echoes using internally generated reference signals, e.g. via delay line, via RF or IF signal injection or via integrated reference reflector or transponder involving a delay line
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S7/00—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
- G01S7/02—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S13/00
- G01S7/40—Means for monitoring or calibrating
- G01S7/4052—Means for monitoring or calibrating by simulation of echoes
- G01S7/4056—Means for monitoring or calibrating by simulation of echoes specially adapted to FMCW
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Abstract
The invention provides a digital frequency storage device with low stray large delay and an application method thereof, belonging to the technical field of electronic warfare. Wherein the apparatus comprises: the device comprises a QDR module, an ADC module, an FPGA module and a DAC module. The implementation method adopted by the invention reduces the memory capacity requirement of the QDR module, improves the layout and wiring capacity of the FPGA module, increases the target simulation distance by seven times on the basis of reducing the stray caused by the AD device, and simultaneously reduces the normal temperature stray of the AD device to be more than-55 dBc. In addition, the adopted FPGA provides hardware guarantee for software upgrading; the adopted ADC module can simultaneously realize two paths of intermediate frequency signal 2.5GSPS sampling, and the two paths of low-stray large-delay target simulation can be simultaneously realized by matching with the DAC module, so that the flexibility of the system is improved.
Description
Technical Field
The invention relates to the technical field of signal processing and analysis, in particular to a digital frequency storage device with low spurious large delay and an application method thereof.
Background
The ADC device includes an AD device that quantizes the analog intermediate frequency signal into a digital signal, and a DA device that reduces the digital signal into an analog intermediate frequency signal. To simulate realistic target types, it is often necessary to employ higher significance AD and DA devices; to accommodate the rich signal types, larger sampling rate AD and DA devices have to be used, however, higher significance and larger sampling rate are themselves a couple of industrial difficulties. Meanwhile, the AD device is more difficult to do than the DA device because the DA device can be replaced with a DDS device or the like, and the sampling rate and the number of significant bits are relatively easy to do better. Thus, at the same 2.5GSPS sampling rate, spurs of the DRFM signal are limited to the AD devices. In the prior art, in the input intermediate frequency range of 2.5GSPS sampling rate and 1.35-2.4 GHz of an AD device, stray can already reach-50 dBc, but the cost is high, an interface is generally 204B or 204C, and transmission response is large. Under the same condition, the output intermediate frequency stray of the DA device can easily reach-55 dBc.
As a first core component of the DRFM apparatus, a memory device is used to store digital signals. By the set memory delay, the set position of the target can be formed after the radar-side processing. Based on the 2.5GSPS sampling rate and the 10bit quantization bits, the memory throughput rate can be calculated to be 3.125GBytes/s. To ensure the fastest deterministic read and write latency, RAM-type memories, such as QDR devices, are used. However, such devices tend to have a small capacity, substantially 72Mbits. From the above conditions, a maximum delay of 2.88 milliseconds can be calculated. From the radar equation, it can be calculated that the maximum simulated distance of the target is 432 km, which constitutes a great limit to the movement of the target, as shown in fig. 1.
As a second core component of the DRFM apparatus, the FPGA device is used to generate the radar target analog modulation. Since the radar may emit signals of varying frequencies, but the doppler frequencies of signals of different frequencies in the same target echo are different, it is necessary to measure the frequencies of the sub-pulses (or know the frequency of the emitted waveform in advance), and to track the sub-pulses, and to modulate different doppler frequencies for each sub-pulse according to the measured signal frequency, as shown in fig. 2.FGPA also needs to complete device control, storage delay control, etc., which presents a serious challenge to FPGA resources.
Disclosure of Invention
The purpose of the invention is as follows: a digital frequency storage device with low stray and large delay and an application method thereof are provided, and the function of the device is realized through a hardware programming language (HDL) so as to solve the problems in the prior art. The radar test equipment with lower stray and larger delay is developed under the condition of not increasing the hardware cost of an AD device and a memory and meeting the requirements of the domesticated process index, and the target analog signal with low stray and large delay is generated.
The technical scheme is as follows: in a first aspect, a digital frequency storage device with low spurious large delay is provided, which specifically includes the following modules: ADC module, FPGA module, QDR module, DAC module.
The ADC module is used for simulating intermediate frequency sampling and generating a digital intermediate frequency signal; the FPGA module is connected with the ADC module and used for receiving the digital intermediate-frequency sampling signal output by the ADC module, and carrying out target simulation on the digital intermediate-frequency sampling signal according to preset target time delay and echo Doppler to generate a digital intermediate-frequency target simulation signal; the QDR module is connected with the FPGA module and used for receiving digital intermediate-frequency target analog signals output by the FPGA and storing and reading the output signals of the FPGA module; meanwhile, according to the read-write control input by the FPGA module, the digital zero intermediate frequency sampling signal is output in a delayed mode to generate a zero intermediate frequency delay signal; and the DAC module is connected with the FPGA module and used for quantizing the signal output by the FPGA module and generating an analog intermediate frequency signal.
In some implementations of the first aspect, the ADC module samples an input analog intermediate frequency to generate a digital intermediate frequency signal and outputs the digital intermediate frequency signal to the FPGA module; the DAC module quantizes the digital signal of the FPGA module and outputs an analog intermediate frequency signal; the QDR module realizes the storage, reading and writing of digital signals of the FPGA module; the FPGA module performs target simulation on the analog intermediate-frequency signal to generate a low-spurious large-delay DRFM signal, and is connected with the ADC module, the DAC module and the QDR module.
In some implementations of the first aspect, the programming of the FPGA module employs a pipeline-structured low-coupling high-coherence module, which includes an ADC sampling unit, a DAC sampling unit, an intermediate frequency fast frequency measurement unit, a QDR storage delay unit, a first frequency shift modulation unit, an instantaneous octave decimation unit, and an instantaneous octave interpolation unit.
In the FPGA module, an ADC sampling unit is connected with an intermediate frequency rapid frequency measurement unit and an instantaneous octave extraction unit, a QDR storage delay unit is connected with the instantaneous octave extraction unit and a frequency shift modulation unit, the frequency shift modulation unit is connected with an instantaneous octave interpolation unit, the instantaneous octave interpolation unit is simultaneously connected with a DAC sampling unit, and the intermediate frequency rapid frequency measurement unit is connected with the instantaneous octave extraction unit and the instantaneous octave interpolation unit.
The ADC sampling unit is used for configuring a register of the DAC module and converting the intermediate-frequency digital target analog signal into a required data format of the DAC module, the ADC sampling unit is used for carrying out 2.5GSPS sampling on intermediate-frequency input, the intermediate-frequency fast frequency measurement unit is used for carrying out fast intermediate-frequency measurement on the digital sampling, the instantaneous octave extraction unit is used for carrying out zero intermediate-frequency conversion on the intermediate-frequency digital sampling and extracting octaves to generate a zero intermediate-frequency digital signal, the QDR storage delay unit is used for carrying out storage delay on the digital zero intermediate-frequency digital signal, the first frequency shift modulation unit is used for carrying out Doppler frequency shift on the logarithmic zero intermediate-frequency delay digital signal, the instantaneous octave interpolation unit is used for interpolating the octave extraction target analog signal and generating a digital intermediate-frequency target analog signal through intermediate-frequency conversion, and the DAC sampling unit is used for configuring the register of the DAC module and converting the intermediate-frequency digital target analog signal into the required data format of the DAC module.
In some implementations of the first aspect, the ADC sampling unit performs sampling on the intermediate frequency input 2.5GSPS to obtain a digital intermediate frequency sampling signal y (n) = a (n) cos (2 pi f) c nT s +φ(n))，n∈[0,1,2,…,N-1]Wherein, T s Representing the sampling time, f c Representing an input signal carrier frequency; phi (n) represents the initial phase of the intermediate frequency input signal; a represents the intermediate frequency input signal amplitude; n represents the number of samples.
The intermediate frequency rapid frequency measurement unit obtains the instantaneous frequency estimation of the intermediate frequency signal by looking up a table based on the phase difference of the digital intermediate frequency sampling signal
Intermediate frequency signal instantaneous frequency estimation of instantaneous eight-time decimation unit based on digital intermediate frequency sampling signal
Generating eight-time decimated 16-path digital zero-IF sampling signal y D2 (n) the bit width is 10 bits, and the operation clock frequency is 19.53125MHz.
The QDR storage delay unit is used for indicating the digital zero intermediate frequency sampling signal y based on the 3.3V width-preserving pulse signal D2 (n) storing and outputting the zero intermediate frequency delay digital signal y D2 (n- τ), where τ is the target number of delayed beats and is expressed as:
in the formula, R 0 Representing the relative distance between the radar and the simulated target; v represents the velocity between the radar and the simulated target; a represents the acceleration between the radar and the simulated target; c represents the speed of light in air; t is a unit of clk Representing the running period of the FPGA digital signal clock; t represents the target motion time.
Frequency shift modulation unit delays digital signal y based on zero intermediate frequency D2 (n-tau) frequency shift becomes eight times extraction target analog signal
Wherein, f d For target motion doppler, the corresponding expression is:
wherein V represents the velocity between the radar and the simulated target; a represents the acceleration between the radar and the simulated target; c represents the speed of light in air;
in the representationAnd estimating the instantaneous frequency of the frequency signal.
Instantaneous frequency estimation of intermediate frequency signal based on digital intermediate frequency signal by instantaneous eight-time interpolation unit
Generating eight-fold interpolated 16-path digital intermediate frequency target analog signal
The bit width is 10 bits, and the running clock frequency is 156.25MHz.
DAC sampling unit pairs 16 paths of digital intermediate frequency target analog signals
The bit width is 10 bits, the operation clock frequency is 156.25MHz, and the intermediate frequency output is carried out.
The instantaneous eight-time extraction unit comprises: the orthogonal digital down-conversion unit, the second frequency shift modulation unit and the filtering extraction unit are used for generating zero intermediate frequency digital signals and filtering out stray waves in a preset floating range;
the instantaneous octave interpolation unit includes: the filter interpolation unit, the third frequency shift modulation unit and the orthogonal digital up-conversion unit; the method is used for extracting the target analog signal by eight times to perform zero intermediate frequency conversion, and interpolating the zero intermediate frequency digital signal by eight times to generate a digital intermediate frequency target analog signal.
In a second aspect, an application method of a digital frequency storage device with low spurious large delay is provided, which specifically includes the following steps:
step 1, after the equipment is powered on, initializing relevant configuration parameters and enabling relevant modules to be in a normal working state;
specifically, the ADC sampling unit completes configuration of two paths of 2.5GSPS in the ADC module, so that the ADC module normally samples the intermediate frequency input 2.5GSPS to obtain y (n); the DAC sampling unit completes 2.5GSPS configuration on the DAC module, and the QDR storage delay unit completes initialization on the QDR module;
step 2, the ADC module collects digital intermediate frequency sampling signals and transmits the digital intermediate frequency sampling signals to the FPGA module;
step 3, utilizingIntermediate frequency instantaneous frequency estimation obtained by intermediate frequency rapid frequency measurement unit in FPGA module
Step 4, estimating instantaneous frequency of instantaneous eight-time extraction unit in FPGA module based on intermediate frequency signal
Generating a zero intermediate frequency digital signal y decimated by eight times D1 (n) and generating 16 paths of digital zero intermediate frequency sampling signals y through FIFO bit width conversion technology D2 (n)；
Step 5, a QDR storage delay unit in the FPGA module indicates the digital zero intermediate frequency sampling signal y based on the 3.3V width-keeping pulse signal D2 (n) storing and outputting the zero intermediate frequency delayed digital signal y D2 (n-τ)；
Step 6, the frequency shift modulation unit in the FPGA module delays the digital signal y based on zero intermediate frequency D2 (n-tau) frequency shift to generate eight times of extracted target analog signal
Step 7, instantaneous eight-interpolation unit in FPGA module based on intermediate frequency signal instantaneous frequency estimation
Eight-time extraction target analog signal of sum frequency shift modulation unit
Generating octave interpolated digital intermediate frequency target analog signal
Step 8, simulating the low-spurious large-delay DRFM target analog 2.5GSPS digital intermediate frequency target analog signal by a DAC sampling unit in the FPGA module
And carrying out intermediate frequency output.
Has the advantages that: the invention provides a digital frequency storage device with low stray and large delay and an application method thereof, which adopt an instantaneous eight-time extraction and instantaneous eight-time interpolation method to reduce the capacity requirement of a QDR module memory, improve the layout and wiring capacity of an FPGA module, increase the target simulation distance by seven times on the basis of reducing the stray caused by an AD device, and reduce the normal-temperature stray of the AD device; the adopted FPGA provides device guarantee for software upgrading; the adopted ADC module can simultaneously realize two paths of intermediate frequency signals 2.5GSPS sampling, and can simultaneously realize two paths of low-stray large-delay target simulation by matching with the DAC module, so that the flexibility of the system is improved; the adopted DRFM device and method with low stray and large delay can be used for testing the detection and tracking functions of the radar on a long-distance target, can be separated from the actual working environment during testing, and is easy to test whether a product can normally work; the adopted low-stray large-delay DRFM device has small volume, simple hardware circuit and convenient popularization and use; the adopted complex Doppler modulation technology can realize the target simulation of two paths of intermediate frequency signals 2.5GSPS sampling signals under the condition of less FPGA resources.
Drawings
Fig. 1 is a schematic diagram of a radar target distance simulation in the prior art.
Fig. 2 is a diagram of a doppler simulation of a frequency agile signal in the prior art.
FIG. 3 is a diagram showing the connection relationship between modules in the FPGA module according to the present invention.
FIG. 4 is a diagram of the connection relationship of the units in the instant eight-fold decimation unit of the present invention.
FIG. 5 is a diagram of the connection of units within the instantaneous octave interpolation unit of the present invention.
Fig. 6 is an overall workflow diagram of the present invention.
Detailed Description
In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the invention.
Aiming at the performance requirements of a DRFM device in the prior art, the invention provides a digital frequency storage device with low stray and large delay and an application method thereof.
Example one
In one embodiment, a digital frequency storage device with low spurious large delay is provided, as shown in fig. 3, the device specifically includes the following modules: ADC module, FPGA module, QDR module, DAC module.
Specifically, the ADC module samples the input analog intermediate frequency to generate a digital intermediate frequency signal, and outputs the digital intermediate frequency signal to the FPGA module; the DAC module quantizes the digital signal of the FPGA module and outputs an analog intermediate frequency signal; the QDR module realizes the storage and reading of the digital signals of the FPGA module; the FPGA module performs target simulation on the analog intermediate-frequency signal to generate a low-spurious large-delay DRFM signal, and is connected with the ADC module, the DAC module and the QDR module.
In a further embodiment, the QDR module stores the intermediate frequency signal input by the FPGA module, and delays and outputs the intermediate frequency signal according to read-write control input by the FPGA module, and connects with the FPGA module. And the ADC module is used for performing 2.5GSPS sampling on the analog input intermediate frequency signal, outputting the sampled signal to the FPGA module and connecting the FPGA module with the ADC module. And the FPGA module is used for simulating a low-stray large-delay DRFM target of the digital intermediate frequency signal according to the intermediate frequency sampling signal and the set target time delay and echo Doppler and is connected with the ADC module, the DAC module and the QDR module. And the DAC module is used for converting the 2.5GSPS digital intermediate frequency signal into an analog intermediate frequency output signal and is connected with the FPGA module.
Example two
In a further embodiment based on the first embodiment, according to the requirement that the nyquist sampling rate is more than twice of the input bandwidth, an ADC device ev10aq190 with a sampling rate of 2.5GSPS and a quantization bit number of 10 is selected, and the device has four paths of 1.25GSPS sampling modules, and can be flexibly spliced into two paths of 2.5GSPS intermediate frequency samples.
The QDR module selects CY7C1565KV18-500BZC, the storage capacity is 72MBits, the stability is strong, the throughput rate reaches 144 × 500/2Bits/s =4.5GBytes/s, and the requirement is larger than the requirement of the memory throughput rate by 3.125GBytes/s.
The FPGA module selects SMQ7K410T-FFG900 with rich programmable resources, and lays a foundation for software free upgrade and two-way DRFM target simulation.
According to the requirement that the Nyquist sampling rate is more than twice the input bandwidth, the DAC module selects a DAC device DA9739 with the sampling rate of 2.5GSPS and the quantization bit number of 14. In the output intermediate frequency range of 1.35-2.4 GHz, the theoretical stray energy of the device can reach-55 dBc.
EXAMPLE III
In a further embodiment based on the first embodiment, the programming of the FPGA module adopts a low-coupling high-cohesion module unit with a pipeline structure, and the module unit comprises an ADC sampling unit, a DAC sampling unit, an intermediate frequency fast frequency measurement unit, a QDR storage delay unit, a first frequency shift modulation unit, an instantaneous octave extraction unit and an instantaneous octave interpolation unit, wherein in the FPGA module, the ADC sampling unit is connected with the intermediate frequency fast frequency measurement unit and the instantaneous octave extraction unit, the QDR storage delay unit is connected with the instantaneous octave extraction unit and the frequency shift modulation unit, the frequency shift modulation unit is connected with the instantaneous octave interpolation unit, the instantaneous octave interpolation unit is simultaneously connected with the DAC sampling unit, and the intermediate frequency fast frequency measurement unit is connected with the instantaneous octave extraction unit and the instantaneous octave interpolation unit.
The ADC sampling unit configures a register of the DAC module and performs 2.5GSPS sampling on an intermediate frequency input, the intermediate frequency fast frequency measurement unit performs fast intermediate frequency measurement on digital sampling, the instantaneous octave extraction unit performs zero intermediate frequency conversion on the intermediate frequency digital sampling and extracts octaves to generate a zero intermediate frequency digital signal, the QDR storage delay unit performs storage delay on the digital signal, the first frequency shift modulation unit performs doppler frequency shift on the digital signal, the instantaneous octave interpolation unit interpolates the digital signal by octaves and generates an intermediate frequency digital target analog signal, and the DAC sampling unit configures a register of the DAC module and converts the intermediate frequency digital target analog signal into a data format required by the DAC module, as shown in fig. 4.
Example four
In a further embodiment based on the first embodiment, the ADC sampling unit outputs the sampled intermediate frequency signal in parallel by 16 paths y (n) based on a 2.5GSPS register configuration, the data sampling bit is 10 bits wide, and the operation clock frequency is 156.25MHz.
The intermediate frequency rapid frequency measurement unit carries out parallel 16 Fourier transform on the intermediate frequency signal based on 16 paths of digital intermediate frequency sampling signals Y (n), outputs a signal branch complex signal Y (n) and an index channel e (8, …, 15) of the second area, and finally measures the frequency f of the signal branch complex signal Y (n) i hat Instantaneous frequency estimation of output intermediate frequency signal
The corresponding expression is:
as shown in FIG. 4, the instantaneous eight-fold decimation unit is based on 16 paths of 156.25MHz digital intermediate frequency sampled signals y (n), and an intermediate frequency signal instantaneous frequency estimate
Generating eight-time decimated 2-way zero intermediate frequency digital signal y D1 (n) with a bit width of 10 bits and generating 16-path digital zero intermediate frequency sampling signal y by FIFO bit width conversion technique D2 (n) the bit width is 10 bits, and the operation clock frequency is 19.53125MHz.
And a quadrature digital down-conversion unit in the instantaneous octave decimation unit is used for carrying out digital orthogonalization on 16 paths of 156.25MHz digital intermediate frequency sampling signals y (n) to generate 8 paths of 156.25MHz complex intermediate frequency signals Z (n).
The instantaneous eight-time pumpingA second frequency shift modulation unit in the fetch unit for estimating the instantaneous frequency of the intermediate frequency signal
The 8 paths of 156.25MHz complex intermediate frequency signals Z (n) are frequency shifted to zero frequency, and 8 paths of 156.25MHz complex zero intermediate frequency signals Zo (n) are generated.
The instantaneous eight-time decimation unit generates a zero intermediate frequency digital signal y D1 And (n), the order of the FIR filter of the filtering and extracting unit is set as a 64-order optimal filter, the in-band ripple of the FIR filter is 0.1dB, and the out-of-band rejection depth of the FIR filter is 60dB. Thus, at the instant frequency estimation of the intermediate frequency signal
And the stray outside the left 78.125MHz is filtered out, so that the stray of the AD device is reduced.
The filtering extraction unit is used for extracting eight times of 8 paths of 156.25MHz complex zero intermediate frequency signals Zo (n) after filtering and outputting 2 paths of zero intermediate frequency digital signals y D1 And (n) generating 16 paths of digital zero intermediate frequency sampling signals by using an FIFO bit width conversion technology, wherein the bit width is 10 bits, and the operating clock frequency is 19.53125MHz.
The QDR memory delay unit sets the QDR address bit width to 19 bits and the data bit width to 144 bits. When the 3.3V width-keeping pulse signal indicates high level, 16 paths of digital zero intermediate frequency sampling signals y are transmitted D2 And (n) writing the signal into QDR after intercepting 9 bits, wherein the read address is slower than the write address by tau clock beats, and the duration of each beat is the reciprocal of the operating clock frequency of 19.53125MHz (as can be seen, the maximum target simulation distance is expanded to eight times through clock speed reduction, and 500 kilometer 8 is not larger than 4000 kilometers). Outputting zero intermediate frequency delayed digital signal y according to read data D2 (n- τ) having a bit width of 9 bits and an operating clock frequency of 19.53125MHz, where τ is the target number of delay beats:
in the formula, R 0 Representing the relative distance between the radar and the simulated target; v denotes radar andsimulating a velocity between the targets; a represents the acceleration between the radar and the simulated target; c represents the speed of light in air; t is clk Representing the running period of the FPGA digital signal clock; t represents the target motion time.
The frequency shift modulation unit delays the digital signal y based on zero intermediate frequency D2 (n- τ) having a bit width of 9 bits, an operation clock frequency of 19.53125MHz, and a shift frequency of eight times the extracted target analog signal
Its bit width is 10 bits, and its running clock frequency is 19.53125MHz, in which f d For target motion doppler, the corresponding expression is:
wherein V represents the velocity between the radar and the simulated target; a represents the acceleration between the radar and the simulated target; c represents the speed of light in air;
representing an instantaneous frequency estimate of the intermediate frequency signal.
As shown in FIG. 5, the instantaneous octave interpolation unit is based on the instantaneous frequency value of the digital intermediate frequency signal
And eight times of extraction target analog signal output by frequency shift modulation unit
The bit width is 10 bits, the operation clock frequency is 19.53125MHz, and eight times of interpolation 16 paths of parallel digital intermediate frequency target analog signals are generated
The bit width is 10 bits, and the running clock frequency is 156.25MHz.
Instantaneous eight-time interpolation unit for generating 16-path parallel digital intermediate frequency target analog signalNumber (C)
And the order of the FIR filter of the filtering interpolation unit is set as a 64-order optimal filter, the in-band ripple of the FIR filter is 0.1dB, and the out-of-band rejection depth of the FIR filter is 60dB. Thus, at intermediate frequency signal frequencies
Aliasing signals outside the left and right 78.125MHz can be filtered out, and the signal stray is guaranteed.
The filtering interpolation unit in the instantaneous octave interpolation unit extracts the target analog signal of octave output by the frequency shift modulation unit
Its bit width is 10 bits, operation clock frequency is 19.53125MHz, and after interpolation eight times and filtering, 8-path 156.25MHz target analog complex zero intermediate frequency signal Co (n) is generated.
A third frequency shift modulation unit in the instantaneous octave interpolation unit estimates the instantaneous frequency of the intermediate frequency signal
Instantaneous frequency estimation of frequency superposition intermediate frequency signal Co (n) of 8 paths of 156.25MHz target analog complex zero intermediate frequency signals
Generating 8 paths of 156.25MHz target analog complex intermediate frequency signals C (n).
The orthogonal digital up-conversion unit in the instantaneous octave interpolation unit carries out digital inverse orthogonalization on 8 paths of 156.25MHz target analog complex intermediate frequency signals C (n) to generate 16 paths of parallel digital intermediate frequency target analog signals
The bit width is 10 bits, and the running clock frequency is 156.25MHz.
DAC sampling unit pair 16-path parallel digital intermediate frequency target analog signal
The bit width is 10 bits, the operation clock frequency is 156.25MHz, and the two paths of 1.25GSPS intermediate frequency are divided to be output to the DAC module.
EXAMPLE five
In a further embodiment based on the first embodiment, a path of intermediate frequency fast frequency measurement unit of the 16-phase low spurious large delay DRFM target analog 2.5GSPS digital signal FPGA module, a logic unit Slice LUT and a Register thereof, a storage unit RAMB18E1, and a multiplier DSP48E1 consume, as shown in table 1 below.
TABLE 1 frequency estimation resource occupancy
| Resource type | Has been used | All are | Percentage of used |
| Registers | 33656 | 508400 | 6.63 |
| Slice LUTs | 18734 | 254200 | 7.37 |
| RAMB18E1s | 20 | 1590 | 1.26 |
| DSP48E1s | 192 | 1540 | 12.47 |
The static time sequence analysis result shows that the maximum working period of a key path of the intermediate frequency rapid frequency measurement unit is 4.436ns, the highest working frequency is 225.428MHz, and therefore the highest working frequency of the system cannot exceed 225.428MHz. Based on the above discussion, one path of 2.5GSPS intermediate frequency signal of the system is divided into 16 paths in the FPGA to operate, and the digital system clock is 156.25MHz, which meets the timing sequence requirement.
An instantaneous eight-time extraction unit, a QDR control unit, a frequency shift modulation unit and an instantaneous eight-time interpolation unit of a 16-phase low-spurious large-delay DRFM target analog 2.5GSPS digital signal FPGA module, a logic unit Slice LUT and a Register thereof, a storage unit RAMB18E1 and a multiplier DSP48E1 consume, as shown in the following table 2.
TABLE 2DRFM resource occupancy
| Resource type | Has been used | All are | Percentage of used |
| Registers | 113274 | 508400 | 22.28 |
| Slice LUTs | 68578 | 254200 | 26.98 |
| RAMB18E1s | 406 | 1590 | 25.53 |
| DSP48E1s | 338 | 1540 | 21.95 |
The static time sequence analysis result shows that the maximum working period of the key path of the instantaneous eight-time extraction unit, the QDR control unit, the frequency shift modulation unit and the instantaneous eight-time interpolation unit is 5.217ns, and the highest working frequency is 191.681MHz, so that the highest working frequency of the system cannot exceed 191.681MHz. Based on the above discussion, one path of 2.5GSPS intermediate frequency signal of the system is divided into 16 paths in the FPGA to operate, and the digital system clock is 156.25MHz, wherein the system clock of the QDR control and frequency shift modulation unit is only 19.531MHz, which meets the timing sequence requirement.
The low-stray large-delay digital frequency storage device based on the FPGA and the application method thereof show that the product test result of the initial debugging shows that: the product can achieve-55 dBc in the input intermediate frequency range of 1.35-2.4 GHz at the normal temperature stray of the target, and the target simulation distance is as far as 4000 km.
The stray normal temperature test results are shown in table 3, and the devices are not different slightly.
TABLE 3 stray Normal temperature test results
| Intermediate frequency | 1.35-2.4 GH stray | Intermediate frequency | 1.35-2.4 GHz stray |
| 1.35GHz | -56dBc | 1.95GHz | -57dBc |
| 1.45GHz | -58dBc | 2.05GHz | -57dBc |
| 1.55GHz | -57dBc | 2.15GHz | -56dBc |
| 1.65GHz | -57dBc | 2.25GHz | -56dBc |
| 1.75GHz | -58dBc | 2.35GHz | -56dBc |
| 1.85GHz | -61dBc | 2.40GHz | -55dBc |
EXAMPLE six
In one embodiment, an application method of a digital frequency storage device with low spurious large delay is provided, which specifically includes the following steps:
step 1, after the equipment is powered on, initializing relevant configuration parameters and enabling relevant modules to be in a normal working state;
specifically, the ADC sampling unit completes configuration of two 2.5GSPS channels in the ADC module, so that the ADC module performs normal sampling on the intermediate frequency input 2.5GSPS to obtain y (n); the DAC sampling unit completes the configuration of a DAC module 2.5 GSPS; the QDR storage delay unit completes the initialization of the QDR module;
step 2, after the ADC module works normally, the ADC module collects a digital intermediate frequency sampling signal y (n) and transmits the digital intermediate frequency sampling signal y (n) to the FPGA module;
step 3, processing the received signal by using an intermediate frequency rapid frequency measurement unit in the FPGA module to obtain the instantaneous frequency estimation of the intermediate frequency signal
Step 4, estimating instantaneous frequency of instantaneous eight-time extraction unit in FPGA module based on intermediate frequency signal
Generating an eight-fold decimated digital zero intermediate frequency sampled signal y D2 (n)；
Step 5, a QDR storage delay unit in the FPGA module indicates the digital zero intermediate frequency sampling signal y based on the 3.3V width-keeping pulse signal D2 (n) storing and outputting the zero intermediate frequency delay digital signal y D2 (n-τ)；
Step 6, the frequency shift modulation unit in the FPGA module delays the digital signal y based on zero intermediate frequency D2 (n-tau) frequency shift to generate eight times of extracted target analog signal
Step 7, estimating instantaneous frequency of instantaneous eight interpolation units in FPGA module based on intermediate frequency signal
Eight-time extraction target analog signal of sum frequency shift modulation unit
Generating octave interpolated digital intermediate frequency target analog signal
Step 8, simulating the low-spurious large-delay DRFM target analog 2.5GSPS digital intermediate frequency target analog signal by a DAC sampling unit in the FPGA module
And carrying out intermediate frequency output.
In conclusion, the invention has the following advantages:
1. the invention adopts the instantaneous eight-time extraction and the instantaneous eight-time interpolation method to reduce the capacity requirement of the QDR module memory, improve the layout and wiring capacity of the FPGA module, increase the target simulation distance by seven times on the basis of reducing the stray caused by the AD device, and simultaneously reduce the normal-temperature stray of the AD device to be more than-55 dBc.
2. The adopted FPGA provides device guarantee for software upgrading.
3. The adopted ADC module can simultaneously realize two paths of intermediate frequency signal 2.5GSPS sampling, and the two paths of low-stray large-delay target simulation can be simultaneously realized by matching with the DAC module, so that the flexibility of the system is improved.
4. The DRFM device and the method with low stray and large delay can be used for testing the detection and tracking functions of a radar on a long-distance target, can be separated from the actual working environment during testing, and are easy to test whether a product can work normally or not.
5. The adopted DRFM device with low stray and large delay is small in size, simple in hardware circuit and convenient to popularize and use.
6. The adopted complex Doppler modulation technology can realize the target simulation of two paths of intermediate frequency signals 2.5GSPS sampling signals under the condition of less FPGA resources.
As noted above, while the present invention has been shown and described with reference to certain preferred embodiments, it is not to be construed as limited to the invention itself. Various changes in form and detail may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (10)
1. A digital frequency storage device with low spurious large delay is characterized by comprising the following modules:
the ADC module is used for simulating intermediate frequency sampling and generating a digital intermediate frequency sampling signal;
the FPGA module is connected with the ADC module and used for receiving the digital intermediate-frequency sampling signal output by the ADC module, and carrying out target simulation on the digital intermediate-frequency sampling signal according to preset target time delay and echo Doppler to generate a digital intermediate-frequency target simulation signal;
the QDR module is connected with the FPGA module and used for receiving the digital intermediate-frequency target analog signal output by the FPGA and storing and reading the output signal of the FPGA module; meanwhile, according to read-write control input by the FPGA module, the digital zero intermediate frequency sampling signal is output in a delayed mode to generate a zero intermediate frequency delay signal;
and the DAC module is connected with the FPGA module and used for quantizing the digital intermediate-frequency target analog signal output by the FPGA module and generating an analog intermediate-frequency signal.
2. A digital frequency storage device with low spurious large delay according to claim 1,
the programming of FPGA module adopts pipeline structure's high cohesive modular unit of low coupling, further includes:
the ADC sampling unit is used for configuring a register in the ADC module and sampling a digital intermediate frequency sampling signal;
the intermediate frequency rapid frequency measurement unit is connected with the ADC sampling unit and is used for performing rapid intermediate frequency measurement on digital sampling;
the instantaneous eight-time extracting unit is connected with the ADC sampling unit and the intermediate frequency rapid frequency measuring unit, and is used for extracting eight times of the digital intermediate frequency sampling signal to generate a digital zero intermediate frequency sampling signal;
the QDR storage delay unit is connected with the instantaneous eight-time extraction unit and is used for carrying out storage delay on the zero intermediate frequency digital signal;
the first frequency shift modulation unit is connected with the QDR storage delay unit and is used for performing Doppler frequency shift on the zero intermediate frequency digital signal;
the instantaneous eight-time interpolation unit is connected with the intermediate frequency rapid frequency measurement unit and the frequency shift modulation unit and is used for carrying out zero intermediate frequency conversion on the eight-time extracted target analog signals and interpolating eight times of zero intermediate frequency digital signals to generate digital intermediate frequency target analog signals;
and the DAC sampling unit is connected with the instantaneous octave interpolation unit and used for configuring a register of the DAC module and converting the digital intermediate frequency target analog signal into a data format required by the DAC module.
3. A digital frequency storage device with low spurious large delay according to claim 2,
based on 16 paths of 156.25MHz digital intermediate frequency sampling signals y (n) and intermediate frequency signal instantaneous frequency estimation
The instantaneous eight-time decimation unit is used for generating 2 paths of zero intermediate frequency digital signals y decimated by eight times D1 (n) the bit width is 10 bits, and 16 paths of digital zero intermediate frequency sampling signals y are generated through the FIFO bit width conversion technology D2 (n) the bit width is 10 bits, and the operation clock frequency is 19.53125MHz.
4. A digital frequency storage device with low spurious large delay according to claim 3,
the instantaneous eight-time decimation unit generates a zero intermediate frequency digital signal y D1 And (n), the corresponding FIR filter order is preset to be a 64-order optimal filter, the in-band ripple is 0.1dB, and the out-of-band rejection depth is 60dB.
5. A digital frequency storage device with low spurious large delay according to claim 3,
the QDR storage delay unit presets the QDR address bit width to 19 bits and the data bit width to 144 bits; when the 3.3V width-keeping pulse signal indicates high level, 16 paths of digital zero intermediate frequency sampling signals y are transmitted D2 (n) intercepting 9 bits and writing the bits into a QDR module;
the read address is slower than the write address by tau clock beats, and the duration of each beat is a digital zero intermediate frequency sampling signal y D2 (n) outputting a zero intermediate frequency delayed digital signal y according to read data control by operating the reciprocal of the clock frequency D2 (n- τ) having a bit width of 9 bits, where τ is expressed as a target delay beat number by:
in the formula, R 0 Representing the relative distance between the radar and the simulated target; v represents the velocity between the radar and the simulated target; a represents the acceleration between the radar and the simulated target; c represents the speed of light in air; t is clk Representing the running period of the FPGA digital signal clock; t represents the target motion time.
6. A digital frequency storage device with low spurious large delay according to claim 5,
delaying the digital signal y at zero intermediate frequency D2 When the (n-tau) operation clock frequency is 19.53125MHz, the first frequency shift modulation unit delays the digital signal y based on the zero intermediate frequency with the bit width of 9 bits D2 (n-tau), frequency-shifting the signal to eight times to extract the target analog signal
Bit width of 10 bits, f d As target motion doppler, the corresponding expression is:
wherein V represents the velocity between the radar and the simulated target; a represents the acceleration between the radar and the simulated target; c represents the speed of light in air;
representing an instantaneous frequency estimate of the intermediate frequency signal.
7. A digital frequency storage device with low spurious large delay according to claim 3,
the instantaneous octave interpolation unit estimates the instantaneous frequency of the intermediate frequency signal based on the digital intermediate frequency signal
And eight times of extraction target analog signal output by frequency shift modulation unit
Extracting target analog signal by eight times
When the operating clock frequency is 19.53125MHz, eight-fold interpolated 16-path digital intermediate frequency target analog signals are generated
The bit width is 10 bits, and the running clock frequency is 156.25MHz.
8. A digital frequency storage device with low spurious large delay according to claim 3,
in the above-mentionedInstantaneous eight-time interpolation unit for generating digital intermediate frequency target analog signal
In the process, the corresponding FIR filter order is preset to be a 64-order optimal filter, the in-band ripple is 0.1dB, the out-of-band rejection depth is 60dB, and the instantaneous frequency estimation of the intermediate frequency signal is filtered
Aliasing signals outside 78.125MHz float to the left and right.
9. A digital frequency storage device with low spurious large delay according to claim 2,
the instantaneous eight-time extraction unit comprises: the orthogonal digital down-conversion unit, the second frequency shift modulation unit and the filtering extraction unit are used for generating digital zero intermediate frequency sampling signals and filtering out stray signals in a preset floating range;
the instantaneous octave interpolation unit includes: the filter interpolation unit, the third frequency shift modulation unit and the orthogonal digital up-conversion unit; the digital intermediate frequency conversion circuit is used for carrying out zero intermediate frequency conversion on intermediate frequency digital samples and interpolating eight times of zero intermediate frequency digital signals to generate digital intermediate frequency target analog signals.
10. An application method of a digital frequency storage device with low spurious large delay is based on any one of the devices in claims 1-9, and is characterized by comprising the following steps:
step 1, after the equipment is powered on, initializing relevant configuration parameters and enabling relevant modules to be in a normal working state;
step 2, the ADC module collects a digital intermediate frequency sampling signal y (n) and transmits the digital intermediate frequency sampling signal y (n) to the FPGA module;
step 3, obtaining instantaneous frequency estimation of the intermediate frequency signal by utilizing an intermediate frequency rapid frequency measurement unit in the FPGA module
Step 4, estimating instantaneous frequency of instantaneous eight-time extraction unit in FPGA module based on intermediate frequency signal
Generating eight times decimated zero intermediate frequency digital signal y D1 (n) and generating 16 paths of digital zero intermediate frequency sampling signals y through FIFO bit width conversion technology D2 (n)；
Step 5, a QDR storage delay unit in the FPGA module indicates the digital zero intermediate frequency sampling signal y based on the width-preserving pulse signal D2 (n) storing and outputting the zero intermediate frequency delayed digital signal y D2 (n-τ)；
Step 6, the frequency shift modulation unit in the FPGA module delays the digital signal y based on zero intermediate frequency D2 (n-tau) frequency shift to generate eight times of extracted target analog signal
Step 7, estimating instantaneous frequency of instantaneous eight interpolation units in FPGA module based on intermediate frequency signal
Eight-time extraction target analog signal of sum frequency shift modulation unit
Generating octave interpolated digital intermediate frequency target analog signal
Step 8, simulating the low-spurious large-delay DRFM target analog 2.5GSPS digital intermediate frequency target analog signal by a DAC sampling unit in the FPGA module
And carrying out intermediate frequency output.
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