CN115241245A

CN115241245A - Display panel, manufacturing method thereof and display device

Info

Publication number: CN115241245A
Application number: CN202210730732.0A
Authority: CN
Inventors: 唐亮; 崔星宇
Original assignee: BOE Technology Group Co Ltd; Ordos Yuansheng Optoelectronics Co Ltd
Current assignee: BOE Technology Group Co Ltd; Ordos Yuansheng Optoelectronics Co Ltd
Priority date: 2022-06-24
Filing date: 2022-06-24
Publication date: 2022-10-25

Abstract

The embodiment of the disclosure provides a display panel, a manufacturing method thereof and a display device, and belongs to the technical field of display. The display panel comprises an interlayer dielectric layer, a cutting channel and a first flat layer, wherein the interlayer dielectric layer is positioned on one side of a substrate. The cutting channel comprises a plurality of through holes penetrating through the interlayer dielectric layer, and the first flat layer is located on one side, far away from the substrate, of the interlayer dielectric layer. Because one side of the first flat layer close to the display area inclines along the direction far away from the substrate, and the side of the first flat layer far away from the display area and the cutting channel have a distance, the distance can be flexibly set, so that when the anode layer is formed by adopting a composition process, exposure light is reflected along different directions at the inclined side of the first flat layer and the side of the interlayer dielectric layer far away from the substrate, the exposure of the through hole is better, and the anode layer is prevented from being remained at the through hole. I.e. such that the anode layer formed at the side of the second insulation facing away from the substrate is only located in the display area.

Description

Display panel, manufacturing method thereof and display device

Technical Field

The disclosure relates to the technical field of display, and in particular to a display panel, a manufacturing method thereof and a display device.

Background

Currently, in a manufacturing process of a display panel, a display mother board including a plurality of display panels is generally formed first, and then the display mother board is cut to obtain a single display panel.

Each display panel in the display mother substrate generally includes a substrate, a plurality of insulating layers, a planarization layer, and an anode layer, which are sequentially stacked in a direction away from the substrate, and a dicing lane at one side of the substrate, along which dicing is possible. In the related art, the anode layer remains in the scribe line, which affects the yield of the display panel.

Disclosure of Invention

The embodiment of the disclosure provides a display panel, a manufacturing method thereof and a display device, which can solve the problem of anode layer residue at a cutting path position in the related art.

The technical scheme is as follows:

in one aspect, there is provided a display panel including:

a substrate having a display area and a non-display area at least partially surrounding the display area;

the interlayer dielectric layer is positioned on one side of the substrate and positioned in the display area and the non-display area;

the cutting channel is positioned on one side of the substrate and in the non-display area, and comprises a plurality of through holes which penetrate through the interlayer dielectric layer and are sequentially distributed along a first direction;

the first flat layer is positioned on one side, far away from the substrate, of the interlayer dielectric layer and positioned in the non-display area, the first flat layer is far away from the display area relative to the cutting channel, a distance exists between one side, close to the display area, of the first flat layer and one side, far away from the display area, of the cutting channel, and the first flat layer inclines towards the direction far away from the cutting channel along the direction far away from the substrate;

and the anode layer is positioned on one side of the first flat layer, which is far away from the substrate, and is positioned in the display area.

Optionally, the non-display area has a connection area and a fan-out area arranged in sequence along a direction close to the display area; the first flat layer is located at the connection region; the display panel further includes:

the first metal wire extends along a second direction, is positioned on one side, far away from the substrate, of the interlayer dielectric layer and is positioned in the connecting area and the fan-out area, and the second direction is intersected with the first direction;

the orthographic projection of the first flat layer on the substrate is overlapped with the orthographic projection part of the first metal wire on the substrate, and except the overlapped part, a distance exists between one side of the rest part of the first flat layer close to the display area and one side of the cutting street far away from the display area.

Optionally, in the second direction, the first flat layer has a trench recessed in a direction away from the cutting street;

the distance between one side of the rest part of the first flat layer close to the display area and one side of the cutting way far away from the display area is equal to the maximum width of the digging groove in the second direction.

Optionally, an orthographic projection of the grooves on the substrate is rectangular, circular, oval or trapezoidal.

Optionally, the display panel further includes:

the pin part is positioned on one side of the interlayer dielectric layer, which is far away from the substrate, and is positioned in the fan-out area, and the pin part comprises a plurality of routing pins which are arranged at intervals along the first direction;

in the first direction, the length of the digging groove is larger than or equal to that of the pin part, and the pin part is positioned in the range limited by extension lines on two sides of the digging groove.

Optionally, the first metal line includes a first power line and a second power line arranged at an interval along the first direction, and a potential of a first power signal provided by the first power line is greater than a potential of a second power signal provided by the second power line;

wherein the cutout and the pin portion are located between the first power line and the second power line.

Optionally, the display panel further includes:

the second metal wire extends along the first direction, is positioned on one side, close to the substrate, of the interlayer dielectric layer and is positioned in the connecting area;

an orthographic projection of the first flat layer on the substrate covers an orthographic projection of the second metal line on the substrate.

Optionally, the scribe line is located at the connection region, and the scribe line is close to the fan-out region with respect to the first flat layer.

Optionally, the first direction and the second direction are both directions parallel to a display surface of the display panel, and the first direction is perpendicular to the second direction.

Optionally, the display panel further includes:

the buffer layer is positioned between the interlayer dielectric layer and the substrate and positioned in the display area and the non-display area;

a transistor located in the display region, the transistor including: the active layer and the gate insulating layer are positioned between the buffer layer and the interlayer dielectric layer and are sequentially stacked along the direction far away from the substrate, the gate metal layer is positioned between the gate insulating layer and the interlayer dielectric layer, and the source drain metal layer is positioned between the interlayer dielectric layer and the second flat layer;

the via hole penetrates through the interlayer dielectric layer and the gate insulating layer and exposes the buffer layer;

and in the display panel with a first metal wire, a second metal wire and a pin part, the first metal wire and the pin part are positioned on the same layer with the source drain metal layer, and the second metal wire and the gate metal layer are positioned on the same layer.

Optionally, the display panel further includes:

the second flat layer is positioned on one side, far away from the substrate, of the interlayer dielectric layer and positioned in the display area, and the second flat layer and the first flat layer are positioned on the same layer.

Optionally, the thickness of the first flat layer is smaller than the thickness of the second flat layer.

Optionally, a distance between one side of the first flat layer close to the display area and one side of the cutting street far away from the display area is greater than 10 micrometers.

In another aspect, there is provided a method for manufacturing a display panel, the method being used for manufacturing the display panel according to the above aspect, the method including:

providing a substrate having a display area and a non-display area at least partially surrounding the display area;

forming an interlayer dielectric layer on one side of the substrate, wherein the interlayer dielectric layer is positioned in the display area and the non-display area;

forming a cutting channel penetrating through the interlayer dielectric layer on one side of the substrate, wherein the cutting channel is positioned in the non-display area and comprises a plurality of through holes which are sequentially distributed along a first direction;

forming a first flat layer on one side of the interlayer dielectric layer far away from the substrate, wherein the first flat layer is positioned in the non-display area, the first flat layer is far away from the display area relative to the cutting channel, a distance exists between one side of the first flat layer close to the display area and one side of the cutting channel far away from the display area, and the first flat layer inclines towards the direction far away from the cutting channel along the direction far away from the substrate;

and forming an anode layer on one side of the first flat layer far away from the substrate, wherein the anode layer is positioned in the display area.

In still another aspect, there is provided a display device including: the display panel according to the above aspect.

To sum up, the beneficial effects brought by the technical scheme provided by the embodiment of the present disclosure at least can include:

a display panel, a manufacturing method thereof and a display device are provided. The display panel comprises an interlayer dielectric layer, a cutting channel and a first flat layer, wherein the interlayer dielectric layer is positioned on one side of a substrate. The cutting channel comprises a plurality of through holes penetrating through the interlayer dielectric layer, and the first flat layer is located on one side, far away from the substrate, of the interlayer dielectric layer. Because one side of the first flat layer close to the display area inclines along the direction far away from the substrate, and the side of the first flat layer far away from the display area and the cutting channel have a distance, the distance can be flexibly set, so that when the anode layer is formed by adopting a composition process, exposure light is reflected along different directions at the inclined side of the first flat layer and the side of the interlayer dielectric layer far away from the substrate, the exposure of the through hole is better, and the anode layer is prevented from being remained at the through hole. I.e. so that the anode layer formed at the side of the second insulation from the side remote from the substrate is only located at the display area.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present disclosure, and it is obvious for those skilled in the art to obtain other drawings based on the drawings without creative efforts.

Fig. 1 is a schematic diagram of a substrate in a display panel provided by an embodiment of the present disclosure;

fig. 2 is a schematic structural diagram of a display panel provided in an embodiment of the present disclosure;

fig. 3 is a cross-sectional view of a display panel provided by an embodiment of the present disclosure;

fig. 4 is a cross-sectional view of another display panel provided by an embodiment of the present disclosure;

fig. 5 is a cross-sectional view of yet another display panel provided by an embodiment of the present disclosure;

fig. 6 is a schematic diagram of a substrate in another display panel provided by an embodiment of the present disclosure;

fig. 7 is a schematic structural diagram of another display panel provided in the embodiment of the present disclosure;

fig. 8 is a cross-sectional view of still another display panel provided by an embodiment of the present disclosure;

fig. 9 is a cross-sectional view of still another display panel provided by an embodiment of the present disclosure;

fig. 10 is a schematic structural diagram of another display panel provided in the embodiment of the present disclosure;

fig. 11 is a cross-sectional view of still another display panel provided by an embodiment of the present disclosure;

fig. 12 is a flowchart of a method for manufacturing a display panel according to an embodiment of the disclosure;

fig. 13 is a schematic structural diagram of a display device according to an embodiment of the present disclosure.

Detailed Description

In order to make the objects, technical solutions and advantages of the present disclosure more apparent, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

Fig. 1 is a schematic structural diagram of a display panel according to an embodiment of the disclosure. As shown in fig. 1, the display panel includes:

a substrate 01 having a display area A1 and a non-display area B1 at least partially surrounding the display area A1. For example, in the substrate 01 shown in fig. 1, the non-display area B1 is located on the left side of the display area A1, adjacent to (i.e., adjacent to and in contact with) the display area A1 to partially surround the display area A1. Of course, also not limited to the left side, the non-display area B1 may be located at a lower side and/or an upper side of the display area A1 as in connection with fig. 1. Alternatively, the non-display area B1 may also be located on each side of the display area A1 to surround the display area A1.

In addition, it should be noted that the area of the display area A1 is generally much larger than that of the non-display area B1, and the drawings are only schematic illustrations and do not limit the areas of the display area A1 and the non-display area B1.

On the basis of the structure shown in fig. 1, fig. 2 shows a top view of a display panel provided by an embodiment of the present disclosure. Fig. 3 is a cross-sectional view of the structure shown in fig. 2 in the MM' direction. Also, fig. 2 shows only the non-display area B1, and fig. 3 shows the display area A1 and the non-display area B1. As can be seen from fig. 2 and 3, the display panel according to the embodiment of the present disclosure further includes:

an inter-layer di-electric (ILD) layer 02, the ILD layer 02 being positioned at one side of the substrate 01 and positioned in the display area A1 and the non-display area B1. That is, a part of the interlayer dielectric layer 02 is located in the display region A1, another part is located in the non-display region B1, and the entire layer covers the substrate 01 side.

And a cutting street 03, wherein the cutting street 03 is positioned on one side of the substrate 01 and is positioned in the non-display area B1. The scribe line 03 includes a plurality of via holes K1 penetrating through the interlayer dielectric layer 02 and sequentially arranged along a first direction X1.

Wherein, only one via K1 is schematically shown in the cross-sectional view of fig. 3. When the display panel is manufactured, the display mother board may be cut along the cutting street 03, that is, cut at the via hole K1, to obtain a single display panel. Optionally, the sidewall of the via K1 may be perpendicular to the substrate 01 to facilitate cutting.

A first Planarization (PLN) layer 04. The first planarization layer 04 is located on the interlayer dielectric layer 02 at a side away from the substrate 01 and located in the non-display region B1. And, the first flat layer 04 is far away from the display area A1 relative to the cutting street 03, that is, the first flat layer 04 is located on the side of the cutting street 03 far away from the display area A1.

Wherein a side of the first planarization layer 04 close to the display area A1 (i.e., side f indicated in the figure) is inclined in a direction away from the substrate 01 toward a direction away from the scribe line 03. In other words, an included angle α between the side of the first planarization layer 04 close to the display area A1 and the upper surface of the interlayer dielectric layer 02 far from the substrate 01 is an obtuse angle, which is greater than 90 degrees. And a distance d1 exists between one side of the first flat layer 04 close to the display area A1 and one side of the cutting street 03 far away from the display area A1. That is, the orthographic projection of the side f on the substrate 01 does not overlap the orthographic projection of the side wall of the via hole K1 included in the scribe lane 03 on the substrate 01 on the side away from the display area A1. Based on the position of the first planarization layer 04, the side of the first planarization layer 04 close to the display area A1 can be regarded as a boundary of the first planarization layer 04, and the following embodiment is referred to as a tilt boundary.

And, further includes an Anode (Anode) layer 05. The anode layer 05 is located on the side of the first planarization layer 04 away from the substrate 01 and located in the display area A1.

Note that the anode layer 05 can be formed by a one-step patterning process using a mask. The primary patterning process comprises the following steps: coating photoresist, exposing, developing, etching, stripping the photoresist and the like. That is, as shown in fig. 4, the anode thin film 05M may be formed prior to the side of the first planarization layer 04 away from the substrate 01, and then the anode thin film 05M may be subjected to a patterning process once using the mask M1 to form the anode layer 05.

Since the scribe line 03 generally has a deeper via K1, it can also be seen from fig. 4 that the Photoresist (PR) applied at the via K1 is generally thicker. On this basis, if the inclined boundary of the first flat layer 04 is set to contact with the side of the scribe line 03 far away from the display area A1, when the light L00 is used for exposure, the light is all reflected obliquely in the same direction on the inclined boundary of the first flat layer 04, and thus the exposure at the via hole K1 is insufficient, and the anode layer 05 remains at the via hole K1 (refer to the drawing shown in fig. 5), so that the formed anode layer 05 is not only located at the display area A1, but also partially located at the via hole K1 of the non-display area B1, and the product yield is poor. In addition, since the anode layer 05 is a highly reflective film layer, it is more likely to leave residues at via holes than other film layers.

In the embodiment of the present disclosure, by setting the side of the first flat layer 04 close to the display area A1 and the side of the scribe line 03 far from the display area A1 to have the distance d1, that is, by making the inclined boundary of the first flat layer 04 not contact with the side of the scribe line 03 far from the display area A1, the distance d1 may be set flexibly, for example, by setting the distance d1 to be larger, so that most of the side (i.e., the upper surface shown in fig. 3) of the interlayer dielectric layer 02 far from the substrate close to the via hole K1 is not covered by the first flat layer 04, and the light L00 during exposure is reflected in different directions at the inclined boundary and the part of the side of the interlayer dielectric layer 02 far from the substrate, which is not covered by the first flat layer 04, rather than being totally reflected obliquely in the same direction. On this basis, it is possible to ensure sufficient exposure amount and avoid the anode layer 05 remaining at the via hole K1, i.e., the anode layer 05 formed is located only in the display area A1 (see the drawing shown in fig. 4). Therefore, the good yield of the display product is ensured.

In summary, the embodiments of the present disclosure provide a display panel. The display panel comprises an interlayer dielectric layer, a cutting channel and a first flat layer, wherein the interlayer dielectric layer is positioned on one side of a substrate. The cutting channel comprises a plurality of through holes penetrating through the interlayer dielectric layer, and the first flat layer is located on one side, far away from the substrate, of the interlayer dielectric layer. Because one side of the first flat layer close to the display area inclines along the direction far away from the substrate, and the side of the first flat layer far away from the display area and the cutting channel have a distance, the distance can be flexibly set, so that when the anode layer is formed by adopting a composition process, exposure light is reflected along different directions at the inclined side of the first flat layer and the side of the interlayer dielectric layer far away from the substrate, the exposure of the through hole is better, and the anode layer is prevented from being remained at the through hole. I.e. so that the anode layer formed at the side of the second insulation from the side remote from the substrate is only located at the display area.

Alternatively, the distance d1 between the side of the first planarization layer 04 close to the display area A1 and the side of the scribe line 03 far from the display area A1 may be greater than 10 micrometers (μm). That is, in conjunction with fig. 2 and 3, the pitch d1>10 μm between the first planarization layer 04 and the via hole K1 may be set. For example, d1 can be set to 12 μm.

Optionally, fig. 6 is a schematic structural diagram of another display panel provided in the embodiment of the present disclosure. As shown in fig. 6, the non-display area B1 may have a connection area B11 and a fan-out area B12 sequentially arranged in a direction close to the display area A1. Here, as the name implies, the connection region B11 may refer to a region to which a signal line is connected to a circuit that supplies a signal to the signal line. The fan-out area B12 may refer to an area to which a signal line fans out (also referred to as a lead-out). Alternatively, the signal lines included in the connection region B11 may be signal lines for lighting test before shipment, such as switching signal lines and data line leads. The connection area B11 may be cut off when cut through the cutting street 03, and the display panel shipped from the factory does not include the connection area B11. The lighting signal may be input to the display area A1 through the fan-out area B12 to light up the pixels in the display area A1 in the display panel.

On the basis of the area division shown in fig. 6, fig. 7 shows a top view of another display panel provided by the embodiment of the present disclosure. Fig. 8 shows a cross-sectional view of the structure of fig. 7 in the MM' direction. Fig. 9 shows a cross-sectional view of the structure shown in fig. 7 in the NN' direction. As can be seen with reference to fig. 7 to 9, the first flat layer 04 recited in the embodiment of the present disclosure may be located only at the connection region B11. And, the display panel may further include:

the first metal line L1 extending in the second direction Y1 generally includes a plurality of lines. The first metal line L1 may be located on a side of the interlayer dielectric layer 02 away from the substrate 01, and may be located in the connection region B11 and the fan-out region B12. That is, a portion of each first metal line L1 may be located at the connection region B11, and another portion may be located at the fan-out region B12. In some embodiments, the first metal line L1 may also be fanned out to the display area A1 through the fan-out area B12. That is, the first metal line L1 may also be located in the display area A1.

As still referring to fig. 7, the first metal line L1 may include a first power line VDD and a second power line VSS spaced apart from each other along the first direction X1, and the first power line VDD may provide a first power signal having a potential greater than that of the second power line VSS. The first power line VDD and the second power line VSS may be fanned out to the display area A1 via the fan-out area B12, and connected to the pixels in the display area A1 for driving the pixels to emit light.

Alternatively, the first direction X1 and the second direction Y1 may both be directions parallel to the display surface of the display panel, and the second direction Y1 may intersect with the first direction X1. For example, the first direction X1 is perpendicular to the second direction Y1. Referring to the drawings, the MM 'direction in fig. 7 is the second direction Y1, and the NN' direction in fig. 8 is the first direction X1.

Alternatively, as can be seen with continued reference to fig. 7, the orthographic projection of the first planarization layer 04 on the substrate 01 and the orthographic projection of the first metal line L1 on the substrate 01 may partially overlap. And apart from the overlapping portion, the side of the first planarization layer 04 close to the display area A1 has the distance d1 from the side of the scribe lane 03 far from the display area A1. That is, in the embodiment of the present disclosure, it may be only provided that a portion of the inclined boundary of the first planarization layer 04 that is not overlapped with the first metal line L1 has a distance d1 from a side of the scribe lane 03 away from the display area A1. And as in the above embodiments, d1 may be set to be large, such as greater than 10 μm. Therefore, the anode layer 05 can be prevented from being left in the through hole K1, the metal wire can be protected, the metal wire is prevented from being corroded by external water and oxygen, and the good product yield is further ensured.

That is, in the embodiment of the present disclosure, as shown in fig. 2, the whole of the inclined boundary of the first flat layer 04 may be disposed at a larger distance from the side of the scribe line 03 away from the display area A1. Alternatively, as shown in fig. 7, only the portion of the inclined boundary of the first planarization layer 04 is spaced apart from the side of the scribe line 03 away from the display area A1 by a large distance. Provided that the distance d1 is set to ensure that no anode layer 05 remains at the via hole K1.

Alternatively, on the basis that the distance d1 between the portion where the inclined boundary of the first flat layer 04 is provided and the side of the scribe line 03 away from the display area A1 is large, as can be seen in fig. 7 and 9, in the second direction Y1, the first flat layer 04 may have a cutout C1 recessed in the direction away from the scribe line 03. That is, the first planarization layer 04 may be trenched to improve the problem of the residue of the anode layer 05. In addition, because no film layer is required to be newly added, the cost is not required to be increased, the process is simple, the cost is lower, and the method is suitable for mass production.

In this way, the distance d1 between the side of the remaining portion of the first planarization layer 04 close to the display area A1 and the side of the scribe lane 03 far from the display area A1 may be substantially equal to the maximum width w1 of the trench C1 in the second direction Y1. In other words, the width w1 of the digging groove C1 can be set to be greater than 10 μm according to the embodiment of the disclosure.

By way of example, as can be seen in conjunction with fig. 7 and 9, the orthographic projection of the trench C1 on the substrate 01 can be rectangular, circular, oval or trapezoidal. Of course, in some embodiments, the orthographic projection of the trench C1 on the substrate 01 may also have other shapes, such as an irregular shape, and the shape is not limited by the embodiments of the disclosure.

Optionally, still referring to fig. 7, it can be seen that the display panel according to the embodiment of the present disclosure may further include: the lead part 06. The pin part 06 may be located on a side of the interlayer dielectric layer 02 away from the substrate 01, and may be located only in the fan-out region B12. The lead part 06 may include a plurality of trace leads Pin spaced along the first direction X1, also referred to as Pin pins. Where a signal line or external circuitry may be tied. Fig. 7 only schematically shows 5 Pin pins.

In the first direction X1, the length l1 of the trench C1 may be greater than or equal to the length l2 of the lead part 06, that is, the length l1 of the trench C1 may be flexibly adjusted according to the Pin width of the Pin.

Also, the lead part 06 may be positioned within a range defined by extension lines of both sides of the cutout C1. Here, the extension line may refer to an extension line extending toward the lead part 06. As can be seen from fig. 7, the lead portion 06 is surrounded by the cutouts C1 on both sides in the first direction X1. So, can realize the effective protection to the Pin foot, avoid when seting up the digging groove, cause intercommunication between the different Pin feet, the signal takes place to crosstalk, has further ensured that the product yield is better.

Alternatively, still referring to fig. 7, on the basis that the first metal line L1 includes the first power line VDD and the second power line VSS, both the cutout C1 and the pin part 06 may be located between the first power line VDD and the second power line VSS. Therefore, the narrow frame design of the display panel can be facilitated.

Optionally, still referring to fig. 7, it can be seen that the display panel according to the embodiment of the present disclosure may further include: the second metal line L2 extending along the first direction X1 generally includes a plurality of lines. The second metal line L2 may be located on the side of the interlayer dielectric layer 02 close to the substrate 01 and only located at the connection region B11. In combination with the above embodiments, the second metal line L2 may be a signal line for lighting test, such as a Switch line Switch.

Wherein. An orthogonal projection of the first planarization layer 04 on the substrate 01 may cover an orthogonal projection of the second metal line L2 on the substrate 01. That is, referring to fig. 7 to 9, the second metal line L2 may be covered by the first planarization layer 04, and the groove is designed to be opened only to the side of the second metal line L2 close to the display area A1, but not to contact the side of the second metal line L2 close to the display area A1. Therefore, the residue of the anode layer 05 can be improved, and the reliable protection of the second metal line L2 can be ensured, so that the good product yield is further ensured.

Alternatively, as shown in another schematic region division diagram shown in fig. 7 and fig. 10, the scribe line 03 according to the embodiment of the disclosure may be located in the connection region B11 and near the fan-out region B12 with respect to the first flat layer 04. That is, the scribe line 03 is located on the side of the first flat layer 04 near the fan-out area B12. Of course, in some other embodiments, the cutting street 03 may also be located in the fan-out region B12 and closer to the connection region B11 than to the lead part 06. In other words, the scribe line 03 may be located on the side where the connection region B11 and the fan-out region B12 are adjacent, and located in the connection region B11 or the fan-out region B12. Still alternatively, the scribe line 03 may be partially located in the connection region B11 and partially located in the fan-out region B12. In addition, FIG. 10 also schematically identifies the design location of the pockets.

Alternatively, on the basis of the above drawings, fig. 11 shows a cross-sectional view of another display panel provided by the embodiment of the present disclosure, which includes a display area A1 and a non-display area B1. As shown in fig. 11, the display panel may further include:

buffer layer 07. The buffer layer 07 may be positioned between the interlayer dielectric layer 02 and the substrate 01, and positioned in the display area A1 and the non-display area B1. That is, a portion of the buffer layer 07 may be located in the display area A1, and another portion may be located in the non-display area B1.

And a second flat layer 08, wherein the second flat layer 08 can be positioned on the side of the interlayer dielectric layer 02 far away from the substrate 01 and positioned in the display area A1.

A transistor T1, and the transistor T1 may be located in the display area A1. Also, the transistor T1 may include: an active layer P1 and a Gate Insulator (GI) layer GI that are located between the buffer layer 07 and the interlayer dielectric layer 02 and are sequentially stacked in a direction away from the substrate 01, a gate metal layer GT that is located between the gate insulator GI and the interlayer dielectric layer 02, and a source drain metal layer SD that is located between the interlayer dielectric layer 02 and the second planar layer 08. That is, the transistor T1 shown in fig. 11 may be a transistor of a top gate structure. Of course, in some other embodiments, the transistor T1 may also be a transistor with a bottom gate structure.

The via hole K1 included in the cutting track 03 may penetrate through the interlayer dielectric layer 02 and the gate insulating layer GI, and expose the buffer layer 07, and the via hole K1 thus formed may be deep, so as to facilitate cutting. The second planarization layer 08 and the first planarization layer 04 may be located on the same layer. As can be seen from fig. 7 and 11, the first metal line L1 and the lead part 06 may be located on the same layer as the source/drain metal layer SD, and the second metal line L2 may be located on the same layer as the gate metal layer GT.

It should be noted that being located on the same layer may refer to a layer structure formed by forming a film layer for forming a specific pattern by using the same film formation process, and then patterning the film layer by using the same mask plate through a one-time patterning process. Depending on the specific pattern, one patterning process may include multiple exposure, development or etching processes, and the specific pattern in the formed layer structure may be continuous or discontinuous. That is, multiple elements, components, structures and/or portions located at the "same layer" are made of the same material and are formed through the same patterning process. Therefore, the manufacturing process and the manufacturing cost can be saved, and the manufacturing efficiency can be accelerated.

That is, in the embodiment of the present disclosure, the second planarization layer 08 located in the display area A1 and the first planarization layer 04 located in the non-display area B1 may be formed by one patterning process using the same material. The first metal line L1 and the lead part 06 in the non-display region B1, and the source-drain metal layer SD included in the transistor T1 in the display region A1 may be formed by a single patterning process using the same material. The second metal line L2 located in the non-display area B1 and the gate metal layer GT included in the transistor T1 located in the display area A1 may be formed by a single patterning process using the same material.

Alternatively, as can be seen by continuing to refer to fig. 11, in the display panel described in the embodiment of the present disclosure, the thickness of the first flat layer 04 may be smaller than that of the second flat layer 08, and the thickness direction may be perpendicular to the substrate 01. On this basis, the slope of the inclined boundary of the first planarization layer 04 can be made gentle, so that sufficient exposure can be ensured when the anode layer 05 is formed, and the anode layer 05 can be prevented from remaining in the via hole K1.

In an example, since the first and second planarization layers 04 and 08 are located on the same layer, when the first and second planarization layers 04 and 08 are formed simultaneously, a half-transmissive and half-reflective mask plate may be used, which has a wider application range.

It should be noted that, except for the deep hole position of the scribe line 03, the design of the embodiment of the present disclosure (for example, the design of the trench for the first flat layer 04) may be adopted, and the deep hole positions at other positions, which are likely to cause the anode layer to remain, may also be designed in the same manner, so as to effectively ensure a better product yield.

In addition, referring to fig. 11, the connection relationship and the material between the layers in the display panel are described as follows:

in one aspect, the display panel may further include: a light emitting layer, a Pixel Definition Layer (PDL), a Cathode (Cathode) layer, and a support layer PS, which are sequentially stacked on the anode layer 05 on the side away from the substrate 01. Fig. 11 schematically shows only the pixel defining layer PDL and the support layer PS.

On the other hand, the source drain metal layer SD may include: and the source metal layer S1 and the drain metal layer D1 are positioned on the same layer and are mutually spaced. The source metal layer S1 and the drain metal layer D1 may overlap the active layer P1 by penetrating the interlayer dielectric layer 02 and the gate insulating layer GI and exposing the overlapping hole of the active layer P1. Also, the active layer P1 may have a semiconducting region (also referred to as a channel region) and a conducting region (referred to as a source region and a drain region, respectively) at both sides of the channel region. Therein, the semiconducting region may be undoped or doped differently from the source and drain regions and thus have semiconducting properties. The region of conductivation may be doped and therefore conductive. The impurity to be doped may vary depending on the type of transistor (i.e., N-type or P-type). The source/drain metal layer SD may overlap the conductive region. The anode layer 05 may overlap the drain metal layer D1 by passing through the second planarization layer 08 and exposing a contact hole of the drain metal layer D1. In this way, the transistor T1 may transmit a driving voltage to the anode layer 05 through the drain metal layer D1, and the driving voltage and a driving voltage applied to the cathode layer may form a voltage difference, thereby driving the light emitting layer to emit light.

In general, a pixel includes a pixel circuit and a light-emitting element, and the light-emitting element includes the anode layer 05, the light-emitting layer, and the cathode layer described in the above embodiments. The pixel circuit includes a plurality of transistors such as a data writing transistor, a reset transistor, and a driving transistor, in which the driving transistor can be electrically connected to the anode layer 05 included in the light emitting element to supply a driving signal to the light emitting element, thereby driving the light emitting element to emit light. As such, the transistor T1 shown in fig. 11 may be referred to as a driving transistor.

Fig. 12 is a flowchart of a method for manufacturing a display panel according to an embodiment of the present disclosure, where the method may be used to manufacture the display panel shown in the above-mentioned drawings. As shown in fig. 12, the method includes:

step 1201, providing a substrate.

As shown in fig. 1, a substrate 01 may be provided having a display area A1 and a non-display area B1 at least partially surrounding the display area A1. Optionally, the substrate 01 provided may include: a glass substrate or a flexible substrate.

Step 1202, forming an interlayer dielectric layer on one side of the substrate.

Alternatively, an interlayer dielectric layer may be formed on the substrate by a single patterning process. As can be seen from fig. 3 and 11, the interlayer dielectric layer 02 may be formed in the display area A1 and the non-display area B1.

Step 1203, forming a scribe line penetrating through the interlayer dielectric layer on one side of the substrate.

Alternatively, a cutting path penetrating through the interlayer dielectric layer can be formed on the substrate by adopting a one-step patterning process. As can be seen from fig. 3 and 11, the formed scribe line 03 may be located in the non-display area B1 and include a plurality of via holes K1 sequentially arranged along the first direction X1.

And 1203, forming a first flat layer on one side of the interlayer dielectric layer, which is far away from the substrate.

Optionally, a first planarization layer may be formed on the side of the interlayer dielectric layer away from the substrate by using a one-step patterning process. As can be seen from fig. 3, the first planarization layer 04 may be formed only in the non-display area B1, the first planarization layer 04 is far away from the display area A1 relative to the scribe line 03, and a distance d1 may exist between a side of the first planarization layer 04 close to the display area A1 and a side of the scribe line 03 far away from the display area A1, and the first planarization layer is inclined in a direction away from the substrate 01 toward a direction away from the scribe line 03. For example, the pitch d1 may be greater than 10 μm.

And 1204, forming an anode layer on one side of the first flat layer far away from the substrate.

Alternatively, the anode layer may be formed on the side of the first planarization layer away from the substrate by a single patterning process. Moreover, as can be seen from the above embodiments, by setting the distance d1 to be large, it can be ensured that the exposure amount is sufficient when the anode layer is formed by the patterning process, so that no anode layer 05 remains at the position of the via hole K1, i.e., the formed anode layer 05 is only located in the display area A1. Thus, the product yield is ensured to be better.

Alternatively, as can be seen with reference to fig. 6 and 7, the non-display area B1 may have a connection area B11 and a fan-out area B12 sequentially arranged in a direction close to the display area A1. On this basis, the first flat layer 04 may be formed only at the connection region B11. And, a first metal line L1 extending along the second direction Y1 may be further formed on one side of the interlayer dielectric layer 02 far from the substrate 01 by using a patterning process. Also, the first metal line L1 may be formed at the connection region B11 and the fan-out region B12.

Wherein the second direction Y1 and the first direction X1 may intersect. For example, the first direction X1 and the second direction Y1 may be perpendicular. Also, the first direction X1 and the second direction Y1 may both be directions parallel to the carrying surface of the substrate 01.

In the embodiment of the present disclosure, as can also be seen in conjunction with fig. 7, an orthogonal projection of the first planarization layer 04 on the substrate 01 and an orthogonal projection of the first metal line L1 on the substrate 01 may be partially overlapped, and apart from the overlapped portion, a distance d1 exists between a side of the first planarization layer 04 close to the display area A1 and a side of the scribe line 03 far away from the display area A1.

For example, the first planarization layer 04 may be formed to have the cutouts C1 recessed in the direction away from the streets 03 in the second direction Y1. That is, a trenching design may be performed to improve the problem of residue of the anode layer 05. In addition, as can be seen from the above embodiments, the distance d1 may be substantially equal to the maximum width w1 of the trench C1 in the second direction Y1. Alternatively, the first planarization layer 04 may be etched to form the trench C1.

Alternatively, as can be seen with continued reference to fig. 7, the orthogonal projection of the formed trench C1 on the substrate 01 may be rectangular.

Optionally, as can be seen with continued reference to fig. 7, a patterning process may be further employed to form the lead portion 06 on the side of the interlayer dielectric layer 02 away from the substrate 01. And the formed Pin part 06 may be located only in the fan-out region B12, and the Pin part 06 may include a plurality of trace pins, i.e., pin pins, arranged at intervals along the first direction X1.

Further, in the first direction X1, a length L1 of the cutout C1 may be formed to be greater than or equal to a length L2 of the lead part 06, and the lead part 06 may be located within a range defined by extension lines of both sides of the cutout C1.

Alternatively, as can be seen with continued reference to fig. 7, the first metal line L1 may be formed to include a first power line VDD and a second power line VSS arranged at an interval along the first direction X1, where a potential of the first power signal provided by the first power line VDD is greater than a potential of the second power signal provided by the second power line VSS.

On this basis, the cutout C1 and the pin part 06 may be formed between the first power line VDD and the second power line VSS. That is, the cutout C1 may be opened between the first power line VDD and the second power line VSS and the lead part 06 may be formed.

Alternatively, as can be seen with continued reference to fig. 7 to 9, a patterning process may be further adopted to form a second metal line L2 extending along the first direction X1 on a side of the interlayer dielectric layer 02 close to the substrate 01. And, the second metal line L2 may be formed only at the connection region B11. And the orthographic projection of the formed first flat layer 04 on the substrate 01 covers the orthographic projection of the formed second metal line L2 on the substrate 01.

Alternatively, as can be seen with continued reference to fig. 7 to 9, the scribe line 03 formed may be located only at the connection region B11 and closer to the fan-out region B12 than the first planar layer 04.

Optionally, as can be seen with continued reference to fig. 11, a buffer layer 07 may be further formed between the interlayer dielectric layer 02 and the substrate 01 by using a patterning process, and the formed buffer layer 07 may be located in the display area A1 and the non-display area B1. And forming a second flat layer 08 on the side, away from the substrate 01, of the interlayer dielectric layer 02 by using a patterning process, wherein the formed second flat layer 08 is only positioned in the display area A1. And, forming a transistor T1 in the display area A1 by using a patterning process. The transistor T1 includes an active layer P1 and a gate insulating layer GI that are located between the buffer layer 07 and the interlayer dielectric layer 02 and are sequentially stacked in a direction away from the substrate 01, a gate metal layer GT that is located between the gate insulating layer GI and the interlayer dielectric layer 02, and a source drain metal layer SD that is located between the interlayer dielectric layer 02 and the second planarization layer 08.

On this basis, optionally, the formed via hole K1 may penetrate through the interlayer dielectric layer 02 and the gate insulating layer GI, and expose the buffer layer 07. That is, the scribe lane 03 may be formed by processing the interlayer dielectric layer 02 and the gate insulating layer GI to obtain the via hole K1. The second planarization layer 08 and the first planarization layer 04 may be formed on the same layer. That is, the second planarization layer 08 and the first planarization layer 04 may be formed by one patterning process using the same material. The formed first metal line L1 and the formed pin part 06 may be located on the same layer as the source-drain metal layer SD, and the second metal line L2 may be located on the same layer as the gate metal layer GT. That is, the first metal line L1, the lead part 06, and the source-drain metal layer SD included in the transistor T1 may be formed by a single patterning process using the same material. And the same material is adopted, and the second metal line L2 and the gate metal layer GT are formed through a one-time composition process.

Alternatively, in the embodiment of the present disclosure, the first flat layer 04 may be formed to have a thickness smaller than that of the second flat layer 08. Thus, a half-transmissive and half-reflective mask can be used to simultaneously form insulating layers of different thicknesses on the same layer.

In summary, the present disclosure provides a method for manufacturing a display panel. The display panel formed by the method comprises an interlayer dielectric layer, a cutting path and a first flat layer, wherein the interlayer dielectric layer is positioned on one side of a substrate. The cutting channel comprises a plurality of through holes penetrating through the interlayer dielectric layer, and the first flat layer is located on one side, far away from the substrate, of the interlayer dielectric layer. Because the first flat layer that forms inclines along the direction of keeping away from the substrate near one side of display interval, and has the interval with the one side that the display interval was kept away from to the cutting street, so can through setting up the interval size in a flexible way to when adopting the picture composition technology to form the anode layer, exposure light is along not equidirectional reflection at the one side that first flat layer inclined and the one side that the substrate was kept away from to the interlaminar dielectric layer, makes the exposure of through-hole department better, avoids remaining the anode layer in through-hole department. I.e. so that the anode layer formed at the side of the second insulation from the side remote from the substrate is only located at the display area.

Fig. 13 is a schematic structural diagram of a display device according to an embodiment of the present disclosure. As shown in fig. 13, the display device includes: such as the display panel 00 shown in the above figures. And, the display device may further include a power supply component J1, and the power supply component J1 may be connected with the display panel 00 to supply power to the display panel 00.

Optionally, the display device may be: any product or component with a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator or a transparent display product, and the like. The transparent display product can be applied to vehicle-mounted display of automobiles, subways and the like, can be applied to show window display of hotels, clothing stores and the like, and has the advantages of clear image quality, vivid display effect and the like.

It is noted that in the drawings, the sizes of layers and regions may be exaggerated for clarity of illustration. Also, it will be understood that when an element or layer is referred to as being "on" another element or layer, it can be directly on the other element or layer or intervening layers may also be present. In addition, it will be understood that when an element or layer is referred to as being "under" another element or layer, it can be directly under the other element or intervening layers or elements may also be present. In addition, it will also be understood that when a layer or element is referred to as being "between" two layers or elements, it can be the only layer between the two layers or elements, or there can be more than one intermediate layer or element. Like reference numerals refer to like elements throughout.

And, the terminology used in the description of the embodiments of the present disclosure is for the purpose of describing the embodiments of the present disclosure only and is not intended to be limiting of the present disclosure. Unless otherwise defined, technical or scientific terms used in the embodiments of the present disclosure should have the ordinary meaning as understood by those having ordinary skill in the art to which the present disclosure belongs.

As such, in the disclosed embodiments, the terms "first" and "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance. The term "plurality" means two or more unless expressly limited otherwise.

Also, the use of the terms "a" or "an" and the like do not denote a limitation of quantity, but rather denote the presence of at least one.

The word "comprising" or "comprises", and the like, means that the element or item appearing in front of the word "comprising" or "comprises" includes the element or item listed after the word "comprising" or "comprises" and its equivalents, and does not exclude other elements or items.

"upper", "lower", "left", or "right", etc. are used merely to indicate relative positional relationships, which may also change accordingly when the absolute position of the object being described changes. "connect" or "couple" refers to an electrical connection.

"and/or" means that three relationships may exist, e.g., A and/or B, may mean: a exists alone, A and B exist simultaneously, and B exists alone. The character "/" generally indicates that the former and latter associated objects are in an "or" relationship.

The above description is intended to be exemplary only and not to limit the present disclosure, and any modification, equivalent replacement, or improvement made without departing from the spirit and scope of the present disclosure is to be considered as the same as the present disclosure.

Claims

1. A display panel, comprising:

2. The display panel according to claim 1, wherein the non-display region has a connection region and a fan-out region arranged in order in a direction close to the display region; the first flat layer is located at the connection region; the display panel further includes:

the first metal wire extends along a second direction, is positioned on one side, far away from the substrate, of the interlayer dielectric layer and is positioned in the connecting area and the fan-out area, and the second direction intersects with the first direction;

3. The display panel according to claim 2, wherein in the second direction, the first flat layer has a cutout groove recessed in a direction away from the scribe line;

4. The display panel of claim 3, wherein an orthographic projection of the cutout on the substrate is rectangular, circular, elliptical, or trapezoidal.

5. The display panel according to claim 3, characterized in that the display panel further comprises:

6. The display panel according to claim 5, wherein the first metal line comprises a first power line and a second power line arranged at an interval in the first direction, and wherein a potential of a first power signal supplied from the first power line is larger than a potential of a second power signal supplied from the second power line;

7. The display panel according to any one of claims 2 to 6, characterized by further comprising:

8. The display panel according to any of claims 2 to 6, wherein the scribe line is located at the connection area and the scribe line is located near the fan-out area with respect to the first flat layer.

9. The display panel according to any one of claims 2 to 6, wherein the first direction and the second direction are both directions parallel to a display surface of the display panel, and the first direction is perpendicular to the second direction.

10. The display panel according to any one of claims 1 to 6, characterized by further comprising:

a transistor in the display region, the transistor including: the active layer and the gate insulating layer are positioned between the buffer layer and the interlayer dielectric layer and are sequentially stacked along the direction far away from the substrate, the gate metal layer is positioned between the gate insulating layer and the interlayer dielectric layer, and the source drain metal layer is positioned between the interlayer dielectric layer and the second flat layer;

and in the display panel with the first metal wire, the second metal wire and the lead part, the first metal wire and the lead part are positioned on the same layer with the source drain metal layer, and the second metal wire and the gate metal layer are positioned on the same layer.

11. The display panel according to any one of claims 1 to 6, characterized by further comprising:

12. The display panel according to claim 11, wherein the first planarization layer has a thickness smaller than that of the second planarization layer.

13. The display panel according to any of claims 1 to 6, wherein a distance between a side of the first flat layer close to the display region and a side of the scribe line far away from the display region is greater than 10 μm.

14. A method for manufacturing a display panel, the method being used for manufacturing the display panel according to any one of claims 1 to 13, the method comprising:

forming a first flat layer on one side, far away from the substrate, of the interlayer dielectric layer, wherein the first flat layer is located in the non-display area, the first flat layer is far away from the display area relative to the cutting street, and a distance exists between one side, close to the display area, of the first flat layer and one side, far away from the display area, of the cutting street, and the first flat layer inclines towards the direction far away from the cutting street along the direction far away from the substrate;

15. A display device, characterized in that the display device comprises: the display panel according to any one of claims 1 to 13.