CN115224662B

CN115224662B - Over-temperature protection circuit of functional circuit and power supply chip

Info

Publication number: CN115224662B
Application number: CN202210937351.XA
Authority: CN
Inventors: 王子威; 尚宇
Original assignee: Longxin Zhongke Nanjing Technology Co ltd
Current assignee: Longxin Zhongke Nanjing Technology Co ltd
Priority date: 2022-08-05
Filing date: 2022-08-05
Publication date: 2024-07-19
Anticipated expiration: 2042-08-05
Also published as: CN115224662A

Abstract

The embodiment of the invention provides an over-temperature protection circuit of a functional circuit and a power supply chip, and relates to the technical field of circuits. In the embodiment of the invention, when the working temperature of the functional circuit is increased to a higher temperature and is reduced to a lower temperature, the gate terminal voltage of the input pair tube of the fully differential amplifier is changed greatly, so that the temperature hysteresis circuit is arranged to output different high and low levels, thereby triggering the closing or opening of the functional circuit.

Description

Over-temperature protection circuit of functional circuit and power supply chip

Technical Field

The present invention relates to the field of circuit technologies, and in particular, to an over-temperature protection circuit for a functional circuit and a power chip.

Background

The over-temperature protection function of the circuit is to control the working state of the circuit by detecting the working temperature of the circuit. During the operation of the circuit, heat loss is inevitably generated, so that the temperature of the circuit is increased, and if the heat dissipation effect of the circuit is poor, the temperature is higher and higher until the circuit is burnt out. The over-temperature protection function is to close the circuit after the temperature of the circuit exceeds the specified temperature during the operation, so as to avoid burning out the circuit due to the over-high temperature, and restart the circuit to restart the operation after the circuit dissipates heat and cools down.

In practical application, the over-temperature protection function can detect temperature through the temperature sensitive device, but when the circuit is prepared, the over-temperature protection function needs to be integrated inside the circuit, at the moment, few selectable temperature sensitive devices are needed, and a plurality of selectable temperature sensitive devices need special process support, so that the over-temperature protection circuit applicable to the common process is less.

The temperature hysteresis range of the conventional over-temperature protection circuit is very limited, so that the protection effect of the over-temperature protection circuit is poor.

Disclosure of Invention

In view of the above problems, embodiments of the present invention are provided to provide an over-temperature protection circuit and a power chip for a functional circuit that overcome or at least partially solve the above problems, so as to solve the problem that the current over-temperature protection circuit has a limited hysteresis temperature interval, resulting in poor over-temperature protection effect.

In order to solve the problems, the embodiment of the invention discloses an over-temperature protection circuit of a functional circuit, which comprises a temperature hysteresis circuit and a hysteresis enhancement circuit, wherein the hysteresis enhancement circuit is respectively connected with at least one functional circuit;

The temperature hysteresis circuit is used for detecting and controlling the temperature of the functional circuit and comprises a triode and a fully differential amplifier; the emitter of the triode outputs emitter voltage to the fully differential amplifier; the fully differential amplifier outputs a first signal to the hysteresis enhancement circuit based on the emitter voltage, and an externally input reference voltage and an output common mode reference voltage;

The hysteresis enhancing circuit comprises a Schmitt trigger circuit, and the Schmitt trigger circuit enhances and shapes the first signal and then outputs a second signal to the functional circuit;

Wherein the emitter voltage is inversely related to the operating temperature of the functional circuit; the voltage corresponding to the first signal is positively correlated with the emitter voltage; the voltage corresponding to the second signal is inversely related to the voltage corresponding to the first signal so as to control the functional circuit to be turned off or turned on.

Optionally, the fully differential amplifier includes a main operational amplifier circuit and a common mode feedback amplifier;

The main operational amplifier circuit comprises a first PMOS transistor, a second PMOS transistor, a first resistor, a second resistor, a first NMOS transistor and a second NMOS transistor; the first NMOS transistor and the first PMOS transistor are respectively connected with the positive end of the common mode feedback amplifier through the first resistor, and the second NMOS transistor and the second PMOS transistor are respectively connected with the positive end of the common mode feedback amplifier through the second resistor so as to send an output common mode voltage to the common mode feedback amplifier;

And the common mode feedback amplifier stabilizes the output common mode voltage according to the output common mode reference voltage, and outputs the obtained stabilized voltage to the first NMOS transistor and the second NMOS transistor respectively.

Optionally, the first PMOS transistor is configured to be turned on when the operating temperature of the functional circuit increases to a maximum value of a set hysteresis temperature interval, and turned off when the operating temperature of the functional circuit decreases to a minimum value of the hysteresis temperature interval; the second PMOS transistor is configured to be opposite to an on-off state of the first PMOS transistor.

Optionally, the emitter voltage is configured to decrease when the operating temperature of the functional circuit increases, and to be lower than a specific voltage value of the input reference voltage when the operating temperature of the functional circuit increases to a maximum value of a set hysteresis temperature interval; and is configured to rise when the operating temperature of the functional circuit decreases, and to be higher than the specific voltage value when the operating temperature of the functional circuit decreases to the minimum value of the hysteresis temperature interval;

The first PMOS transistor is specifically configured to turn on when the emitter voltage is below the specific voltage value and turn off when the emitter voltage is above the specific voltage value; the second PMOS transistor is specifically configured to be turned off when the emitter voltage is lower than the specific voltage value and turned on when the emitter voltage is higher than the specific voltage value.

Optionally, the voltage value of the input reference voltage is set as an average value of the first voltage value and the second voltage value; the first voltage value is a voltage value corresponding to the common connection position of the gate end of the first PMOS transistor and the emitter of the triode when the working temperature of the functional circuit is increased to the maximum value of the hysteresis temperature interval, and the second voltage value is a voltage value corresponding to the common connection position of the drain end of the first PMOS transistor, the first end of the first resistor and the drain end of the first NMOS transistor when the working temperature of the functional circuit is reduced to the minimum value of the hysteresis temperature interval.

Optionally, the voltage value of the output common-mode reference voltage is set to be an average value of the third voltage value and the fourth voltage value; the third voltage value is a voltage value corresponding to a common connection between the first end of the first resistor and the drain end of the first NMOS transistor, or a common connection between the second end of the second resistor and the drain end of the second NMOS transistor when the operating temperature of the functional circuit is increased to the maximum value of the hysteresis temperature interval, and the fourth voltage value is a voltage value corresponding to a common connection between the first end of the first resistor and the drain end of the first NMOS transistor, or a common connection between the second end of the second resistor and the drain end of the second NMOS transistor when the operating temperature of the functional circuit is reduced to the minimum value of the hysteresis temperature interval.

Optionally, the first signal includes a first sub-signal and a second sub-signal that are mutually inverted; the first output end of the temperature hysteresis circuit is configured to output the first sub-signal, and the second output end of the temperature hysteresis circuit is configured to output the second sub-signal;

The schmitt trigger circuit comprises a first schmitt trigger and a second schmitt trigger, and the second signal comprises a third sub-signal and a fourth sub-signal which are mutually inverted; the first schmitt trigger receives the output of the first output end of the temperature hysteresis circuit, and is specifically configured to perform signal enhancement based on the first sub-signal and output the third sub-signal; the second schmitt trigger receives the output of the second output end of the temperature hysteresis circuit, and is specifically configured to perform signal enhancement based on the second sub-signal and output the fourth sub-signal;

the voltage corresponding to the first sub-signal is inversely related to the emitter voltage, and the voltage corresponding to the third sub-signal is inversely related to the voltage corresponding to the first sub-signal.

Optionally, the temperature hysteresis circuit further comprises a bias circuit for biasing the triode and the fully differential amplifier; the bias circuit comprises a third PMOS transistor, a fourth PMOS transistor and a fifth PMOS transistor;

The third PMOS transistor receives an externally input bias current proportional to temperature, and outputs the bias current to the fourth PMOS transistor connected to the transistor and the fifth PMOS transistor connected to the fully differential amplifier, respectively, so that the transistor and the fully differential amplifier stably operate.

Optionally, the over-temperature protection circuit further comprises a signal shaping circuit, and the hysteresis enhancement circuit is connected with the functional circuit through the signal shaping circuit;

the signal shaping circuit is configured to shape the second signal to obtain a shaped third signal, and output the third signal to the functional circuit, so that the functional circuit is turned off or turned on according to the third signal.

Optionally, the signal shaping circuit includes an inverter circuit and a reset set flip-flop;

The inverter circuit comprises at least one inverter, and is configured to shape the second signal for the first time to obtain a fourth signal and output the fourth signal to the reset setting trigger;

the reset setting trigger is configured to perform second shaping on the fourth signal to obtain the third signal.

Optionally, the inverter circuit includes a first inverter and a second inverter;

The fourth signal includes a fifth sub-signal and a sixth sub-signal which are inverted with respect to each other; the first inverter is configured to perform first shaping on the third sub-signal so as to shorten the rising edge time and the falling edge time of the signal, adjust the level of the signal, obtain the fifth sub-signal, and output the fifth sub-signal to the reset input end of the reset setting trigger; the second inverter is configured to perform first shaping on the fourth sub-signal to shorten the rising edge time and the falling edge time of the signal, adjust the level of the signal, obtain the sixth sub-signal, and output the sixth sub-signal to the set input end of the reset set flip-flop;

The voltage corresponding to the fifth sub-signal is inversely related to the voltage corresponding to the third sub-signal.

Optionally, the third signal includes a seventh sub-signal and an eighth sub-signal that are inverted with respect to each other; the reset setting trigger is configured to perform second shaping on the fifth sub-signal and the sixth sub-signal so as to shorten signal rising edge time and signal falling edge time, adjust the height of a signal level, output the seventh sub-signal from a non-Q end of the reset setting trigger to the functional circuit, and output the eighth sub-signal from a Q end of the reset setting trigger to the functional circuit;

wherein, the voltage corresponding to the seventh sub-signal and the voltage corresponding to the fifth sub-signal are in positive correlation.

The embodiment of the invention also discloses a power chip, which comprises a functional circuit and the over-temperature protection circuit for over-temperature protection of the functional circuit.

The embodiment of the invention has the following advantages:

In the embodiment of the invention, when the working temperature of the functional circuit is increased to a higher temperature and is reduced to a lower temperature, the gate end voltage of the input pair tube of the fully differential amplifier is changed greatly, so that the temperature hysteresis circuit where the gate end voltage is positioned outputs different high and low levels, and further the over-temperature protection circuit outputs different enabling signals of voltage, thereby triggering the closing or opening of the functional circuit. Thus, the over-temperature protection of the functional circuit is realized, and the temperature hysteresis of the over-temperature protection is realized.

Drawings

FIG. 1 is a circuit diagram of an embodiment of an over-temperature protection circuit for a functional circuit of the present invention;

FIG. 2 is a circuit diagram of a temperature hysteresis circuit of the present invention;

FIG. 3 is a circuit diagram of a common mode feedback amplifier of the present invention;

FIG. 4 is a circuit diagram of another temperature hysteresis circuit of the present invention;

FIG. 5 is a circuit diagram of another common mode feedback amplifier of the present invention;

FIG. 6 is a circuit diagram of a Schmitt trigger of the present invention;

FIG. 7 is a circuit diagram of an embodiment of an over-temperature protection circuit for another functional circuit of the present invention;

FIG. 8 is a circuit diagram of an inverter of the present invention;

FIG. 9 is a circuit diagram of a reset set flip-flop of the present invention;

FIG. 10 is a simulation result of the output of the over-temperature protection circuit of the functional circuit of the present invention;

Fig. 11 is a simulation result of the output of the over-temperature protection circuit of another functional circuit of the present invention.

Detailed Description

In order that the above-recited objects, features and advantages of the present invention will become more readily apparent, a more particular description of the invention will be rendered by reference to the appended drawings and appended detailed description.

Referring to fig. 1, a circuit diagram of an embodiment of an over-temperature protection circuit for a functional circuit according to the present invention is shown, where the over-temperature protection circuit may specifically include a temperature hysteresis circuit 10 and a hysteresis enhancement circuit 20, where the hysteresis enhancement circuit 20 is connected to at least one functional circuit 30 (only one functional circuit 30 is shown in the drawing), and the over-temperature protection circuit 10 is used for over-temperature protection of the functional circuit 30.

Referring to fig. 2, a circuit diagram of a temperature hysteresis circuit 10 according to the present invention is shown, where the temperature hysteresis circuit 10 is used for detecting and controlling a temperature of a functional circuit 30, the temperature hysteresis circuit 10 is a comparator structure comp_0, including a triode 11 and a fully differential amplifier 12, and the comparator structure comp_0 is a three-input two-output module. The emitter e of the transistor 11 is connected to the fully differential amplifier 12, the transistor 11 is configured to output an emitter voltage to the fully differential amplifier 12, and the fully differential amplifier 12 is configured to output a first signal (corresponding voltage is net_0/1) to the hysteresis enhancement circuit 20 based on the emitter voltage (=net_7) output by the transistor 11, and the input reference voltage (vi_ref) and the output common mode reference voltage (voc_ref) input from the outside of the over-temperature protection circuit. Wherein the output common-mode reference voltage (Voc _ ref) is used to achieve common-mode feedback of the fully differential amplifier 12. The input reference voltage (vi_ref) is used to characterize a temperature interval, the hysteresis enhancement circuit 20 includes a schmitt trigger circuit, which includes at least one schmitt trigger (st_0/1), and is connected to the fully differential amplifier 12, and outputs a second signal (corresponding to voltage net_2/3) to the functional circuit 30 after the schmitt trigger circuit enhances and shapes the first signal (corresponding to voltage net_0/1).

Wherein the emitter voltage (=net_7) is inversely related to the operating temperature of the functional circuit, the voltage (net_0/1) corresponding to the first signal is inversely related to the emitter voltage (=net_7), the voltage (net_2/3) corresponding to the second signal is inversely related to the voltage (net_0/1) corresponding to the first signal, and the functional circuit 30 is configured to be turned off or turned on based on the voltage (net_2/3) corresponding to the second signal related to the operating temperature.

In the embodiment of the invention, the temperature hysteresis refers to that when the working temperature of the functional circuit is raised to a temperature T1, an over-temperature protection mechanism can be triggered to close the functional circuit, and then when the functional circuit is lowered from a high temperature to a temperature T2, a recovery mechanism is triggered to restart the functional circuit. The reason that the hysteresis function is needed for the over-temperature protection is that if the hysteresis function is not needed, the function circuit is closed once the working temperature of the function circuit reaches a temperature threshold, the function circuit is restarted once the working temperature of the function circuit is lower than the temperature threshold, and after the restart, the temperature is quickly increased to the temperature threshold due to power consumption, so that the working state of a chip to which the function circuit belongs continuously oscillates, and the chip cannot work normally. Since the above-described case is true when the active load amplifier is used in the comparator configuration, the condition for generating the hysteresis function cannot be provided when the active load amplifier is used as the comparator.

In the embodiment of the present invention, the fully differential amplifier 12 includes an input pair of transistors, and the fully differential amplifier 12 can output by comparing the magnitudes of two voltages input to the gate terminals of the input pair of transistors, wherein one voltage input to the input pair of transistors is the emitter voltage of the triode 11, which is inversely related to the operating temperature of the functional circuit, and the other voltage input to the input pair of transistors is the input reference voltage (vi_ref). Since the emitter voltage of the transistor 11 is inversely related to the operating temperature of the functional circuit 30, when the operating temperature of the functional circuit 30 increases, the emitter voltage of the transistor 11 decreases, and when the temperature increases to the temperature T3, the emitter voltage of the transistor 11 is lower than a specific voltage value of the input reference voltage (vi_ref), two transistors in the input pair of transistors operate in a state in which one transistor is turned on and the other transistor is turned off, so that the first signal output by the over-temperature protection circuit based on the state can be used as an enable signal for triggering the functional circuit 30 to be turned off; when the temperature is reduced to the temperature T4, the emitter voltage of the transistor 11 is higher than another specific voltage value of the input reference voltage (vi_ref), two transistors in the input pair will work in a state that one transistor is turned off and the other transistor is turned on, and different high and low levels are output in contrast to the switching state of the two transistors in the previous period, so that the first signal output by the over-temperature protection circuit in this state can be used as an enabling signal for triggering the functional circuit 30 to turn on.

The specific voltage value corresponds to the operating temperature range of the functional circuit 30, and is related to the circuit bias condition and the process used, so that the specific voltage value is adjustable.

In addition, the schmitt trigger also has certain hysteresis characteristics, so that after the first signal with the hysteresis characteristics is input into the schmitt trigger, the schmitt trigger can enhance the hysteresis effect, thereby expanding the hysteresis temperature interval from [ T4, T3] to [ T2, T1], wherein T2 is less than T4 and less than T3 is less than T1.

The schmitt trigger may shape the first signal output from the fully differential amplifier 12. In practical applications, the rising edge and the falling edge of the output waveform of the fully differential amplifier 12 change slowly, and the high-low level misjudgment is easy to generate in the slow change process, so that the embodiment of the invention can also reshape the output waveform of the fully differential amplifier 12 into the waveform with shorter rising edge time and falling edge time through the schmitt trigger, thereby enabling the change between the high-low level to be close to abrupt change and improving the performance of the over-temperature protection circuit.

When the operating temperature of the functional circuit 30 increases to the maximum value T1 of the required hysteresis temperature interval and decreases to the minimum value T2 of the required hysteresis temperature interval, the input pair of the fully differential amplifier 12 can operate in different states, so that the over-temperature protection circuit outputs enable signals with different voltages, thereby triggering the functional circuit 30 to be turned off or turned on, and thus over-temperature protection of the functional circuit 30 can be realized based on temperature hysteresis. In addition, the temperature hysteresis is realized by the fully differential amplifier 12, the first signal is output, and the hysteresis effect of the first signal is enhanced by the schmitt trigger, so that a larger hysteresis temperature interval can be realized.

In one implementation of the main operational amplifier circuit of an embodiment of the present invention, referring to fig. 2, the fully differential amplifier 12 includes a main operational amplifier circuit and a common mode feedback amplifier A0.

The main operation circuit comprises a first PMOS transistor (positive CHANNEL METAL-Oxide-Semiconductor Field-Effect Transistor), a P-channel metal Oxide semiconductor field effect transistor (PM 3), a second PMOS transistor (PM 4), a first resistor (R0), a second resistor (R1), a first NMOS transistor (NEGATIVE CHANNEL METAL-Oxide-Semiconductor Field-Effect Transistor), an N-channel metal Oxide semiconductor field effect transistor (NM 0) and a second NMOS transistor (NM 1). The first NMOS transistor (NM 0) and the first PMOS transistor (PM 3) are respectively connected with the positive end of the common mode feedback amplifier A0 through a first resistor (R0), the second NMOS transistor (NM 1) and the second PMOS transistor (PM 4) are respectively connected with the positive end of the second resistor (R1) so as to send an output common mode voltage to the common mode feedback amplifier A0; the common mode feedback amplifier A0 stabilizes an output common mode voltage according to an output common mode reference voltage, and outputs the resulting stabilized voltage to the first NMOS transistor (NM 0) and the second NMOS transistor (NM 1), respectively.

Specifically, referring to fig. 2, the gate terminal of the first PMOS transistor (PM 3) and the emitter e of the triode 11 are connected to the first node (K1), the drain terminal of the first PMOS transistor (PM 3), the first terminal of the first resistor (R0) and the drain terminal of the first NMOS transistor (NM 0) are connected to the second node (K2), the source terminal of the first PMOS transistor (PM 3) is biased, the source terminal of the first NMOS transistor (NM 0) is grounded, and the second node (K2) is connected to the first output terminal of the temperature hysteresis circuit 10.

The gate terminal of the second PMOS transistor (PM 4) is connected to the first input terminal (in_0) of the temperature hysteresis circuit 10, the first input terminal (in_0) is used for inputting the input reference voltage (vi_ref), the drain terminal of the second PMOS transistor (PM 4), the second terminal of the second resistor (R1) and the drain terminal of the second NMOS transistor (NM 1) are all connected to the third node (K3), the source terminal of the second PMOS transistor (PM 4) is biased, the source terminal of the second NMOS transistor (NM 1) is grounded, and the third node (K3) is connected to the second output terminal of the temperature hysteresis circuit 10.

The positive terminal of the common mode feedback amplifier A0, the second terminal of the first resistor (R0) and the first terminal of the second resistor (R1) are all connected to the fourth node (K4), the negative terminal of the common mode feedback amplifier A0 is connected to the second input terminal (in_1) of the temperature hysteresis circuit 10, the second input terminal (in_1) is used for inputting and outputting the common mode reference voltage (voc_ref), and the output terminal of the common mode feedback amplifier A0, the gate terminal of the first NMOS transistor (NM 0) and the gate terminal of the second NMOS transistor (NM 1) are all connected to the fifth node (K5).

Wherein the first PMOS transistor (PM 3) is configured to: the switch is turned on when the operating temperature of the functional circuit 30 increases to the maximum value T1 of the set hysteresis temperature interval, and is turned off when the operating temperature of the functional circuit 30 decreases to the minimum value T2 of the hysteresis temperature interval.

The second PMOS transistor (PM 4) is configured to: opposite to the on-off state of the first PMOS transistor (PM 3).

The PMOS transistors PM3 to PM4 are input pair transistors of the fully differential amplifier 12, and if the absolute value of the voltage difference between the gate voltages of the two pair transistors, i.e., the net_7 voltage (emitter voltage) and the input reference voltage (vi_ref) input from in_0, is greater than a certain value, one of the PMOS transistors PM3 to PM4 is turned off, and the other is turned on, so that the fully differential amplifier 12 outputs a low level and a high level. The method comprises the following steps: when the operating temperature of the functional circuit increases to a higher temperature, the emitter voltage of the triode 11 decreases, the absolute value of the voltage difference between the emitter voltage of the triode and the input reference voltage (Vi_ref) input from IN_0 is larger than a certain value, and the two output signal levels of the fully differential amplifier 12 are inverted, so that the enabling signal of the functional circuit changes, and the functional circuit is closed; when the operating temperature of the functional circuit is reduced to a lower temperature, the emitter voltage of the triode 11 is increased, the absolute value of the voltage difference between the emitter voltage of the triode and the input reference voltage (vi_ref) input from in_0 is larger than a certain value, and the two output signal levels of the fully differential amplifier 12 are inverted again, so that the enabling signal of the functional circuit is changed, and the functional circuit is restarted.

In embodiments of the present invention, the output common mode voltage of the fully differential amplifier 12 is typically unstable, requiring a loop to be formed through the common mode feedback structure to stabilize the dc operating point. Fig. 3 shows a circuit diagram of a common mode feedback amplifier A0 according to the present invention, and referring to fig. 3, in one implementation of the main operational amplifier circuit according to an embodiment of the present invention, the common mode feedback amplifier A0 may include a tenth PMOS transistor (PM 9), an eleventh PMOS transistor (PM 10), a twelfth PMOS transistor (PM 11), a seventh NMOS transistor (NM 6), and an eighth NMOS transistor (NM 7).

The source terminal of the tenth PMOS transistor (PM 9) is connected to the power supply terminal (power supply voltage VDD), and the gate terminal of the tenth PMOS transistor (PM 9) is connected to the sixth node (K6).

The drain terminal of the tenth PMOS transistor (PM 9), the source terminal of the eleventh PMOS transistor (PM 10), and the source terminal of the twelfth PMOS transistor (PM 11) are all connected to the fourteenth node (K14).

The drain terminal of the eleventh PMOS transistor (PM 10), the gate terminal of the seventh NMOS transistor (NM 6), and the drain terminal of the seventh NMOS transistor (NM 6) are connected to the fifteenth node (K15).

The drain terminal of the twelfth PMOS transistor (PM 11), the gate terminal of the eighth NMOS transistor (NM 7), and the drain terminal of the eighth NMOS transistor (NM 7) are connected to the sixteenth node (K16).

The source terminal of the seventh NMOS transistor (NM 6) and the source terminal of the eighth NMOS transistor (NM 7) are both grounded.

In another implementation of the main operational amplifier circuit of an embodiment of the present invention, referring to fig. 4, the fully differential amplifier 12 includes a main operational amplifier circuit and a common mode feedback amplifier A0.

The main operation circuit comprises a first PMOS transistor (PM 3), a second PMOS transistor (PM 4), a first resistor (R0), a second resistor (R1), a first NMOS transistor (NM 0) and a second NMOS transistor (NM 1). The first NMOS transistor (NM 0) and the first PMOS transistor (PM 3) are respectively connected with the positive end of the common mode feedback amplifier A0 through a first resistor (R0), the second NMOS transistor (NM 1) and the second PMOS transistor (PM 4) are respectively connected with the positive end of the second resistor (R1) so as to send an output common mode voltage to the common mode feedback amplifier A0; the common mode feedback amplifier A0 stabilizes an output common mode voltage according to an output common mode reference voltage, and outputs the resulting stabilized voltage to the first NMOS transistor (NM 0) and the second NMOS transistor (NM 1), respectively.

Specifically, referring to fig. 4, the gate terminal of the first NMOS transistor (NM 0) and the emitter e of the triode 11 are connected to the first node (K1), the drain terminal of the first NMOS transistor (NM 0), the first terminal of the first resistor (R0) and the drain terminal of the first PMOS transistor (PM 2) are connected to the second node (K2), the source terminal of the first NMOS transistor (NM 0) is biased, the source terminal of the first PMOS transistor (PM 3) is connected to the power supply VDD, and the second node (K2) is connected to the first output terminal of the temperature hysteresis circuit 10.

The gate terminal of the second NMOS transistor (NM 1) is connected to the first input terminal (in_0) of the temperature hysteresis circuit 10, the first input terminal (in_0) is used for inputting the input reference voltage (vi_ref), the drain terminal of the second NMOS transistor (NM 1), the second terminal of the second resistor (R1) and the drain terminal of the second PMOS transistor (PM 4) are all connected to the third node (K3), the source terminal of the second NMOS transistor (NM 1) is biased, the source terminal of the second PMOS transistor (PM 4) is connected to the power supply VDD, and the third node (K3) is connected to the second output terminal of the temperature hysteresis circuit 10.

The positive end of the common mode feedback amplifier A0, the second end of the first resistor (R0) and the first end of the second resistor (R1) are all connected with the fourth node (K4), the negative end of the common mode feedback amplifier A0 is connected with the second input end (IN_1) of the temperature hysteresis circuit 10, the second input end (IN_1) is used for inputting and outputting a common mode reference voltage (Voc_ref), and the output end of the common mode feedback amplifier A0, the gate end of the first PMOS transistor (PM 3) and the gate end of the second PMOS transistor (PM 4) are all connected with the fifth node (K5).

Wherein the first NMOS transistor (NM 0) is configured to: the circuit is turned off when the operating temperature of the functional circuit 30 increases to the maximum value T1 of the set hysteresis temperature interval, and is turned on when the operating temperature of the functional circuit 30 decreases to the minimum value T2 of the hysteresis temperature interval.

The second NMOS transistor (NM 1) is configured to: opposite to the on-off state of the first NMOS transistor (NM 0).

When the absolute value of the voltage difference between the gate voltages of the two transistors, i.e., the net_7 voltage (emitter voltage) and the input reference voltage (vi_ref) input from in_0, is greater than a certain value, one of the NMOS transistors NM0 to NM1 is turned off, and the other is turned on, so that the fully differential amplifier 12 outputs a low level and a high level. The method comprises the following steps: when the operating temperature of the functional circuit increases to a higher temperature, the emitter voltage of the triode 11 decreases, the absolute value of the voltage difference between the emitter voltage of the triode and the input reference voltage (Vi_ref) input from IN_0 is larger than a certain value, and the two output signal levels of the fully differential amplifier 12 are inverted, so that the enabling signal of the functional circuit changes, and the functional circuit is closed; when the operating temperature of the functional circuit is reduced to a lower temperature, the emitter voltage of the triode 11 is increased, the absolute value of the voltage difference between the emitter voltage of the triode and the input reference voltage (vi_ref) input from in_0 is larger than a certain value, and the two output signal levels of the fully differential amplifier 12 are inverted again, so that the enabling signal of the functional circuit is changed, and the functional circuit is restarted.

Referring to fig. 4, the temperature hysteresis circuit 10 further includes a bias circuit 13, and the bias circuit 13 is configured to bias the transistor 11 and the fully differential amplifier 12; the bias circuit 13 includes a third PMOS transistor (PM 0), a fourth PMOS transistor (PM 1), a ninth NMOS transistor (NM 8), a tenth NMOS transistor (NM 9), and an eleventh NMOS transistor (NM 10).

The ninth NMOS transistor (NM 8) receives an externally input bias current proportional to temperature, and outputs the bias current to the fourth PMOS transistor (PM 1) connected to the transistor 11 and the eleventh NMOS transistor (NM 10) connected to the fully differential amplifier 12 after being mirrored by a tenth NMOS transistor (NM 9) and a third PMOS transistor (PM 0), respectively, so that the transistor 11 and the fully differential amplifier 12 stably operate.

Specifically, the source terminal of the third PMOS transistor (PM 0) and the source terminal of the fourth PMOS transistor (PM 1) are connected to a power supply terminal (power supply voltage is VDD), and the drain terminal of the ninth NMOS transistor (NM 8), the drain terminal of the tenth NMOS transistor (NM 9), and the source terminal of the eleventh NMOS transistor (NM 10) are connected to a ground voltage.

The gate end of the third PMOS transistor (PM 0), the drain end of the third PMOS transistor (PM 0) and the gate end of the fourth PMOS transistor (PM 1) are connected with a sixth node (K6); the third input terminal (in_2) of the temperature hysteresis circuit 10, the gate terminal of the ninth NMOS transistor (NM 8), the drain terminal of the ninth NMOS transistor (NM 8), the gate terminal of the tenth NMOS transistor (NM 9) and the gate terminal of the eleventh NMOS transistor (NM 10) are all connected to the seventeenth node (K17), and the third input terminal (in_2) of the temperature hysteresis circuit is for inputting a bias current (Iref) proportional to temperature;

The drain terminal of the fourth PMOS transistor (PM 1) is connected to the first node (K1), and the drain terminal of the eleventh NMOS transistor (NM 10), the source terminal of the first NMOS transistor (NM 0), and the source terminal of the second NMOS transistor (NM 1) are all connected to the seventh node (K7).

Wherein the node voltage of the seventeenth node (K17) is labeled net_12.

For the setting of the in_2 current value, that is, the setting of the bias current (Iref), the magnitude thereof is sufficient to satisfy the bias requirement for the transistor 11 and the fully differential amplifier 12 to operate normally.

For another implementation of the main operational amplifier circuit of an embodiment of the present invention, the output common mode voltage of the fully differential amplifier 12 is typically unstable, requiring a loop to be formed through the common mode feedback structure to stabilize the dc operating point. Referring to fig. 5, a circuit diagram of a common mode feedback amplifier A0 of the present invention is shown, and referring to fig. 5, in a specific embodiment, the common mode feedback amplifier A0 may include a tenth PMOS transistor (PM 9), an eleventh PMOS transistor (PM 10), a seventh NMOS transistor (NM 6), an eighth NMOS transistor (NM 7), and a twelfth NMOS transistor (NM 11).

The source terminal of the twelfth NMOS transistor (NM 11) is connected to the power source terminal (power source voltage is VDD), and the gate terminal of the twelfth NMOS transistor (NM 11) is connected to the seventeenth node (K17).

The source of the twelfth NMOS transistor (NM 11), the source of the seventh NMOS transistor (NM 6) and the source of the eighth NMOS transistor (NM 7) are all connected to the fourteenth node (K14).

The drain terminal of the seventh NMOS transistor (NM 6), the gate terminal of the tenth PMOS transistor (PM 9), and the drain terminal of the tenth PMOS transistor (PM 9) are connected to the fifteenth node (K15).

The drain terminal of the eighth NMOS transistor (NM 7), the gate terminal of the eleventh PMOS transistor (PM 10), and the drain terminal of the eleventh PMOS transistor (PM 10) are connected to the sixteenth node (K16).

The source of the tenth PMOS transistor (PM 9) and the source of the eleventh PMOS transistor (PM 10) are both connected to the power supply VDD.

In the embodiment of the present invention, the first resistor (R0) and the second resistor (R1) acquire the output common-mode voltage output by the fully differential amplifier 12, that is, net_8, the net_8 voltage value and the externally connected output common-mode reference voltage (voc_ref) are input as differences to the input end of the common-mode feedback amplifier A0, and the net_11 voltage value is output at the negative output end of the common-mode feedback amplifier A0 and returned to the gates of the two load NMOS tubes NM0 and NM1 of the fully differential amplifier 12, so as to complete the closed-loop feedback.

As shown IN fig. 1 and 2, since the output common-mode reference voltage in_1 is the output common-mode reference voltage (voc_ref), the output dc operating point of the fully-differential amplifier 12 is determined by the action of the common-mode feedback structure, and IN order to make the output swing of the fully-differential amplifier 12 as large as possible, the voltage average of the corresponding two output voltages net_1 and net_0 when the output common-mode voltage net_8 is T2 (or T1) is required, and the voltage average can be estimated. When the output swing of the fully differential amplifier 12 is as large as possible, the output common-mode voltage net_8 should be equal to the output common-mode reference voltage in_1, so that the voltage average value of the corresponding two output voltages net_1 and net_0 when the output common-mode reference voltage in_1 is set to T2 (or T1) can be set. IN this embodiment, when the operating temperature of the functional circuit 30 increases to T2 (e.g. 150 ℃), the voltage value (emitter voltage) of the emitter net_7 of the triode 11 is lower than the set input reference voltage in_0, and the difference between the two voltages can make PM3 on and PM4 off, at this time, net_1 is at a high level and net_0 is at a low level IN the first signal output by the hysteresis circuit 10, the high level is about the power supply voltage VDD minus the source-drain voltages of the two PMOS transistors (PM 2 and PM 3), and the low level is about the drain-source voltage of one NMOS transistor (NM 1), then the common mode reference voltage is output to take the average value of the two. For example: vdd=1.8v, under the conditions of the SMIC180RF process (which is one of the COMS processes), the high level is about 1.3V and the low level is about 0.3V, so the value of the voltage value of the output common mode reference voltage in_1 should be 0.8V, which is proved to meet the normal operation requirement of the over-temperature protection circuit.

Referring to fig. 2, the transistor 11 is a PNP type transistor (also referred to as a PNP type bipolar transistor), a voltage (net_7) (emitter voltage) of the first node (K1) is equal to an emitter voltage of the transistor 11, and the voltage (net_7) (emitter voltage) of the first node (K1) is configured to:

1. When the operating temperature of the functional circuit 30 increases, it decreases, and when the operating temperature of the functional circuit 30 increases to the maximum value T1 of the set hysteresis temperature interval, it is lower than the specific voltage value of the input reference voltage (Vi_ref), and

2. When the operating temperature of the functional circuit 30 decreases, it increases, and when the operating temperature of the functional circuit 30 decreases to the minimum value T2 of the set hysteresis temperature interval, it is higher than the specific voltage value of the input reference voltage (vi_ref).

The first PMOS transistor (PM 3) is specifically configured to:

1. when the voltage (NET_7) (emitter voltage) of the first node (K1) is lower than the specific voltage value of the input reference voltage (Vi_ref), is conducted

2. Turn off when the voltage (net_7) (emitter voltage) of the first node (K1) is higher than the input reference voltage (vi_ref) by a certain voltage value;

the second PMOS transistor (PM 4) is specifically configured to:

1. When the voltage (NET_7) (emitter voltage) of the first node (K1) is lower than the specific voltage value of the input reference voltage (Vi_ref), is turned off, and

2. The first node (K1) is turned on when the voltage (NET_7) (emitter voltage) is higher than the input reference voltage (Vi_ref) by a specific voltage value.

In the embodiment of the present invention, the voltage value of the input reference voltage (vi_ref) may be set as an average value of the first voltage value (V1) and the second voltage value (V2). The first voltage value (V1) is a voltage value corresponding to the first node (K1) when the operating temperature of the functional circuit 30 increases to the maximum value T1 of the hysteresis temperature interval, and the second voltage value (V2) is a voltage value corresponding to the first node (K1) when the operating temperature of the functional circuit 30 decreases to the minimum value T2 of the hysteresis temperature interval.

In the embodiment of the present invention, the voltage value of the output common-mode reference voltage (voc_ref) may be set to an average value of the third voltage value (V3) and the fourth voltage value (V4). The third voltage value (V3) is a voltage value corresponding to the second node (K2) or the third node (K3) when the operating temperature of the functional circuit 30 increases to the maximum value T1 of the hysteresis temperature interval, and the fourth voltage value (V4) is a voltage value corresponding to the second node (K2) or the third node (K3) when the operating temperature of the functional circuit 30 decreases to the minimum value T2 of the hysteresis temperature interval.

The current mirror composed of PMOS transistors PM0 to PM2 applies an externally input bias current (Iref) proportional to temperature to the PNP transistor 11, and the fully differential amplifier 12 composed of PMOS transistors PM3 to PM4, NMOS transistors NM0 to NM1, resistors R0 to R1, and the common mode feedback amplifier A0, so that a first node voltage (net_7) (emitter voltage) of negative temperature coefficient can be obtained, and the first node voltage (net_7) (emitter voltage) becomes smaller as the temperature increases.

In an alternative embodiment, the first signal (corresponding to voltage net_0/1) includes a first sub-signal (corresponding to voltage net_1) and a second sub-signal (corresponding to voltage net_0) that are opposite to each other, the first output terminal of the temperature hysteresis circuit 10 is configured to output the first sub-signal, and the second output terminal of the temperature hysteresis circuit 10 is configured to output the second sub-signal.

Accordingly, the schmitt trigger circuit may include a first schmitt trigger (st_1) and a second schmitt trigger (st_0), the second signal (corresponding to voltage net_2/3) including a third sub-signal (corresponding to voltage net_3) and a fourth sub-signal (corresponding to voltage net_2) which are inverted with each other, the first schmitt trigger (st_1) receiving an output of the first output terminal of the temperature hysteresis circuit 10, the first schmitt trigger (st_1) being specifically configured to: and performing signal enhancement based on the first sub-signal, and outputting a third sub-signal.

The second schmitt trigger (st_0) receives the output of the second output end of the temperature hysteresis circuit, and the second schmitt trigger (st_0) is specifically configured to: and performing signal enhancement based on the second sub-signal, and outputting a fourth sub-signal.

The voltage (net_1) corresponding to the first sub-signal is inversely related to the emitter voltage (net_7), and the voltage (net_3) corresponding to the third sub-signal is inversely related to the voltage (net_1) corresponding to the first sub-signal.

Fig. 6 shows a circuit diagram of a schmitt trigger of the present invention, and referring to fig. 6, in one embodiment, the schmitt trigger may include sixth (PM 5), seventh (PM 6) and eighth (PM 7) PMOS transistors, a third (NM 2), a fourth (NM 3) and fifth (NM 4) NMOS transistors.

The input terminal (in_3) of the schmitt trigger, the gate terminal of the sixth PMOS transistor (PM 5), the gate terminal of the seventh PMOS transistor (PM 6), the gate terminal of the third NMOS transistor (NM 2) and the gate terminal of the fourth NMOS transistor (NM 3) are all connected to the eighth node (K8).

The source end of the sixth PMOS transistor (PM 5) is connected with the power supply end (the power supply voltage is VDD), the drain end of the sixth PMOS transistor (PM 5), the source end of the seventh PMOS transistor (PM 6) and the source end of the eighth PMOS transistor (PM 7) are connected with the ninth node (K9), and the drain end of the eighth PMOS transistor (PM 7) is grounded.

The drain terminal of the seventh PMOS transistor (PM 6), the gate terminal of the eighth PMOS transistor (PM 7), the drain terminal of the third NMOS transistor (NM 2), the gate terminal of the fifth NMOS transistor (NM 4), and the output terminal (out_2) of the schmitt trigger are all connected to the tenth node (K10).

The source terminal of the third NMOS transistor (NM 2), the drain terminal of the fourth NMOS transistor (NM 3) and the source terminal of the fifth NMOS transistor (NM 4) are all connected with the eleventh node (K11), the source terminal of the fourth NMOS transistor (NM 3) is grounded, and the drain terminal of the fifth NMOS transistor (NM 4) is connected with the power supply terminal (the power supply voltage is VDD).

Based on the above circuit description, in the embodiment of the present invention, the voltage (net_7) (emitter voltage) of the first node (K1) is equal to the emitter voltage of the triode 11, and the emitter voltage of the triode 11 is used as a core device for temperature detection, and has a negative temperature coefficient, that is, decreases with the increase of temperature, so that the emitter voltage reflects the operating temperature of the circuit to be tested, and is used as one input voltage of the post-stage fully differential amplifier 12, and the emitter voltage and the other external, already set input reference voltage (vi_ref) are used as two inputs of the fully differential amplifier.

For the setting of the in_0 voltage value, that is, the setting of the input reference voltage (vi_ref), assuming that the over-temperature protection circuit needs to turn off the functional circuit when the temperature is higher than 150 ℃ (T1), and restart the functional circuit when the temperature is reduced to 130 ℃ (T2), the voltage value of the input reference voltage (vi_ref) may take the following values: the average of the net_7 voltage value at 150 ℃ and the net_7 voltage value at 130 ℃. The reason for this is that: when the operating temperature of the functional circuit reaches 150 ℃, the voltage value of net_7 corresponding to the emitter of the triode 11 is lower than the set input reference voltage (vi_ref), and the difference value of the two voltage values can enable the first PMOS transistor PM3 to be on (PM 3 operates in a linear region) and the second PMOS transistor PM4 to be off (PM 4 operates in a cut-off region) due to the conduction characteristic of the PMOS transistor, at this time, net_1 is at a high level and net_0 is at a low level, after the two output levels are output as the fully differential amplifier 12, the functional circuit can be turned off as an enabling signal through further processing of a later stage module, and thus the over-temperature protection is completed once; similarly, when the operating temperature of the functional circuit decreases to 130 ℃, the voltage value of net_7 corresponding to the emitter of the triode 11 will be higher than the set input reference voltage (vi_ref), and the difference between the two voltages can make the first PMOS transistor PM3 turn off (PM 3 operates in the off region) and the second PMOS transistor PM4 turn on (PM 4 operates in the linear region), at this time, net_1 is at a low level and net_0 is at a high level, and after the two output levels are outputted as the fully differential amplifier 12, the functional circuit can be restarted as an enable signal by further processing of the post module, that is, the functional circuit is restarted under the control of the fully differential amplifier.

It can be seen that the fully differential amplifier 12 can achieve a certain hysteresis function by switching the operating section of the input pair of tubes, in other words, it is because the operating section of the input pair of tubes is interchanged only when the voltage value of the emitter net_7 of the triode 11 representing the operating temperature of the functional circuit is higher or lower than the input reference voltage (vi_ref) by a certain section, thereby causing the high and low levels of the two output voltages net_1 and net_0 to be interchanged. Intuitively, this voltage interval reflects the temperature interval, and this temperature interval realizes the hysteresis function.

IN practical application, the in_0 voltage value is used as the input reference voltage of the fully differential amplifier and is changed along with the change of the requirement of the hysteresis temperature interval of the protected circuit, so that the adjustable hysteresis temperature interval is realized.

Referring to fig. 2, the temperature hysteresis circuit 10 further includes a bias circuit 13, and the bias circuit 13 is configured to bias the transistor 11 and the fully differential amplifier 12; the bias circuit 13 includes a third PMOS transistor (PM 0), a fourth PMOS transistor (PM 1), and a fifth PMOS transistor (PM 2).

The third PMOS transistor (PM 0) receives an externally input bias current proportional to temperature, and outputs to the fourth PMOS transistor (PM 1) connected to the transistor 11 and the fifth PMOS transistor (PM 2) connected to the fully differential amplifier 12, respectively, to make the transistor 11 and the fully differential amplifier 12 stably operate.

Specifically, the source terminal of the third PMOS transistor (PM 0), the source terminal of the fourth PMOS transistor (PM 1), and the source terminal of the fifth PMOS transistor (PM 2) are all connected to a power supply terminal (power supply voltage VDD).

The third input terminal (in_2) of the temperature hysteresis circuit 10, the gate terminal of the third PMOS transistor (PM 0), the gate terminal of the fourth PMOS transistor (PM 1) and the gate terminal of the fifth PMOS transistor (PM 2) are all connected to the sixth node (K6), and the third input terminal (in_2) of the temperature hysteresis circuit is used for inputting a bias current (Iref) proportional to temperature;

the drain terminal of the third PMOS transistor (PM 0) is connected to the third input terminal (in_2) of the temperature hysteresis circuit 10, the drain terminal of the fourth PMOS transistor (PM 1) is connected to the first node (K1), and the drain terminal of the fifth PMOS transistor (PM 2), the source terminal of the first PMOS transistor (PM 3), and the source terminal of the second PMOS transistor (PM 4) are all connected to the seventh node (K7).

Wherein the node voltage of the sixth node (K6) is labeled NET_6.

Fig. 7 shows a circuit diagram of another embodiment of the over-temperature protection circuit of the functional circuit of the present invention, and referring to fig. 7, optionally, the over-temperature protection circuit further includes a signal shaping circuit 40, and the hysteresis enhancement circuit 20 may be connected to the functional circuit 30 through the signal shaping circuit 40.

The signal shaping circuit 40 is configured to shape the second signal (corresponding to the voltage net_2/3), obtain a shaped third signal (a signal output at the out_0/1 end), and output the third signal to the functional circuit 30, so that the functional circuit 30 is turned off or turned on according to the third signal.

In an alternative embodiment, referring to fig. 7, signal shaping circuit 40 may specifically include an inverter circuit and a reset set flip-flop.

The inverter circuit comprises at least one inverter (INV_0/1) and is configured to shape the second signal (corresponding to the voltage NET_2/3) for the first time to obtain a fourth signal (corresponding to the voltage NET_4/5) and output the fourth signal to the reset setting flip-flop.

The reset setting flip-flop (SRT_0) is configured to perform second shaping on the fourth signal to obtain a third signal (a signal output by an OUT_0/1 end).

In the embodiment of the present invention, the signal shaping circuit 40 may further shorten the rising edge time and the falling edge time of the second signal, so that the rising edge and the falling edge of the input second signal become steeper, and the misjudgment probability of the high level and the low level is reduced. In addition, the signal shaping circuit 40 may also level shift the second signal, that is, adjust the low level of the second signal to be high and adjust the high level to be low, so that the enable signal output by the over-temperature protection circuit is adapted to the protected functional circuit.

In an alternative embodiment, referring to fig. 7, the inverter circuit may specifically include a first inverter (inv_1) and a second inverter (inv_0), wherein an input terminal of the first inverter (inv_1) is connected to an output terminal of the first schmitt trigger (st_1), an input terminal of the second inverter (inv_0) is connected to an output terminal of the second schmitt trigger (st_0), an output terminal of the first inverter (inv_1) is connected to a reset input terminal (R terminal) of the reset set trigger (srt_0), and an output terminal of the second inverter (inv_0) is connected to a set input terminal (S terminal) of the reset set trigger (srt_0).

The fourth signal (corresponding to voltage net_4/5) includes a fifth sub-signal (corresponding to voltage net_5) and a sixth sub-signal (corresponding to voltage net_4) that are inverted with respect to each other. Correspondingly, the first inverter (inv_1) is configured to perform first shaping on the third sub-signal (corresponding to the voltage net_3), a certain value is used to shorten the rising edge time and the falling edge time of the signal, adjust the signal level to obtain a fifth sub-signal (corresponding to the voltage net_5), and output the fifth sub-signal to the reset input (R end) of the reset setting flip-flop (srt_0).

The second inverter (inv_0) is configured to perform first shaping on the fourth sub-signal (corresponding to the voltage net_2) to shorten the rising edge time and the falling edge time of the signal, adjust the level of the signal, obtain the sixth sub-signal (corresponding to the voltage net_4), and output the sixth sub-signal to the set input terminal (S terminal) of the reset set flip-flop (srt_0).

The voltage (net_5) corresponding to the fifth sub-signal and the voltage (net_3) corresponding to the third sub-signal are in negative correlation.

Fig. 8 shows a circuit diagram of an inverter of the present invention, referring to fig. 8, in a specific embodiment, the inverter may include a ninth PMOS transistor (PM 8) and a sixth NMOS transistor (NM 5).

The gate terminal of the ninth PMOS transistor (PM 8), the gate terminal of the sixth NMOS transistor (NM 5), and the input terminal (in_4) of the inverter are all connected to the twelfth node (K12).

The source terminal of the ninth PMOS transistor (PM 8) is connected to the power supply terminal (power supply voltage VDD), and the source terminal of the sixth NMOS transistor (NM 5) is grounded.

The drain terminal of the ninth PMOS transistor (PM 8), the drain terminal of the sixth NMOS transistor (NM 5), and the output terminal (out_3) of the inverter are all connected to the thirteenth node (K13).

Further, the third signal (the signal output from the out_0/1 terminal) may include a seventh sub-signal (the signal output from the out_1 terminal) and an eighth sub-signal (the signal output from the out_0 terminal) which are inverted from each other. Accordingly, the reset set flip-flop (srt_0) is configured to perform the second shaping of the fifth sub-signal (corresponding to the voltage net_5) and the sixth sub-signal (corresponding to the voltage net_4) to shorten the signal rising edge time and the signal falling edge time, and adjust the signal level, and output the seventh sub-signal (signal output from the out_1 terminal) from the non-Q terminal (labeled QN in the drawing) of the reset set flip-flop (srt_0) to the functional circuit 30, and output the eighth sub-signal (signal output from the out_0 terminal) from the Q terminal (labeled Q in the drawing) of the reset set flip-flop to the functional circuit 30.

The voltage corresponding to the seventh sub-signal (the signal output from the out_1 terminal) and the voltage (net_5) corresponding to the fifth sub-signal are positively correlated.

In the embodiment of the present invention, the substrate of each PMOS transistor is connected to the power supply terminal (the power supply voltage is VDD), and the substrate of each NMOS transistor is grounded.

Fig. 9 shows a circuit diagram of a reset set flip-flop of the present invention, referring to fig. 9, in one embodiment, the reset set flip-flop (srt_0) includes a first NAND gate device (NAND 1) and a second NAND gate device (NAND 0).

The first input end of the first NAND gate device (NAND 1) is a reset input end (R end) of a reset setting trigger (SRT_0), the first input end of the second NAND gate device (NAND 1) is a set input end (S end) of the reset setting trigger, the output end of the first NAND gate device is a non-Q end of the reset setting trigger (SRT_0), and the output end of the second NAND gate device (NAND 1) is a Q end of the reset setting trigger (SRT_0).

A second input of the first NAND gate device (NAND 1) is connected to an output of the second NAND gate device (NAND 1), and a second input of the second NAND gate device (NAND 1) is connected to an output of the first NAND gate device (NAND 1).

In the embodiment of the invention, the inverter and the reset setting trigger in the signal shaping circuit can double-shape the second signal and double level shift, so that the enabling signal output by the over-temperature protection circuit has clear high-low level distinction, and the control of the functional circuit is more accurate.

As shown in fig. 7, in the embodiment of the present invention, the over-temperature protection circuit composed of the temperature hysteresis circuit 10, the hysteresis enhancement circuit 20 and the signal shaping circuit 40 may be a small module among all modules of the power chip, and the function of this module is to output an enable signal according to the temperature change, where the output enable signal determines whether the other modules (i.e. the functional circuit 30) in the power chip work normally, and the third signal (the signal output from the out_0/1 terminal) is used as the enable signal.

For example, in one embodiment, if the operating temperature of the functional circuit 30 is higher than 150 ℃, the output of the out_0 terminal is changed from high level to low level, and all the modules in the power chip using the output signal of the out_0 terminal as the enable signal are turned off, so that the power chip will not continue to operate at an excessive temperature; when the operating temperature of the functional circuit 30 falls back to 130 ℃ due to heat dissipation of the chip, the output of the out_0 terminal will become high again, and all the modules in the power chip taking the output signal of the out_0 terminal as the enabling signal will be turned on, so that the power chip enters the normal operating state again.

The voltage change of the OUT_1 end of the output end of the over-temperature protection circuit is opposite to the voltage change of the OUT_0 end, correspondingly, if the working temperature of the functional circuit is higher than 150 ℃, the output of the OUT_1 end is changed from low level to high level, and all modules taking the output signal of the OUT_1 end as an enabling signal in the power chip are closed, so that the power chip can not continue to work at the over-high temperature; when the working temperature of the functional circuit falls back to 130 ℃ due to heat dissipation of the chip, the output of the OUT_1 end is changed to low level again, and all modules taking the output signal of the OUT_1 end as an enabling signal in the power chip are started, so that the power chip enters a normal working state again.

IN summary, when the operating temperature of the functional circuit increases, the emitter voltage net_7 decreases, the temperature increases to T1, so that the net_7 voltage is lower than the specific voltage value of the input reference voltage (in_0 voltage), the first PMOS transistor PM3 of the fully differential amplifier IN the temperature hysteresis circuit is turned on, the second PMOS transistor PM4 is turned off, so that the net_0 IN the first signal output by the temperature hysteresis circuit is low, the net_2 IN the second signal output by the hysteresis enhancement circuit is high, the net_4 IN the fourth signal output by the inverter circuit is low, and the out_0 end IN the third signal output by the signal shaping circuit outputs low, thereby controlling the functional circuit to be turned off.

When the working temperature of the functional circuit is reduced, the voltage of the emitter voltage NET_7 is increased, the temperature is reduced to T2, the voltage of NET_7 is higher than the specific voltage value of the input reference voltage (IN_0 voltage), the first PMOS transistor PM3 of the fully differential amplifier IN the temperature hysteresis circuit is turned off, the second PMOS transistor PM4 is turned on, NET_0 IN a first signal output by the temperature hysteresis circuit is high level, NET_2 IN a second signal output by the hysteresis enhancement circuit is low level, NET_4 IN a fourth signal output by the inverter circuit is high level, and the OUT_0 end IN a third signal output by the signal shaping circuit is high level, so that the functional circuit is controlled to restart.

Fig. 10 and 11 exemplarily show the output simulation results of an over-temperature protection circuit of a functional circuit of the present invention, which can achieve a hysteresis temperature interval of 131-148.5 ℃. In fig. 10, the operating temperature of the functional circuit is increased from 120 ℃ to 160 ℃, the solid line is the output voltage of the out_0 terminal of the over-temperature protection circuit, the dotted line is the output voltage of the out_1 terminal of the over-temperature protection circuit, and as can be seen from fig. 9, the over-temperature protection circuit can turn off the functional circuit when the operating temperature of the functional circuit is increased to about 148.5 ℃; fig. 11 shows a case where the operating temperature of the functional circuit is reduced from 160 ℃ to 120 ℃, the solid line is the output voltage of the out_0 terminal of the over-temperature protection circuit, the dotted line is the output voltage of the out_1 terminal of the over-temperature protection circuit, and as can be seen from fig. 10, the functional circuit can be restarted to operate normally when the operating temperature of the functional circuit is reduced to about 131 ℃.

In the embodiment of the invention, when the working temperature of the functional circuit is increased to a higher temperature and is reduced to a lower temperature, the input pair tubes of the fully differential amplifier can work in different states, so that the over-temperature protection circuit outputs different enabling signals of voltage, and the functional circuit is triggered to be turned off or turned on, thus the over-temperature protection of the functional circuit is realized, and the temperature hysteresis of the over-temperature protection is realized. In addition, the embodiment of the invention can realize temperature hysteresis through the fully differential amplifier, and then the hysteresis effect is enhanced through the Schmitt trigger, so that a larger hysteresis temperature interval is realized, and the hysteresis temperature interval is adjustable.

The embodiment of the invention also provides a power supply chip, which comprises a functional circuit and the over-temperature protection circuit for over-temperature protection of the functional circuit.

The above description of the over-temperature protection circuit and the power supply chip of the functional circuit provided by the invention applies specific examples to illustrate the principle and the implementation of the invention, and the above description of the examples is only used for helping to understand the method and the core idea of the invention; meanwhile, as those skilled in the art will have variations in the specific embodiments and application scope in accordance with the ideas of the present invention, the present description should not be construed as limiting the present invention in view of the above.

Claims

1. The over-temperature protection circuit of the functional circuit is characterized by comprising a temperature hysteresis circuit and a hysteresis enhancement circuit, wherein the hysteresis enhancement circuit is respectively connected with at least one functional circuit;

Wherein the emitter voltage is inversely related to the operating temperature of the functional circuit; the voltage corresponding to the first signal is positively correlated with the emitter voltage; the voltage corresponding to the second signal is inversely related to the voltage corresponding to the first signal so as to control the functional circuit to be closed or opened;

The fully differential amplifier comprises a main operational amplifier circuit and a common mode feedback amplifier; the main operational amplifier circuit comprises a first PMOS transistor, a second PMOS transistor, a first resistor, a second resistor, a first NMOS transistor and a second NMOS transistor; the first NMOS transistor and the first PMOS transistor are respectively connected with the positive end of the common mode feedback amplifier through the first resistor, and the second NMOS transistor and the second PMOS transistor are respectively connected with the positive end of the common mode feedback amplifier through the second resistor so as to send an output common mode voltage to the common mode feedback amplifier.

2. The excess temperature protection circuit of a functional circuit of claim 1, wherein,

3. The over-temperature protection circuit according to claim 2, wherein the first PMOS transistor is configured to be turned on when an operation temperature of the functional circuit increases to a maximum value of a set hysteresis temperature interval, and turned off when the operation temperature of the functional circuit decreases to a minimum value of the hysteresis temperature interval; the second PMOS transistor is configured to be opposite to an on-off state of the first PMOS transistor.

4. The over-temperature protection circuit of claim 3, wherein the emitter voltage is configured to decrease when an operating temperature of the functional circuit increases, and to be lower than a specific voltage value of the input reference voltage when the operating temperature of the functional circuit increases to a maximum value of a set hysteresis temperature interval; and is configured to rise when the operating temperature of the functional circuit decreases, and to be higher than the specific voltage value when the operating temperature of the functional circuit decreases to the minimum value of the hysteresis temperature interval;

5. The over-temperature protection circuit of the functional circuit according to claim 4, wherein the voltage value of the input reference voltage is set to an average value of a first voltage value and a second voltage value; the first voltage value is a voltage value corresponding to the gate end of the first PMOS transistor when the working temperature of the functional circuit is increased to the maximum value of the hysteresis temperature interval, and the second voltage value is a voltage value corresponding to the drain end of the first PMOS transistor when the working temperature of the functional circuit is reduced to the minimum value of the hysteresis temperature interval.

6. The over-temperature protection circuit of the functional circuit according to claim 4, wherein a voltage value of the output common-mode reference voltage is set to an average value of a third voltage value and a fourth voltage value; the third voltage value is a voltage value corresponding to the drain terminal of the first NMOS transistor when the working temperature of the functional circuit is increased to the maximum value of the hysteresis temperature interval, and the fourth voltage value is a voltage value corresponding to the drain terminal of the first NMOS transistor when the working temperature of the functional circuit is decreased to the minimum value of the hysteresis temperature interval.

7. The over-temperature protection circuit of the functional circuit of claim 2, wherein the first signal comprises a first sub-signal and a second sub-signal that are inverted with respect to each other; the first output end of the temperature hysteresis circuit is configured to output the first sub-signal, and the second output end of the temperature hysteresis circuit is configured to output the second sub-signal;

8. The over-temperature protection circuit of the functional circuit of claim 2, wherein the temperature hysteresis circuit further comprises a bias circuit for biasing the transistor and the fully differential amplifier; the bias circuit comprises a third PMOS transistor, a fourth PMOS transistor and a fifth PMOS transistor;

The third PMOS transistor receives an externally input bias current and outputs the externally input bias current to the fourth PMOS transistor connected to the transistor and the fifth PMOS transistor connected to the fully differential amplifier, respectively, so that the transistor and the fully differential amplifier stably operate.

9. The over-temperature protection circuit of a functional circuit according to claim 1, further comprising a signal shaping circuit, the hysteresis enhancement circuit being connected to the functional circuit through the signal shaping circuit;

10. The over-temperature protection circuit of the functional circuit of claim 9, wherein the signal shaping circuit comprises an inverter circuit and a reset set flip-flop;

11. The over-temperature protection circuit of the functional circuit of claim 10, wherein the inverter circuit comprises a first inverter and a second inverter;

the second signal comprises a third sub-signal and a fourth sub-signal which are mutually inverted;

12. The over-temperature protection circuit of the functional circuit according to claim 11, wherein the third signal includes a seventh sub-signal and an eighth sub-signal that are inverted from each other; the reset setting trigger is configured to perform second shaping on the fifth sub-signal and the sixth sub-signal so as to shorten signal rising edge time and signal falling edge time, adjust the height of a signal level, output the seventh sub-signal from a non-Q end of the reset setting trigger to the functional circuit, and output the eighth sub-signal from a Q end of the reset setting trigger to the functional circuit;

13. A power chip comprising a functional circuit, and an over-temperature protection circuit for over-temperature protection of the functional circuit according to any one of claims 1 to 12.