CN115224110A - Semiconductor structure and manufacturing method, memory and manufacturing method, and memory system - Google Patents
Semiconductor structure and manufacturing method, memory and manufacturing method, and memory system Download PDFInfo
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- CN115224110A CN115224110A CN202210855323.3A CN202210855323A CN115224110A CN 115224110 A CN115224110 A CN 115224110A CN 202210855323 A CN202210855323 A CN 202210855323A CN 115224110 A CN115224110 A CN 115224110A
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/764—Air gaps
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/05—Making the transistor
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Abstract
The embodiment of the application provides a semiconductor structure and a manufacturing method thereof, a memory and a manufacturing method thereof, and a memory system, wherein the semiconductor structure comprises: an active pillar group in the semiconductor layer; the active column set includes: a first active pillar and a second active pillar; the first air gap isolation structure is positioned between the adjacent active column groups; a second air gap isolation structure located between adjacent first and second active pillars.
Description
Technical Field
The present application relates to the field of semiconductor technology, and relates to, but is not limited to, a semiconductor structure and a manufacturing method thereof, a memory and a manufacturing method thereof, and a memory system.
Background
Transistors in semiconductor structures are widely used as switching devices or driving devices in electronic devices. For example, the transistor may be used in a Dynamic Random Access Memory (DRAM) for controlling a capacitance in each Memory cell. The basic memory cell structure of the dynamic random access memory consists of a transistor and a storage capacitor, and the main action principle of the basic memory cell structure is that the quantity of stored charges in the capacitor is used for representing whether a binary bit (bit) is l or 0.
However, the transistors in the related art still have many problems to be improved.
Disclosure of Invention
In order to solve the related technical problems, embodiments of the present application provide a semiconductor structure and a manufacturing method thereof, a memory and a manufacturing method thereof, and a memory system.
An embodiment of the present application provides a semiconductor structure, including:
an active pillar group in the semiconductor layer; the active column set includes: a first active pillar and a second active pillar;
the first air gap isolation structure is positioned between the adjacent active column groups;
a second air gap isolation structure located between adjacent first and second active pillars.
In the above scheme, the active pillar groups are arranged in an array along a first direction and a second direction respectively; the first direction and the second direction are both vertical to the thickness direction of the semiconductor layer;
the first active pillar and the second active pillar are arranged in parallel along the first direction;
the semiconductor structure further includes:
a first gate structure located between the second air gap isolation structure and the first active pillar;
a second gate structure located between the second air gap isolation structure and the second active pillar.
In the above aspect, the dimension of the second air gap isolation structure along the first direction is greater than the dimension of the first air gap isolation structure along the first direction.
In the above scheme, the semiconductor structure further includes: insulating layers between the first gate structure and the first active pillar, between the second gate structure and the second active pillar, and between the first air gap isolation structure and the set of active pillars;
the protective layer is positioned above the active column group and the first air gap isolation structure;
and the cap layer is positioned above the second air gap isolation structure and the first gate structure and the second gate structure, and the top of the cap layer is flush with the top of the protective layer.
In the above scheme, the semiconductor structure further includes:
a support layer between the first and second active pillars and below the first and second gate structures.
In the above scheme, the first active pillar and the second active pillar both include:
a channel region;
a source located at a first end of the channel region;
a drain at a second end of the channel region; the first end and the second end are two opposite ends in the extending direction of the channel region respectively; the extending direction is parallel to the direction of the thickness of the semiconductor layer.
In the above scheme, an included angle between the first direction and the second direction ranges from 0 to 90 degrees.
An embodiment of the present application provides a memory, including: the semiconductor structure described in the above embodiment;
the memory cell is connected with one of a source electrode and a drain electrode of an active column in the semiconductor structure; and
a bit line connected to a remaining one of the source and the drain of each active pillar in a row of active pillars in the semiconductor structure.
An embodiment of the present application provides a storage system, including: a memory as described in the above embodiments; and the number of the first and second groups,
a memory controller connected with the memory and used for controlling the memory.
The embodiment of the application provides a manufacturing method of a semiconductor structure, which comprises the following steps:
providing a semiconductor layer;
forming a first groove and a second groove;
forming a third groove; the second trench and the third trench divide the semiconductor layer into an active pillar group; the active pillar set includes a first active pillar and a second active pillar separated by the first trench; forming a protective layer on the second trench to form a first air gap isolation structure in the second trench;
forming a first gate structure covering one side of the first active column and a second gate structure covering one side of the second active column on the side wall of the first groove, and forming a fourth groove between the first gate structure and the second gate structure;
and forming a cap layer on the fourth trench to form a second air gap isolation structure in the fourth trench.
In the above solution, the first trenches and the second trenches penetrate through the semiconductor layer and are alternately arranged along a first direction; the third grooves penetrate through the semiconductor layer and are arranged along a second direction;
the active column groups are respectively arranged in an array along a first direction and a second direction; the first direction and the second direction are both vertical to the thickness direction of the semiconductor layer;
the first active pillar and the second active pillar are juxtaposed along the first direction.
In the above scheme, after the first trench and the second trench are formed, an insulating layer is formed on a sidewall of each of the first trench and the second trench;
the forming a protective layer on the second trench includes:
forming a protective layer in contact with the insulating layer on the top of the second trench in which the insulating layer is formed;
the method further comprises the following steps:
and when forming the protective layer on the second groove, forming the protective layer covering the insulating layer in the first groove formed with the insulating layer.
In the above scheme, the method further comprises:
before forming a first gate structure covering one side of the first active column and a second gate structure covering one side of the second active column, filling an insulating material in a first trench in which a protective layer is formed, and removing a part of the protective layer, a part of the insulating layer and a part of the insulating material in the first trench to form a support layer at the bottom of the first trench.
In the above aspect, the providing a semiconductor layer includes:
providing a substrate; the substrate comprises silicon-on-insulator, wherein the silicon-on-insulator comprises bottom silicon, middle silicon oxide positioned on the bottom silicon, and top silicon positioned on the middle silicon oxide; the top layer silicon is the semiconductor layer;
the first trench and the second trench penetrate the top layer silicon.
In the above scheme, the first gate structure includes a first gate oxide layer and a first gate; the second grid structure comprises a second grid oxide layer and a second grid;
the forming a first gate structure covering one side of the first active pillar and a second gate structure covering one side of the second active pillar on the sidewall of the first trench includes:
forming a first grid electrode oxidation layer on one side of the first active column; forming a first gate overlying the first gate oxide layer; and
forming a second grid electrode oxidation layer on one side of the second active column; and forming a second grid electrode covering the second grid electrode oxidation layer.
The embodiment of the application provides a manufacturing method of a memory, which comprises the following steps:
forming a semiconductor structure; the semiconductor structure is manufactured by the manufacturing method of the semiconductor structure provided in the above embodiment;
forming a memory cell, wherein the memory cell is connected with one of a source electrode and a drain electrode of an active column in the semiconductor structure;
forming a bit line connected to a remaining one of the source and the drain of the one active pillar in the semiconductor structure.
The embodiment of the application provides a semiconductor structure and a manufacturing method thereof, a memory and a manufacturing method thereof, and a memory system, wherein the semiconductor structure comprises: an active pillar group in the semiconductor layer; the active column set includes: a first active pillar and a second active pillar; the first air gap isolation structure is positioned between the adjacent active column groups; a second air gap isolation structure located between adjacent first and second active pillars. In the embodiments of the present application, a first air gap isolation structure is disposed between the active pillar groups, and a second air gap isolation structure is disposed between the first active pillar and the second active pillar in the active pillar groups, so that the adjacent active pillar groups in the semiconductor structure, and the first active pillar and the second active pillar in the active pillar groups can be separated by the air gap isolation structures, and thus, the coupling capacitance between the transistors formed by the active pillars and between the transistor groups formed by the active pillar groups can be reduced, and further, the performance of the semiconductor structure can be improved.
Drawings
Fig. 1 is a schematic diagram of a control circuit adopting an architecture of 1T1C provided in an embodiment of the present application;
fig. 2 is a schematic flow chart illustrating an implementation of a method for manufacturing a semiconductor structure according to an embodiment of the present disclosure;
fig. 3a to 3j are schematic cross-sectional views illustrating a manufacturing process of a semiconductor structure according to an embodiment of the present disclosure.
Description of reference numerals:
300-a substrate; 301-bottom silicon; 302-intermediate layer silicon oxide; 303-top layer silicon (semiconductor layer); 304-a first trench; 305-a second trench; 306-a third trench; 307-active column set; 3071-first active pillars; 3072-a second active pillar; 308-an insulating layer; 309-a protective layer; 310-a first air gap isolation structure; 311-an insulating material; 312-a support layer; 313-a gate structure; 3131-a first gate structure; 3132-a second gate structure; 314-a fourth trench; 315-cap layer; 316-second air gap isolation structure.
In the drawings described above (which are not necessarily drawn to scale), like reference numerals may describe similar components in different views. Like reference numerals having different letter suffixes may represent different examples of similar components. The drawings illustrate generally, by way of example, but not by way of limitation, various embodiments discussed herein.
Detailed Description
Exemplary embodiments disclosed in the present application will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present application are shown in the drawings, it should be understood that the present application may be embodied in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present application. It will be apparent, however, to one skilled in the art, that the present application may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the present application; that is, not all features of an actual embodiment are described herein, and well-known functions and structures are not described in detail.
In the drawings, the size of layers, regions, elements, and relative sizes may be exaggerated for clarity. Like reference numerals refer to like elements throughout.
It should be understood that spatial relationship terms such as "under" \8230; under "", "' under 8230; \8230; under" \8230;, "' over 8230; over" "," "over", etc., may be used herein for ease of description to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "at 8230; \8230; below" and "at 8230; \8230; below" may include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
So that the manner in which the features and elements of the present embodiments can be understood in detail, a more particular description of the embodiments, briefly summarized above, may be had by reference to embodiments, some of which are illustrated in the appended drawings.
Embodiments of the present invention relate to semiconductor structures that are to be used in subsequent processes to form at least a portion of a final device structure. Here, the final device may include a memory, including but not limited to a dynamic random access memory, which is described below as an example only. It should be noted that the following description of the embodiment of the dynamic random access memory is only used to illustrate the present application and is not intended to limit the scope of the present application.
It can be understood that a dram is composed of a plurality of memory cell structures, each of which is mainly composed of a Transistor and a memory cell (Capacitor) controlled by the Transistor, that is, the dram includes a structure of 1 Transistor (T) and 1 Capacitor (C) (1T 1C); the main action principle is to use how much charge is stored in the capacitor to represent whether a binary bit is l or 0.
Fig. 1 is a schematic diagram of a control circuit adopting an architecture of 1T1C provided in an embodiment of the present application; as shown in fig. 1, a drain of the transistor T is electrically connected to a Bit Line (BL), a source region of the transistor T is electrically connected to one of the electrode plates of the capacitor C, the other electrode plate of the capacitor C may be connected to a reference voltage, which may be a ground voltage or another voltage, and a gate of the transistor T is connected to a Word Line (WL); the transistor T is controlled to be turned on or off by applying a voltage to the word line WL, and the bit line BL is used to perform a read or write operation on the transistor T when the transistor T is turned on.
However, as miniaturization of the memory device progresses, the pitch between the plurality of transistors formed in the semiconductor layer gradually decreases, so that the coupling capacitance between two adjacent transistors gradually increases, thereby affecting the performance of the memory device.
In view of the above, in order to solve one or more of the above problems, embodiments of the present application provide a semiconductor structure and a manufacturing method thereof, a memory and a manufacturing method thereof, so as to reduce a coupling capacitance between two adjacent transistors, thereby improving the performance of the memory. Fig. 2 is a schematic flow chart illustrating an implementation of a method for manufacturing a semiconductor structure according to an embodiment of the present disclosure. As shown in fig. 2, the method for manufacturing the semiconductor structure includes the following steps:
step S201, providing a semiconductor layer;
step S202, forming a first groove and a second groove;
step S203, forming a third groove; the second trench and the third trench divide the semiconductor layer into active pillar groups; the active pillar set includes a first active pillar and a second active pillar separated by the first trench;
step S204, forming a protective layer on the second trench to form a first air gap isolation structure in the second trench;
step S205, forming a first gate structure covering one side of the first active pillar and a second gate structure covering one side of the second active pillar on a sidewall of the first trench, and forming a fourth trench between the first gate structure and the second gate structure;
step S206, forming a cap layer on the fourth trench to form a second air gap isolation structure in the fourth trench.
It should be understood that the steps shown in FIG. 2 are not exclusive, and other steps may be performed before, after, or between any of the steps in the operations shown; the steps shown in fig. 2 may be sequentially adjusted according to actual needs. Fig. 3a to fig. 3j are schematic cross-sectional views illustrating a manufacturing process of a semiconductor structure according to an embodiment of the present disclosure. The method for fabricating the semiconductor structure according to the embodiment of the present application will be described in detail with reference to fig. 2 and 3a to 3 j.
It should be noted that, in the embodiment of the present application, the first direction intersects with the second direction, that is, an included angle between the first direction and the second direction ranges from 0 to 90 degrees. In some embodiments, the first direction may be perpendicular to the second direction. It is understood that the included angle between the first direction and the second direction establishes the position relationship of the plurality of active pillars arranged along the array of the first direction and the second direction.
Here and hereinafter, for convenience of description, the first direction and the second direction in the embodiment of the present application are expressed as two orthogonal directions parallel to the surface of the substrate; wherein the substrate surface may be understood as a plane perpendicular to the extension direction of the active pillars. For example, the first direction may be represented as an X direction in the drawing; the second direction may be represented as the Y direction in the drawing; the extending direction of the active pillars may be represented as a Z direction in the drawing. It is understood that in other embodiments, the first direction may be represented as the Y direction in the drawings; the second direction may be represented as the X direction in the drawing.
Executing step S201 and step S202, referring to fig. 3a, fig. 3b, and fig. 3c, fig. 3a is a cross-sectional view of the XOZ plane, fig. 3b is a top view of the XOY plane, and fig. 3c is a top view of the XOY plane; fig. 3b isbase:Sub>A top view of fig. 3base:Sub>A taken alongbase:Sub>A-base:Sub>A section, and fig. 3c is an enlarged view corresponding tobase:Sub>A dashed frame shown in fig. 3 b.
In some embodiments, the providing a semiconductor layer comprises: providing a substrate 300; the substrate 300 comprises a Silicon-on-Insulator (SOI) comprising a bottom layer of Silicon 301, an intermediate layer of Silicon oxide 302 on the bottom layer of Silicon, and a top layer of Silicon 303 on the intermediate layer of Silicon oxide 302; the top silicon 303 is the semiconductor layer.
In some embodiments, the substrate may also be Germanium-on-Insulator (GOI).
Next, referring to fig. 3a, 3b, and 3c, first trenches 304 and second trenches 305 are formed, wherein the first trenches 304 and the second trenches 305 penetrate through the semiconductor layer 303 (i.e., the top layer silicon), and the first trenches 304 and the second trenches 305 are alternately arranged along the first direction. Here, the first trench 304 and the second trench 305 extend to the surface of the intermediate layer silicon oxide 302; in other words, the intermediate layer of silicon oxide 302 may act as an etch stop for the first trench 304 and the second trench 305.
In other embodiments, the width of the first trench 304 along the first direction may be greater than or equal to the width of the second trench 305 along the first direction; preferably, the width of the first groove 304 along the first direction is larger than the width of the second groove 305 along the first direction.
In some embodiments, the first trench 304 and the second trench 305 are formed by a photolithography process (here and below may be understood as photolithography-Etch (LE)) and a Self-Aligned Double patterning (SADP) process. Here, the self-aligned double patterning process includes depositing a sacrificial material (Sacrifice Layer) on the surface of the semiconductor Layer, performing photolithography and etching, transferring the pattern on the mask onto the sacrificial material Layer, and depositing a thin film with a relatively uniform thickness as an isolation structure on the surface and the side of the sacrificial material Layer by using Atomic Layer Deposition (ALD). And then the isolation structure is removed by back etching, and due to the geometric effect of the side wall of the sacrificial material layer, the materials deposited on the two sides of the sacrificial material layer pattern can be remained to form the isolation structure. The sacrificial material layer is removed using a highly selective etchant, leaving only the isolation structures on the substrate surface. The period of the isolation structure pattern is half of that of the photoetching pattern, and the multiplication of space pattern density is realized. Finally, the isolation structure pattern is transferred to a hard mask in the substrate by plasma etching, so that the preset pattern of the active column can be transferred to the surface of the semiconductor layer.
Referring to fig. 3b, step S203 is performed to form a third trench 306. The third trenches 306 are arranged along the second direction, and each third trench 306 penetrates through the semiconductor layer 303 and extends along the first direction.
In some embodiments, after forming the first trench 304 and the second trench 305, the method further comprises: an insulating material, such as silicon oxide, is filled in the first trench 304 and the second trench 305. The third trench 306 is then formed and the remaining insulating material in the first trench 304 and the second trench 305 is removed after the third trench 306 is formed.
In some embodiments, the method of forming the third trench 306 may include: a mask layer is formed on the surface of the semiconductor layer 303, and is developed and exposed to form a predetermined pattern of the third trench 306, and then the third trench 306 is formed through an etching process.
It should be noted that step S202 and step S203 do not have a definite sequence of execution, and the first trench and the second trench may be filled after the first trench and the second trench are formed, and then a third trench is formed in the semiconductor layer; or forming a third groove first, filling the third groove, and then forming a first groove and a second groove in the semiconductor layer; a net-shaped mask layer can be formed, and the first groove, the second groove and the third groove are formed at one time. In other words, the formation order of the first trench, the second trench, and the third trench may be selectively set according to the actual situation.
Here, the second trench 305 and the third trench 306 divide the semiconductor layer into a plurality of active pillar groups 307 arranged in an array along the first direction and the second direction; the first direction and the second direction are both perpendicular to the thickness direction of the semiconductor layer. Referring to fig. 3b and 3c, each of the active pillar groups 307 includes a first active pillar 3071 and a second active pillar 3072, the first active pillar 3071 and the second active pillar 3072 are juxtaposed along a first direction, and the first active pillar 3071 and the second active pillar 3072 are isolated by a first trench 304; in other words, the first trench 304 is located between the first active pillar 3071 and the second active pillar 3072; the second trench 305 is located between two adjacent active pillar groups 307.
Here, the method for forming the first trench 304, the second trench 305, and the third trench 306 includes, but is not limited to, a plasma dry etching process.
Referring to fig. 3d, 3e, in some embodiments, the method further comprises: after the third trench 306 is formed, an insulating layer 308 is formed on the sidewall of each of the first trench 304 and the second trench 305. The insulating layer 308 may be used to couple dangling bonds (e.g., dangling bonds of silicon) of the sidewalls of the first trench 304 and the second trench 305.
In some embodiments, the material of the insulating layer 308 includes, but is not limited to, silicon oxide; methods of forming the insulating layer 308 include, but are not limited to, physical Vapor Deposition (PVD) processes, chemical Vapor Deposition (CVD) processes, ALD, and the like.
Here, fig. 3d is a cross-sectional view of the XOZ plane, fig. 3e is a top view of the XOY plane, wherein fig. 3e is a top view of fig. 3d along the B-B cross-section.
Referring to fig. 3d and 3e, step S204 is performed to form a protection layer 309 on the second trench 305.
In some embodiments, the forming a protection layer on the second trench 305 includes:
forming a protective layer 309 in contact with the insulating layer 308 on top of the second trench 305 in which the insulating layer 308 is formed; and forming a protective layer 309 on the surface of the active pillar group; wherein the surface of the protective layer on top of the second trench 305 is substantially flush with the surface of the protective layer on the surface of the active pillar group, in other words, the height of the surface of the protective layer 309 in the Z-axis direction is greater than the height of the surface of the active pillar group in the Z-axis direction.
The method further comprises the following steps:
when forming the protective layer 309 on the second trench 305, the protective layer 309 covering the insulating layer 308 is formed in the first trench 304 in which the insulating layer 308 is formed.
Referring to fig. 3d, the protection layer 309 is in contact with the insulating layer 308 at the sidewall of the second trench 305 to form a first air gap isolation structure 310 in the second trench 305. Wherein the protection layer 309 is located above the active pillars (first and second active pillars) and the first air gap isolation structure 310. It should be noted that each active pillar is used to form a corresponding transistor, and the active pillar group forms a corresponding transistor group in a subsequent process, where the first air gap isolation structure 310 may be used to reduce the coupling capacitance between two adjacent transistor groups.
Note that in some embodiments, the second trench is filled with a solid isolation structure (e.g., silicon oxide) so that two adjacent active pillars for forming a transistor are separated; in the embodiment, an air gap isolation structure is adopted to separate two adjacent active columns for forming the transistor; here, the air gap isolation structure may include a gas such as nitrogen, air, or the like. Preferably, the air gap isolation structure comprises air; it will be appreciated that air is a good dielectric with a significantly smaller relative permittivity (about 1), and that the coupling capacitance generated between two transistors separated by an air gap isolation structure is smaller; the relative dielectric constant of the solid isolation structure is relatively large (such as silicon oxide, which has a relative dielectric constant of about 4), and the coupling capacitance between two transistors separated by the solid isolation structure is large; therefore, in the present embodiment, the use of the air gap isolation structure can reduce the coupling capacitance between two adjacent transistor groups compared with the solid isolation structure.
Note that the height of the insulating layer 308 in the Z-axis direction may be higher than the surface of the active pillar, see fig. 3d; the formation process may include first forming a first protection layer on the surface of the active pillar, then forming an insulating layer 308 on the sidewall and the bottom of the second trench 305 of the active pillar, where the surface of the insulating layer 308 is substantially flush with the surface of the first protection layer, and finally forming a second protection layer on the insulating layer 308 and the surface of the first protection layer, where the protection layer 309 includes the first protection layer and the second protection layer.
It should be noted that, in the process of forming the protection layer 309, since the diameter width of the second trench 305 along the first direction is smaller, the protection layer 309 is formed only at the opening of the second trench, so that the first air gap isolation structure 310 is formed in the second trench 305; here, the protection layer 309 located at the opening of the second trench 305 may be used to protect the first air gap isolation structure 310 from being etched or filled in a subsequent etching process.
The material of the protection layer 309 includes but is not limited to silicon nitride; methods of forming the protective layer 309 include, but are not limited to, PVD processes, CVD processes, ALD processes, or the like.
Here, since the first trench 304 has a large dimension in the first direction, the protective layer 309 is also located on the sidewalls and the bottom surface of the first trench 304 where the insulating layer 308 is formed.
Next, referring to fig. 3f and 3g, the first trench 304 with the protection layer 309 formed therein is filled with an insulating material 311, and a portion of the protection layer 309, a portion of the insulating layer 308 and a portion of the insulating material 311 in the first trench 304 are removed to form a support layer 312 at the bottom of the first trench 304.
The constituent material of the insulating material 311 includes, but is not limited to, silicon oxide; methods of forming the insulating material 311 include, but are not limited to, PVD processes, CVD processes, and the like; the removal process includes, but is not limited to, an etching process; the support layer 312 may be used for supporting and also making the gate structure formed in the first trench shorter in the subsequent process, so as to further reduce the parasitic capacitance; referring to fig. 3f, the support layer 312 is the corresponding structure shown in the dashed box in fig. 3 f.
Here, fig. 3f is a cross-sectional view of the XOZ plane, fig. 3g is a top view of the XOY plane, wherein fig. 3g is a top view of fig. 3f along the C-C section.
It should be noted that, in the process of removing a portion of the protection layer 309, a portion of the insulation layer 308, and a portion of the insulation material 311 located in the first trench 304, a portion of the protection layer 309 located on top of the active pillar group and the second trench is also removed; wherein the protection layer 309 located on top of the second trench is used to protect the first air gap isolation structure 310 from being damaged.
Referring to fig. 3h, fig. 3i, and fig. 3j, step S205 is performed to form a gate structure 313; wherein the gate structure 313 includes a first gate structure 3131 and a second gate structure 3132, where the first gate structure 3131 covers a side of the first active pillar 3071; the second gate structure 3132 covers a side of the second active pillar 3072.
Here, the method of forming the gate structure 313 includes: a first gate structure 3131 covering a side of the first active pillar 3071 and a second gate structure 3132 covering a side of the second active pillar 3072 are formed at sidewalls of each of the first trenches 304. Here, the first gate structure and the second gate structure in each of the active pillar groups are confined in the same trench (first trench).
Methods of forming the first and second gate structures 3131, 3132 include, but are not limited to, PVD, CVD, or ALD processes.
Here, fig. 3h is a cross-sectional view of the XOZ plane, fig. 3i is a top view of the XOY plane, and fig. 3j is a top view of the XOY plane, where fig. 3i is a top view of fig. 3h taken along the D-D cross-section, and fig. 3j is an enlarged view corresponding to the dashed-line frame shown in fig. 3 i.
In some embodiments, the first gate structure 3131 comprises a first gate oxide layer and a first gate; the second gate structure 3132 comprises a second gate oxide layer and a second gate;
the forming a first gate structure covering one side of the first active pillar and a second gate structure covering one side of the second active pillar on the sidewall of the first trench includes:
forming a first grid electrode oxidation layer on one side of the first active column; forming a first grid electrode covering the first grid electrode oxide layer; and
forming a second gate oxide layer on one side of the second active pillar; and forming a second grid electrode covering the second grid electrode oxidation layer.
In other words, the first gate oxide layer (not shown in fig. 3 h) is located between the insulating layer 308 of the first active pillar sidewall and the first gate; the second gate oxide layer (not shown in fig. 3 h) is located between the insulating layer 308 of the second active pillar sidewall and the second gate.
It should be noted that the gate oxide layer in the transistor may be used to induce different electric fields and apply them on the surface of the channel region, so that the minority carriers in the first semiconductor layer are adsorbed to the surface of the channel region to accumulate and invert, so that the gate oxide layer becomes the same as the doping type of the source and drain, thereby achieving conduction between the source and drain.
In other embodiments, when the insulating layer 308 is formed on the sidewall of the first trench 304, the first gate structure includes a first gate; the second gate structure includes a second gate. Meanwhile, the insulating layer 308 between the first gate structure and the first active pillar may be used as a first gate oxide layer corresponding to the first gate; the insulating layer 308 between the second gate structure and the second active pillar may serve as a second gate oxide layer corresponding to the second gate.
Here, the material of the first gate and the second gate may include metal (e.g., tungsten) or polysilicon (Poly); the material of the first gate oxide layer and the second gate oxide layer may include silicon oxide.
In some embodiments, the method further comprises: forming a channel region, a source at a first end of the channel region, and a drain at a second end of the channel region in the first active pillar to form a first transistor; forming a channel region, a source at a first end of the channel region, and a drain at a second end of the channel region in the second active pillar to form a second transistor; the first transistor and the second transistor form a transistor group; wherein the first end and the second end are two opposite ends in the extending direction of the channel region respectively; the extending direction is parallel to the direction of the thickness of the semiconductor layer.
Here, a fourth trench 314 is formed between the first gate structure 3131 and the second gate structure 3132.
Next, referring to fig. 3h, 3i, and 3j, step S206 is performed to form a cap layer 315 on the fourth trench 314 to form a second air-gap isolation structure 316 in the fourth trench 314.
Here, the capping layer 315 is located over the second air gap isolation structure 316 and the first and second gate structures 3131 and 3132, and the capping layer 315 is in contact with the insulating layer 308 located at the sidewalls of the first trench 304, such that the capping layer 315, the first gate structure 3131, the support layer 312, and the second gate structure 3132 form a closed second air gap isolation structure 316; in some embodiments, the top of the cap layer 315 is substantially flush with the top of the protective layer 309.
Here, the second air gap isolation structure 316 may be used to reduce the coupling capacitance between the adjacent first and second transistors, thereby improving the performance of the memory.
In some embodiments, the cap layer is made of a material including, but not limited to, silicon oxide; methods of forming the cap layer include, but are not limited to, PVD processes, CVD processes, ALD processes, or the like.
It should be noted that the dimensions of the structures in fig. 3a to 3j are only for illustration and do not represent actual dimensions, in practical applications, the radial width of the second trench and the fourth trench along the first direction is very narrow, and the protection layer 309 may be formed above the second trench, so that the first air gap isolation structure 310 can be formed in the second trench; the cap layer 315 may be formed over the opening of the fourth trench, enabling a second air gap isolation structure 316 to be formed in the fourth trench.
In each embodiment of the application, a first air gap isolation structure is arranged between the active column groups, and a second air gap isolation structure is arranged between the first active column and the second active column in each active column group, so that the active column groups in the semiconductor structure and the first active column and the second active column in each active column group can be separated through the air gap isolation structures, and therefore coupling capacitance between transistors formed by the active columns and coupling capacitance between the transistor groups formed by the active column groups can be reduced, and performance of the semiconductor structure is improved.
The present application further provides a semiconductor structure manufactured by the method for manufacturing a semiconductor structure described in the above embodiments, the semiconductor structure including:
an active pillar group in the semiconductor layer; the active column set includes: a first active pillar and a second active pillar;
the first air gap isolation structure is positioned between the adjacent active column groups;
a second air gap isolation structure located between adjacent first and second active pillars.
In some embodiments, the active pillar groups are arranged in an array along a first direction and a second direction, respectively; the first direction and the second direction are both vertical to the thickness direction of the semiconductor layer;
the first active pillar and the second active pillar are arranged in parallel along the first direction;
the semiconductor structure further includes:
a first gate structure located between the second air gap isolation structure and the first active pillar;
a second gate structure located between the second air-gap isolation structure and the second active pillar.
In some embodiments, a dimension of the second air gap isolation structure in the first direction is greater than a dimension of the first air gap isolation structure in the first direction.
In some embodiments, the semiconductor structure further comprises: insulating layers between the first gate structure and the first active pillar, between the second gate structure and the second active pillar, and between the first air gap isolation structure and the set of active pillars;
a protective layer over the active pillar and the first air gap isolation structure;
and the cap layer is positioned above the second air gap isolation structure and the first gate structure and the second gate structure, and the top of the cap layer is flush with the top of the protective layer.
In some embodiments, the semiconductor structure further comprises:
a support layer between the first and second active pillars and below the first and second gate structures.
In some embodiments, the first active pillar and the second active pillar each include:
a channel region;
a source electrode positioned at a first end of the channel region;
a drain electrode positioned at a second end of the channel region; the first end and the second end are two opposite ends in the extending direction of the channel region respectively; the extending direction is parallel to the direction of the thickness of the semiconductor layer.
In some embodiments, the angle between the first direction and the second direction ranges from 0 to 90 degrees.
The present application further provides a memory comprising:
the semiconductor structure described in the above embodiments;
the memory cell is connected with one of a source electrode and a drain electrode of an active column in the semiconductor structure; and
a bit line connected to a remaining one of the source and the drain of each active pillar in a row of active pillars in the semiconductor structure.
In some embodiments, the memory provided by the embodiments of the present application includes various types of memory. For example, a dynamic Random Access Memory (dram), a Ferroelectric Random Access Memory (FRAM), a Magnetic Random Access Memory (MRAM), or a Resistive Random Access Memory (RRAM).
In some embodiments, the memory unit includes: a capacitor; the capacitor includes a second electrode, a dielectric covering sidewalls and a bottom of the second electrode, and a first electrode covering the dielectric. In practical applications, the second electrode may be connected to a source of a transistor in the transistor array, the first electrode is connected to a reference voltage, and the reference voltage may be a ground voltage or may include other voltages. The capacitor is used for storing written data.
In some embodiments, the memory includes a resistive random access memory, and the memory cell includes an adjustable resistor connected between the bit line and a source of a transistor in the semiconductor structure; alternatively, the adjustable resistor is connected between the bit line and a drain of a transistor in the semiconductor structure, and the adjustable resistor is used for adjusting the state of the stored data through a bit line voltage provided by the bit line.
It should be noted that, some common memories are listed here by way of example only, the scope of protection of the present application is not limited thereto, and any memory including transistors provided in the embodiments of the present application falls within the scope of protection of the present application.
An embodiment of the present application provides a storage system, including: a memory as described in the above embodiments; and the number of the first and second groups,
a memory controller connected with the memory and used for controlling the memory.
The embodiment of the application provides a manufacturing method of a memory, which comprises the following steps:
forming a semiconductor structure; the semiconductor structure is manufactured by the manufacturing method of the semiconductor structure provided in the above embodiments;
forming a memory cell, wherein the memory cell is connected with one of a source electrode and a drain electrode of an active column in the semiconductor structure;
forming a bit line connected to a remaining one of the source and the drain of a row of active pillars in the semiconductor structure.
In practical applications, the word line is connected to the gate of each of the semiconductor structures, and the word line is used for providing a word line voltage and controlling the channel region in each of the transistors to be turned on or off through the word line voltage. The bit lines extending along the first direction are connected with the drain of each semiconductor structure, and the bit lines are used for performing reading or writing operation on the memory cells when each transistor is turned on.
The memory manufactured by the method for manufacturing a memory provided by the embodiment of the present application is similar to the memory in the above embodiment, and for technical features not disclosed in the embodiment of the present application, please refer to the above embodiment for understanding, and details are not described herein again.
It should be appreciated that reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure or characteristic described in connection with the embodiment is included in at least one embodiment of the present application. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. It should be understood that, in the various embodiments of the present application, the sequence numbers of the above-mentioned processes do not mean the execution sequence, and the execution sequence of each process should be determined by its function and inherent logic, and should not constitute any limitation to the implementation process of the embodiments of the present application. The above-mentioned serial numbers of the embodiments of the present application are merely for description and do not represent the merits of the embodiments.
The methods disclosed in the several method embodiments provided in the present application may be combined arbitrarily without conflict to obtain new method embodiments.
The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present application, and shall be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
Claims (16)
1. A semiconductor structure, comprising:
an active pillar group located in the semiconductor layer; the active column set includes: a first active pillar and a second active pillar;
the first air gap isolation structure is positioned between the adjacent active column groups;
a second air gap isolation structure located between adjacent first and second active pillars.
2. The semiconductor structure of claim 1, wherein the groups of active pillars are arranged in an array along a first direction and a second direction, respectively; the first direction and the second direction are both vertical to the thickness direction of the semiconductor layer;
the first active pillar and the second active pillar are arranged in parallel along the first direction;
the semiconductor structure further includes:
a first gate structure located between the second air gap isolation structure and the first active pillar;
a second gate structure located between the second air gap isolation structure and the second active pillar.
3. The semiconductor structure of claim 2, wherein a dimension of the second gapped isolation structure along the first direction is greater than a dimension of the first gapped isolation structure along the first direction.
4. The semiconductor structure of claim 2, further comprising: insulating layers between the first gate structure and the first active pillar, between the second gate structure and the second active pillar, and between the first air gap isolation structure and the set of active pillars;
the protective layer is positioned above the active column group and the first air gap isolation structure;
and the cap layer is positioned above the second air gap isolation structure and the first gate structure and the second gate structure, and the top of the cap layer is flush with the top of the protective layer.
5. The semiconductor structure of claim 4, further comprising:
a support layer between the first and second active pillars and below the first and second gate structures.
6. The semiconductor structure of claim 1, wherein the first active pillar and the second active pillar each comprise:
a channel region;
a source electrode positioned at a first end of the channel region;
a drain at a second end of the channel region; the first end and the second end are two opposite ends in the extending direction of the channel region respectively; the extending direction is parallel to the direction of the thickness of the semiconductor layer.
7. The semiconductor structure of claim 2, wherein an angle between the first direction and the second direction is in a range of 0-90 degrees.
8. A memory, comprising:
the semiconductor structure of any one of claims 1 to 7;
the memory cell is connected with one of a source electrode and a drain electrode of one active column in the semiconductor structure; and
a bit line connected to a remaining one of the source and the drain of each active pillar in a row of active pillars in the semiconductor structure.
9. A storage system, comprising:
the memory of claim 8; and the number of the first and second groups,
a memory controller connected with the memory and used for controlling the memory.
10. A method of fabricating a semiconductor structure, comprising:
providing a semiconductor layer;
forming a first groove and a second groove;
forming a third trench; the second trench and the third trench divide the semiconductor layer into an active pillar group; the active pillar set includes a first active pillar and a second active pillar spaced apart by the first trench; forming a protective layer on the second trench to form a first air gap isolation structure in the second trench;
forming a first gate structure covering one side of the first active column and a second gate structure covering one side of the second active column on the side wall of the first groove, and forming a fourth groove between the first gate structure and the second gate structure;
and forming a cap layer on the fourth trench to form a second air gap isolation structure in the fourth trench.
11. The manufacturing method according to claim 10, wherein the first trenches and the second trenches penetrate the semiconductor layer and are alternately arranged in a first direction; the third grooves penetrate through the semiconductor layer and are arranged along a second direction;
the active column groups are respectively arranged in an array along a first direction and a second direction; the first direction and the second direction are both vertical to the thickness direction of the semiconductor layer;
the first active pillar and the second active pillar are juxtaposed along the first direction.
12. The manufacturing method according to claim 11,
after the first trench and the second trench are formed, forming an insulating layer on the side wall of each of the first trench and the second trench;
the forming a protective layer on the second trench includes:
forming a protective layer in contact with the insulating layer on the top of the second trench in which the insulating layer is formed;
the method further comprises the following steps:
and when forming the protective layer on the second groove, forming the protective layer covering the insulating layer in the first groove formed with the insulating layer.
13. The method of manufacturing of claim 12, further comprising:
before forming a first gate structure covering one side of the first active column and a second gate structure covering one side of the second active column, filling an insulating material in a first trench in which a protective layer is formed, and removing a part of the protective layer, a part of the insulating layer and a part of the insulating material in the first trench to form a support layer at the bottom of the first trench.
14. The method of manufacturing of claim 10, wherein the providing a semiconductor layer comprises:
providing a substrate; the substrate comprises silicon-on-insulator, wherein the silicon-on-insulator comprises bottom silicon, middle silicon oxide on the bottom silicon, and top silicon on the middle silicon oxide; the top silicon layer is the semiconductor layer;
the first trench and the second trench penetrate the top layer silicon.
15. The method of manufacturing of claim 10, wherein the first gate structure comprises a first gate oxide layer and a first gate; the second grid structure comprises a second grid oxide layer and a second grid;
the forming a first gate structure covering one side of the first active pillar and a second gate structure covering one side of the second active pillar on a sidewall of the first trench includes:
forming a first grid electrode oxidation layer on one side of the first active column; forming a first gate overlying the first gate oxide layer; and
forming a second grid electrode oxidation layer on one side of the second active column; and forming a second grid electrode covering the second grid electrode oxidation layer.
16. A method of manufacturing a memory, the method comprising:
forming a semiconductor structure; the semiconductor structure is manufactured by the manufacturing method of the semiconductor structure provided by any one of the above claims 10 to 15;
forming a memory cell, wherein the memory cell is connected with one of a source electrode and a drain electrode of an active column in the semiconductor structure;
forming a bit line connected to a remaining one of the source and the drain of a row of active pillars in the semiconductor structure.
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