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CN115206880A - Preparation method of GaN tube core - Google Patents

Preparation method of GaN tube core Download PDF

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Publication number
CN115206880A
CN115206880A CN202210834308.0A CN202210834308A CN115206880A CN 115206880 A CN115206880 A CN 115206880A CN 202210834308 A CN202210834308 A CN 202210834308A CN 115206880 A CN115206880 A CN 115206880A
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Prior art keywords
wafer
gan
layer
substrate
cutting
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CN202210834308.0A
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Inventor
程海英
许东
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Shanghai Xinwei Semiconductor Co ltd
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Shanghai Xinwei Semiconductor Co ltd
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Priority to CN202210834308.0A priority Critical patent/CN115206880A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
    • H01L21/3043—Making grooves, e.g. cutting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/8252—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using III-V technology

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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Abstract

The invention provides a preparation method of a GaN tube core, which comprises the following steps: performing a front side process on the GaN wafer to obtain a plurality of GaN die; defining a cutting channel between adjacent GaN tube cores on the front surface of the GaN wafer, and removing a GaN epitaxial layer in the cutting channel; enabling the front surface of the GaN wafer to face the temporary bonding substrate and bonding the GaN wafer and the temporary bonding substrate; thinning the back of the substrate to obtain a wafer; carrying out surface treatment on the back surface of the wafer; carrying out back through hole etching on the wafer; back metallization is carried out on the wafer; separating the wafer from the temporary bonding substrate; carrying out laser invisible cutting on the front side of the wafer along the cutting channel; and splitting and separating the GaN tube core along the cutting path. The invention realizes the hidden cutting and splitting without edge breakage and chipping based on the GaN tube core, and avoids the edge breakage of split pieces caused by the material characteristic difference between the substrate and the GaN epitaxial layer grown by heteroepitaxy when the tube core is cut.

Description

Preparation method of GaN tube core
Technical Field
The invention belongs to the field of semiconductor device manufacturing, and particularly relates to a preparation method of a GaN tube core.
Background
In recent years, the progress of engineering and commercialization of silicon carbide substrates and GaN epitaxial materials and devices on silicon substrates has increased. In order to meet the high-power and high-frequency characteristic requirements of radio frequency devices, the advantages of gallium nitride-based heterojunction materials in the aspect of manufacturing high-frequency devices are exerted, and besides new epitaxial structures and processes are continuously proposed to improve the performance of the devices in a high-frequency mode, more and more technical developments and researches are being carried out around improving the wafer yield and reliability.
The back section process of the SiC-based GaN radio frequency device generally adopts the following process method: after the front surface of the wafer is processed, the front surface of the wafer and the slide glass substrate are temporarily bonded together, the back surface of the wafer is exposed after bonding, the back surface of the wafer is thinned, and then processing methods such as back surface through holes, back surface metallization, chip cutting and the like are carried out after thinning.
However, the following problems in wafer yield and reliability may be caused in the current processing method: 1) The wafer surface stress is large after the back surface is thinned and polished, so that the etching uniformity of the through holes of the wafer is difficult to control, and the wafer can generate microcracks or fractures due to the introduction of stress in severe cases; 2) A commonly used wafer cutting process is that a wafer is attached to a scribing film, the back surface of the wafer is contacted with the scribing film, and the scribing film is positioned on a cutting ring; the front surface of the wafer is cut along the cutting path, then the wafer is split and cracked, so that the tube core is separated into individual bodies along the crack direction, and edge breakage is easily caused in the wafer splitting process after the cutting step due to the material characteristic difference between the substrate and the GaN epitaxial layer, such as the material characteristic difference between the SiC substrate and the GaN epitaxial layer, and the die splitting loss is caused.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide a method for fabricating a GaN die, which is used to solve the problems of device yield loss caused by edge chipping due to the difference in material characteristics between the substrate and the heteroepitaxially grown GaN epitaxial layer, and microcracking or fracture caused by stress due to backside metallization in the prior art.
To achieve the above and other related objects, the present invention provides a method for fabricating a GaN die, comprising:
providing a substrate, and carrying out heteroepitaxial growth on the front surface of the substrate to obtain a GaN wafer;
performing a front side process on the GaN wafer to obtain a plurality of GaN die;
defining cutting channels between adjacent GaN tube cores on the front surface of the GaN wafer, and removing the GaN epitaxial layer in the cutting channels;
enabling the front surface of the GaN wafer to face a temporary bonding substrate and bonding the GaN wafer with the temporary bonding substrate;
thinning the back surface of the substrate to obtain a thin wafer;
carrying out surface treatment on the back surface of the wafer;
carrying out back through hole etching on the wafer;
back metallization is carried out on the wafer;
separating the wafer from the temporary bonded substrate;
carrying out laser invisible cutting on the front side of the wafer along a cutting channel;
and separating the GaN tube core along the cutting path.
Optionally, back side metallization is performed on the wafer, including the steps of:
forming a metal seed layer on the back surface of the wafer;
forming a photoresist layer on the back surface of the wafer, and defining a preset groove area aligned with the cutting channel through a photoetching process, wherein the preset groove area is covered by the exposed photoresist layer and the area outside the preset groove area is exposed;
forming a first metal layer on the back surface of the wafer, wherein the first metal layer is at least formed in a region outside the preset groove region;
and stripping the photoresist layer covering the preset groove area.
Optionally, a second metal layer is further disposed on the GaN wafer, and the through hole is formed by etching through the second metal layer from the back surface of the wafer by using an etching process, and is used for realizing back extraction of the device unit in the wafer.
Optionally, the metal seed layer is a TiW layer or a stack of a Ti layer and an Au layer, the thickness of the TiW layer or the Ti layer is in a range of 100 nm to 200 nm, and the thickness of the Au layer is in a range of 400 nm to 600 nm.
Optionally, the surface treatment is dry etching, wet etching or a combination of both processes.
Optionally, the first metal layer is formed by an electroplating or evaporation process, and the first metal layer includes an Au plating layer, and a thickness of the Au plating layer ranges from 3 micrometers to 5 micrometers.
Optionally, the first metal layer covers the photoresist layer on the preset trench region; and stripping the photoresist layer covering the preset groove area, and simultaneously removing the first metal layer formed on the surface of the photoresist layer to expose the preset groove, wherein the width range of the preset groove is 20-50 microns.
Optionally, after the back side metallization is performed on the thin wafer, forming a protection layer resistant to wet etching on the back side of the thin wafer.
Optionally, a material for forming the protective layer is selected from any one of polyimide and polyparaphenylene benzobisoxazole.
Optionally, the step of separating the sheet wafer from the temporary bonding substrate is performed by using a thermal separation process or a chemical immersion method, and the bonding surface of the sheet wafer is wet-cleaned.
As described above, the present invention provides a method for manufacturing a GaN die, which achieves the following advantages in terms of wafer back-end process yield and wafer reliability:
1) The invention realizes edge-breakage-free and debris-free splitting based on the GaN tube core, and avoids edge breakage caused by material characteristic difference between the substrate and the GaN epitaxial layer grown by heteroepitaxy by providing a GaN tube core splitting scheme without edge breakage and tube core scribing loss during cutting; in addition, the wafer is cut through a laser invisible cutting process, and the modified layers formed at different depths extend the stress to the back of the wafer for releasing, so that edge breakage, chipping and obvious meandering are avoided in the cutting process;
2) According to the invention, after the wafer is thinned and polished, surface treatment is introduced to release residual stress caused by thinning and polishing;
3) According to the back metallization of the thin wafer, the photoresist layer is used for defining the preset groove area, the preset groove area is aligned to the cutting channel positioned on the front side of the wafer, the photoresist layer is used for covering the preset groove area, the back of the thin wafer is metallized, the groove area is shielded, the possibility of forming a continuous thick metal layer on the back is blocked, the problem that the yield of a device is influenced by stress caused by the metallization of the whole back is avoided, the related process of forming back cutting is effectively simplified, the manufacturing cost is saved, and the yield of the device is improved;
4) Furthermore, the protective layer is formed on the back surface of the wafer to reduce uneven stress caused by subsequent processes and avoid microcracking or fracture caused by stress.
Drawings
Fig. 1 to 7 show schematic structural views of steps of a GaN die fabrication method according to an embodiment of the present invention.
Description of the element reference numerals
100. Substrate and method of manufacturing the same
102. Wafer of thin sheet
110 GaN epitaxial layer
112. Cutting path
120. Through hole
130. Metal seed layer
140. 140a photoresist layer
150. Plating or evaporating metal layer
152. Preset groove
200. Temporary bonding substrate
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
As in the detailed description of the embodiments of the present invention, the cross-sectional views illustrating the device structure are not partially enlarged in general scale for convenience of illustration, and the schematic views are only examples, which should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.
For convenience in description, spatial relational terms such as "below," "beneath," "below," "under," "over," "upper," and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that these terms of spatial relationship are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. Further, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.
In the context of this application, a structure described as having a first feature "on" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed in between the first and second features, such that the first and second features may not be in direct contact.
It should be noted that the drawings provided in the present embodiment are only for schematically illustrating the basic idea of the present invention, and the drawings only show the components related to the present invention rather than being drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of each component in actual implementation may be arbitrarily changed, and the layout of the components may be more complicated.
In order to solve the problems of edge breakage caused by material characteristic difference between a substrate and a heteroepitaxial growth GaN epitaxial layer, microcracking or fracture caused by stress caused by back metallization and the like in the prior art, the wafer is metallized after a photoresist layer is used for covering a preset groove region, the preset groove region aligned with a cutting channel is defined and shielded on the back of the wafer through the photoresist layer, the possibility of forming a metal layer on the whole back is blocked, the problems of stress caused by back whole-surface metallization and influencing the yield of a device are solved, and simultaneously, a back process is simplified.
As shown in fig. 1 to 7, this embodiment provides a method for manufacturing a GaN die, which includes the following steps:
as shown in fig. 1, step 1) is performed first, a substrate 100 is provided, and heteroepitaxial growth is performed on the front surface of the substrate 100 to obtain a GaN wafer.
The material of the substrate includes any one of sapphire, siC, and Si, for example.
Continuing with fig. 1, step 2) is performed to perform a front side process on the GaN wafer to obtain a plurality of GaN die formed based on the heteroepitaxially grown GaN epitaxial layer 110 on the substrate 100.
By way of example, the front side of the substrate 100 has a GaN die-based device unit formed by a front side process, which may be, for example, a GaN-based optoelectronic device, a GaN-based high mobility power device, a GaN-based diode, or the like. In this embodiment, the substrate is a SiC-based substrate, and a front surface of the SiC-based substrate may be formed with a GaN die-based radio frequency device unit.
And then, performing step 3), defining cutting channels 112 between adjacent GaN tube cores on the front surface of the GaN wafer, and removing the GaN epitaxial layer in the cutting channels.
As an example, dicing streets 112 between adjacent GaN dies are defined on the surface of the GaN wafer through a photolithography process, and the GaN epitaxial layers in the dicing streets 112 are removed by dry etching, wet etching or a combination of the two processes. Due to the fact that the step of removing the GaN epitaxial layer in the cutting channel is introduced in the front face process of the wafer, the subsequent wafer splitting process is substantially epitaxial layer-free scribing, and edge breakage caused by material characteristic difference between the substrate (such as a SiC-based substrate) and the GaN epitaxial layer is avoided.
As shown in fig. 2, step 4) is then performed to bond the GaN wafer with a temporary bonding substrate 200. Specifically, step 4) includes: and coating bonding glue or bonding wax on the front surface of the GaN wafer, so that the GaN wafer faces the temporary bonding substrate 200 and is bonded with the temporary bonding substrate 200 to form a bonding piece.
With continued reference to fig. 2, step 5) is performed to thin the back side of the substrate 100 by using the bonding sheet obtained in step 4) to obtain a sheet wafer 102.
As an example, step 5) further comprises: and polishing the thinned substrate to obtain a thin wafer 102 bonded with the temporary bonding substrate 200, wherein the thickness of the thin wafer 102 is 50-100 microns. In this embodiment, the thickness of the wafer 102 may be 75 μm.
Step 6) is then performed to perform surface treatment on the back surface of the sheet wafer 102. Specifically, after the thinning and polishing processes, the back surface of the wafer sheet 102 is subjected to surface treatment to release the residual stress on the surface of the substrate caused by the thinning and polishing. In this embodiment, the surface treatment is dry etching, wet etching or a combination of the two processes.
Then, step 7) is performed to perform via etching on the thin wafer 102.
Specifically, an etching process is adopted to form a through hole 120 from the back surface of the thin wafer 102 to the second metal layer, so as to achieve back surface extraction of the device unit in the thin wafer 102. That is, the through hole 120 is formed as a second metal layer (not shown) penetrating from the back surface to the front surface of the sheet wafer, the second metal layer being formed on the surface of the GaN wafer in the front surface process of the GaN wafer.
As shown in fig. 3 to 5 and 6A to 6B, step 8) of metallizing the back side of the wafer 102 is performed, which includes at least the following steps: 8-1) forming a metal seed layer 130 on the back side of the wafer 102; 8-2) forming a photoresist layer 140 on the back surface of the wafer 102, and defining a predetermined trench region aligned with the scribe line 112 by a photolithography process; 8-3) forming a first metal layer 150 on the backside of the wafer 102.
As an example, step 8) further comprises: cleaning the wafer 102 and the through holes 120 before forming the metal seed layer 130 on the backside of the wafer 102 in step 8-1), wherein the cleaning may be wet cleaning or dry cleaning, or a combination thereof. The cleaning can remove oxide layers or impurities, such as polymers, on the surface of the wafer and in the through hole 120, so as to obtain a smooth through hole 120 with a smooth surface and inner wall of the wafer.
As an example, as shown in fig. 3, at step 8-1), a continuous metal seed layer 130 is formed on the back surface of the thin wafer 102 by a sputtering process, and the metal seed layer 130 is formed on the back surface of the thin wafer 102 and the inner wall of the through hole 120 to form a continuous metal film layer. The metal seed layer has proper thickness to ensure the continuity of the back through hole and the metal seed layer around the back through hole, avoid the discontinuity of the metal seed layer from influencing the subsequent electroplating, and cannot influence the subsequent splitting effect. For example, the metal seed layer 130 may include a TiW layer or a stack of a Ti layer and an Au layer, the thickness of the TiW layer or the Ti layer ranges from 100 nm to 200 nm, and the thickness of the Au layer ranges from 400 nm to 600 nm. In this embodiment, the thickness of the TiW layer is 150 nm, and the thickness of the Au layer is 500 nm.
As shown in fig. 4 to 5, in step 8-2), a photoresist layer 140 is formed on the back surface of the thin wafer 102, and a predetermined trench area aligned with the scribe line 112 is defined through a photolithography process, wherein the predetermined trench area is covered by the photoresist layer 140a and an area outside the predetermined trench area is exposed.
As an example, a photoresist layer 140 may be formed on the back surface of the thin wafer 102 through a spin coating process, and the photoresist layer 140 is baked; then, the photoresist layer 140 is exposed and developed through a photolithography process to define a predetermined trench region, wherein the predetermined trench region is covered by the developed photoresist layer 140a and exposes a region outside the predetermined trench region.
As an example, in step 8-3), a first metal layer 150 is formed on the back side of the sheet wafer 102, where the first metal layer 150 is formed at least in a region other than the predetermined trench region.
As an example, the first metal layer 150 is formed by an electroplating or evaporation process, and the first metal layer 150 includes an Au plating layer having a thickness of 3 to 5 micrometers. In this embodiment, the thickness of the Au plating layer is 4 μm.
In an example, as shown in fig. 6A, the first metal layer is formed by an electroplating process, and during the electroplating process, the predetermined trench region is covered by the photoresist layer 140a, so that the first metal layer is not formed as a continuous metal plating layer, but is separated into multiple sections by the photoresist layer 140 a. Since the metal plating layer is formed on the back surface of the wafer after the predetermined trench region is defined in the photoresist layer 140a, stress caused by metallization of the entire back surface of the wafer 102 is avoided, and the process is simplified.
In another example, as shown in fig. 6B, the first metal layer is formed by an evaporation process, during the evaporation process, the predetermined trench region is covered by the photoresist layer 140a, the first metal layer is formed on the surface of the photoresist layer 140a, and when the photoresist layer 140a is removed, the first metal layer on the surface of the photoresist layer 140a is also removed.
With continued reference to fig. 6A, step 8) further comprises: 8-4) stripping the photoresist layer 140a covering the predetermined trench region to expose the predetermined trench 152. In this embodiment, the depth of the predetermined trench 152 is determined based on the thickness of the first metal layer 150, and the width of the predetermined trench 152 ranges from 20 micrometers to 50 micrometers.
As an example, in step 8-4), the photoresist layer 140a covering the predetermined trench region is stripped by using a wet stripping process, and at this time, the surface of the wafer in the predetermined trench 152 is covered by only one metal seed layer 130 with a relatively small thickness, so as to form a back scribe line.
Step 9) is then performed to separate the wafer 102 from the temporary bond substrate 200.
Specifically, before separating the wafer 102 from the temporary bonding substrate 200 in step 9), a protection layer (not shown) against wet etching may be formed on the back surface of the substrate. For example, the protective layer may be formed by applying a spin coating process to the back surface of the substrate and then curing the protective layer by baking to protect the wafer surface from the stress non-uniformity of the subsequent process. The material used to form the protective layer may be an organic material that is resistant to chemical solutions of the subsequent cleaning process, such as Polyimide (PI), poly-p-Phenylene Benzobisoxazole (PBO), or similar organic materials, so as to resist chemical solutions containing absolute ethyl alcohol and acetone in the subsequent cleaning process.
As an example, the step of separating the front surface of the sheet wafer 102 from the temporary bonding substrate 200 is performed by using a thermal separation process or a chemical immersion method, and the bonding surface of the sheet wafer 102 is wet-cleaned to remove an oxide layer or impurities, such as residual bonding glue or bonding wax, on the surface of the sheet wafer.
And finally, performing a step 10), as shown in fig. 7, performing a cutting process along the cutting street 112, so that the plurality of GaN die particles are split and separated along the cutting street 112.
As an example, performing a laser stealth dicing process on the front side of the sheet wafer 102 includes: multiple modified layers are formed in the substrate by focusing laser energy, for example, multiple modified layers (generally, three modified layers) with different pitches are formed in the SiC substrate, so that stress released by the modified layers extends to the back side of the wafer. In this embodiment, in step 10), the thin wafer 102 may be fixed on a cutting ring with a blue film, and a laser stealth cutting process is performed on the front surface of the thin wafer 102, so as to promote die cracking without edge chipping, without chipping, and without significant meandering, thereby further reducing the die dicing loss. Due to the protection layer formed on the back surface of the wafer 102 in the previous step 9), microcracks or fractures that may be generated during the wafer dicing process can be further alleviated.
In addition, it should be noted that although the laser is used to form the modified layer and perform the stealth dicing process in the embodiment, the invention does not exclude the laser to implement the dicing process, for example, the plasma deep etching or the chemical etching after the deep etching is used to implement the dicing process. The step 10) may further include: after the GaN tube core is split along the cutting street 112, the mutually independent device units are obtained by adopting a film expanding process.
As described above, the GaN tube core preparation method provided by the invention has the following beneficial effects:
according to the back metallization of the thin wafer, the photoresist layer is used for defining the preset groove area, the preset groove area is aligned to the cutting channel positioned on the front side of the wafer, the photoresist layer is used for covering the preset groove area, the back side of the wafer is metallized while the back side cutting channel is defined, the possibility that a continuous thick metal layer is formed on the back side is blocked, the problem that the yield of a device is influenced by stress caused by the metallization of the whole back side is avoided, the related process of the back side cutting channel is effectively simplified, the manufacturing cost is saved, and the yield of the device is improved. In addition, the invention introduces the step of surface treatment to release the residual stress caused by thinning and polishing after the thinning and polishing treatment of the wafer, thereby improving the yield of the back section process.
According to the invention, edge breakage-free and debris-free splitting based on the GaN tube core is realized after the back surface metallization of the wafer sheet is completed, and edge breakage caused by material characteristic difference between the GaN epitaxial layer and the SiC-based substrate is avoided by providing a GaN tube core preparation scheme without edge breakage and tube core scribing loss during cutting; in addition, the wafer is cut through the laser invisible cutting process, the modified layers formed at different depth positions extend the stress to the back of the wafer to be released, edge breakage, chipping and obvious meandering are avoided in the cutting process, and the yield of the wafer back section processing process and the reliability of the wafer are further improved.
Therefore, the present invention effectively overcomes several disadvantages of the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.

Claims (10)

1. A method of fabricating a GaN die, the method comprising:
providing a substrate, and carrying out heteroepitaxial growth on the front surface of the substrate to obtain a GaN wafer;
performing a front side process on the GaN wafer to obtain a plurality of GaN die;
defining cutting channels between adjacent GaN tube cores on the front surface of the GaN wafer, and removing the GaN epitaxial layer in the cutting channels;
enabling the front surface of the GaN wafer to face a temporary bonding substrate and bonding the GaN wafer with the temporary bonding substrate;
thinning the back surface of the substrate to obtain a thin wafer;
carrying out surface treatment on the back surface of the wafer;
carrying out back through hole etching on the wafer;
back metallization is carried out on the wafer;
separating the wafer from the temporary bonding substrate;
carrying out laser invisible cutting on the front side of the wafer along a cutting channel;
and splitting the GaN tube core along the cutting path.
2. A method of manufacturing as claimed in claim 1 wherein back side metallization of the wafer sheet comprises the steps of:
forming a metal seed layer on the back surface of the wafer;
forming a photoresist layer on the back surface of the wafer, and defining a preset groove region aligned with the cutting channel through a photoetching process, wherein the preset groove region is covered by the exposed photoresist layer and the region outside the preset groove region is exposed;
forming a first metal layer on the back surface of the wafer, wherein the first metal layer is at least formed in a region outside the preset groove region;
and stripping the photoresist layer covering the preset groove area.
3. The manufacturing method according to claim 1, wherein a second metal layer is further disposed on the GaN wafer, and the through hole is formed by etching through the second metal layer from the back surface of the wafer by using an etching process, and is used for realizing back surface extraction of the device unit in the wafer.
4. The method according to claim 2, wherein the metal seed layer is a TiW layer or a stack of a Ti layer and an Au layer, the thickness of the TiW layer or the Ti layer is in a range of 100 nm to 200 nm, and the thickness of the Au layer is in a range of 400 nm to 600 nm.
5. The method of claim 1, wherein the surface treatment is dry etching, wet etching, or a combination of both processes.
6. The method of claim 1, wherein: the first metal layer is formed through an electroplating or evaporation process, the first metal layer comprises an Au plating layer, and the thickness range of the Au plating layer is 3-5 micrometers.
7. The method of claim 2, wherein: the first metal layer covers the photoresist layer on the preset groove area; and stripping the photoresist layer covering the preset groove area, and simultaneously removing the first metal layer formed on the surface of the photoresist layer to expose the preset groove, wherein the width range of the preset groove is 20-50 microns.
8. The method as claimed in claim 1, further comprising forming a protection layer on the backside of the wafer after the backside metallization.
9. The production method according to claim 8, wherein a material for forming the protective layer is selected from any one of polyimide and polyparaphenylene benzobisoxazole.
10. A producing method according to claim 1, wherein the step of separating the sheet wafer from the temporary bonding substrate is performed by a thermal separation process or a chemical immersion method, and a bonding face of the sheet wafer is wet-cleaned.
CN202210834308.0A 2022-07-14 2022-07-14 Preparation method of GaN tube core Pending CN115206880A (en)

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