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CN115140700A - Semiconductor assembly and cutting method thereof, filter and electronic equipment - Google Patents

Semiconductor assembly and cutting method thereof, filter and electronic equipment Download PDF

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Publication number
CN115140700A
CN115140700A CN202110343060.3A CN202110343060A CN115140700A CN 115140700 A CN115140700 A CN 115140700A CN 202110343060 A CN202110343060 A CN 202110343060A CN 115140700 A CN115140700 A CN 115140700A
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China
Prior art keywords
substrate
sealing layer
predetermined portion
sealing
upper side
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Pending
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CN202110343060.3A
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Chinese (zh)
Inventor
徐洋
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ROFS Microsystem Tianjin Co Ltd
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ROFS Microsystem Tianjin Co Ltd
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Priority to CN202110343060.3A priority Critical patent/CN115140700A/en
Priority to PCT/CN2022/080121 priority patent/WO2022206331A1/en
Publication of CN115140700A publication Critical patent/CN115140700A/en
Pending legal-status Critical Current

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    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B7/00—Microstructural systems; Auxiliary parts of microstructural devices or systems
    • B81B7/02—Microstructural systems; Auxiliary parts of microstructural devices or systems containing distinct electrical or optical devices of particular relevance for their function, e.g. microelectro-mechanical systems [MEMS]
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B7/00—Microstructural systems; Auxiliary parts of microstructural devices or systems
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B7/00—Microstructural systems; Auxiliary parts of microstructural devices or systems
    • B81B7/0006—Interconnects
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
    • B81C1/00261—Processes for packaging MEMS devices
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
    • B81C1/00261—Processes for packaging MEMS devices
    • B81C1/00301—Connecting electric signal lines from the MEMS device with external electrical signal lines, e.g. through vias
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B2201/00—Specific applications of microelectromechanical systems
    • B81B2201/02—Sensors
    • B81B2201/0271—Resonators; ultrasonic resonators

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Micromachines (AREA)

Abstract

The invention relates to a method for cutting a semiconductor assembly, which comprises the following steps: step 1: providing a first substrate, a second substrate, a sealing layer and a MEMS device, wherein the sealing layer is arranged between the lower side of the first substrate and the upper side of the second substrate, the first substrate, the second substrate and the sealing layer define or enclose a containing space, and the MEMS device is arranged in the corresponding containing space, wherein: the sealing layer comprises a first sealing layer arranged on the first substrate and a second sealing layer arranged on the second substrate, and the first sealing layer is suitable for being in sealing connection with the second sealing layer; step 2: removing a predetermined portion of the peripheral region of the first substrate to expose a second sealing layer corresponding to the predetermined portion; and 3, step 3: and cutting by taking the second sealing layer corresponding to the predetermined part as an alignment mark.

Description

Semiconductor assembly and cutting method thereof, filter and electronic equipment
Technical Field
Embodiments of the present invention relate to the field of semiconductors, and in particular, to a semiconductor device, a method for cutting a semiconductor device, a filter having the semiconductor device, and an electronic apparatus having the filter.
Background
Electronic devices have been widely used as basic elements of electronic equipment, and their application ranges include mobile phones, automobiles, home electric appliances, and the like. In addition, technologies such as artificial intelligence, internet of things, 5G communication and the like which will change the world in the future still need to rely on electronic devices as a foundation.
Electronic devices can exert different characteristics and advantages according to different working principles, and among all electronic devices, devices working by utilizing the piezoelectric effect (or the inverse piezoelectric effect) are important, and the piezoelectric devices have very wide application situations. Film Bulk Acoustic Resonator (FBAR, also called Bulk Acoustic Resonator, BAW for short) is playing an important role in the communication field as an important member of piezoelectric devices, especially FBAR filters have increasingly large market share in the field of radio frequency filters, FBARs have excellent characteristics of small size, high resonance frequency, high quality factor, large power capacity, good roll-off effect and the like, the filters gradually replace traditional Surface Acoustic Wave (SAW) filters and ceramic filters, play a great role in the radio frequency field of wireless communication, and the advantage of high sensitivity can also be applied to the sensing fields of biology, physics, medicine and the like.
For MEMS devices such as film bulk acoustic resonators, which are usually disposed between two substrates bonded by a sealing bonding layer, one substrate may be a functional substrate on which the MEMS device is disposed, and the other substrate may be a package substrate, but the MEMS device may also be disposed. For a separated MEMS device and its packaging structure, it can be referred to as a die.
In the manufacturing process of the MEMS device, two wafers are opposite to each other, the wafers are bonded and connected through a sealing bonding layer, and the two wafers are separated based on the sealing bonding layer, so that a plurality of die are formed between the two wafers.
Fig. 1 is a schematic structural diagram of dicing between two dice to separate the two dice in the prior art. In fig. 1, 201 and 202 are wafers or substrates, 101 is alignment marks for dicing, b is a horizontal distance between the alignment marks 101, 102 is a lower sealing structure or a lower sealing bonding layer, 104 is a conductive via, 105 is a pad, 109 is an upper sealing structure or an upper sealing bonding layer, and the bonding layer 109 and the bonding layer 102 are bonded to each other to form a sealing structure. As shown in fig. 1, the distance between the bonding layers 102 in the horizontal direction is a.
Due to the offset when bonding the two wafers, the alignment mark 101 cannot be completely aligned with the sealing structure. In order to ensure that the sealing structure is not damaged during scribing, the distance a between the lower sealing ring or the lower sealing bonding layer 102 is greater than the distance b between the scribing marks 101, and the difference between a and b is usually about 20 um.
Since the scribing belongs to physical cutting, and the track of the scribing blade cannot guarantee no deviation, the distance b between the scribing marks is larger than the thickness of the scribing blade (or the width of the laser), and is usually about 20um larger.
Therefore, when the dicing scheme shown in fig. 1 is adopted, a redundant width needs to be set, which wastes the area of the wafer.
Fig. 2 is a schematic structural diagram of performing a cutting between two die by using an etching method in the prior art. As shown in fig. 2, if the separation channels 106 are etched by etching, the distance a between the lower sealing structures 102 can be greatly reduced while ensuring accuracy, but if the dice are separated before the pad forming process, this may cause subsequent electroplating to be impossible, or may cause bonding failure due to insufficient external force that can be borne by a single die when the blade thinning process is performed.
Accordingly, there is a need in the art for improved methods of cutting between die.
Disclosure of Invention
The present invention has been made to overcome at least one aspect of the problems in the prior art.
According to an aspect of an embodiment of the present invention, there is provided a semiconductor assembly including:
a first substrate and a second substrate;
a sealing layer disposed between a lower side of the first substrate and an upper side of the second substrate;
at least one of the MEMS devices is configured to,
wherein:
the first substrate, the second substrate and the sealing layer define or enclose at least one accommodating space, and the MEMS device is arranged in the corresponding accommodating space;
the upper side of the first substrate is not provided with an alignment mark for scribing.
Embodiments of the present invention also relate to a method of dicing a semiconductor assembly, including:
step 1: providing a first substrate, a second substrate, a sealing layer and a MEMS device, wherein the sealing layer is arranged between the lower side of the first substrate and the upper side of the second substrate, the first substrate, the second substrate and the sealing layer define or enclose a containing space, and the MEMS device is arranged in the corresponding containing space, wherein: the sealing layer comprises a first sealing layer arranged on the first substrate and a second sealing layer arranged on the second substrate, and the first sealing layer is suitable for being in sealing connection with the second sealing layer;
step 2: removing a predetermined portion of the peripheral region of the first substrate to expose a second sealing layer corresponding to the predetermined portion;
and 3, step 3: and cutting the second sealing layer corresponding to the preset part as an alignment mark.
Embodiments of the present invention also relate to a filter including the semiconductor device described above.
Embodiments of the present invention also relate to an electronic device comprising a filter as described above or a semiconductor component as described above.
Drawings
These and other features and advantages of the various embodiments of the disclosed invention will be better understood from the following description taken in conjunction with the accompanying drawings, in which like reference characters designate like parts throughout, and in which:
FIG. 1 is a schematic structural diagram of a prior art dicing between two dice to separate the two dice by cutting;
FIG. 2 is a schematic structural diagram of a prior art method for performing a cut between two dice by etching;
fig. 3A and 3B are schematic structural views illustrating a cutting method between two dice according to an exemplary embodiment of the present invention, in which fig. 3A illustrates that the upper substrate has not been cut and fig. 3B illustrates that a predetermined portion around the upper substrate has been cut;
FIG. 3C is a schematic top view of the wafer structure of FIG. 3B, wherein the middle circled portion represents the upper wafer;
FIG. 3D is an enlarged partial view of the edge portion of the wafer structure of FIG. 3C;
FIG. 3E is a partial enlarged schematic view of an edge portion of a wafer structure according to another exemplary embodiment of the invention;
FIG. 4 is a schematic diagram of a two-piece wafer before incomplete dicing according to an exemplary embodiment of the invention, wherein the ellipses indicate that more die are not shown;
FIGS. 5A-5F are schematic block diagrams illustrating steps of fabricating the structure shown in FIG. 3B according to an exemplary embodiment of the present invention;
FIG. 6 is a physical map of an etched surface;
fig. 7 is an enlarged view of the etched surface of fig. 6.
Detailed Description
The technical scheme of the invention is further specifically described by the following embodiments and the accompanying drawings. In the specification, the same or similar reference numerals denote the same or similar components. The following description of the embodiments of the present invention with reference to the accompanying drawings is intended to explain the general inventive concept of the present invention and should not be construed as limiting the invention.
Fig. 3A and 3B are schematic structural views illustrating a cutting method between two die according to an exemplary embodiment of the present invention, in which fig. 3A illustrates that the upper substrate has not been cut, and fig. 3B illustrates that a predetermined portion of the periphery of the upper substrate has been cut. Fig. 3C is a schematic top view of the wafer structure in fig. 3B, wherein the middle circled portion represents the upper wafer.
In fig. 3A and 3B, 201 and 202 are wafers or substrates, 102 is a lower sealing structure or a lower sealing bonding layer, 104 is a conductive via, 105 is a pad, 109 is an upper sealing structure or an upper sealing bonding layer, and the bonding layer 109 and the bonding layer 102 are bonded to each other to form a sealing structure.
In layout design, as shown in fig. 3A, the hermetic bonding layer 109 on the substrate 202 is removed within a range of a peripheral width b (generally, 1mm to 10mm, and further, 1mm to 3.5 mm) of the substrate 202, so that two substrates in a region corresponding to b in fig. 3A are in a non-bonding state.
Next, as shown in fig. 3B, the region corresponding to B of the substrate 202 is removed by a cutting method, so that the hermetic bonding layer 102 on the upper side of the substrate 201 is exposed. As such, as shown in fig. 3C, the sealing bonding layer 102 of the outer edge peripheral region of the substrate 201 may be exposed.
Fig. 3D is a partially enlarged view of the edge portion of the wafer structure in fig. 3C. As can be seen in fig. 3D, the hermetic bonding layers 102 (thin solid lines) are criss-crossed, defining a rectangular area enclosing the MEMS device 103. The thin solid lines or the sealing bonding layers 102 form cutting channels therebetween, which are cross scribe streets and longitudinal scribe streets in fig. 3D.
On the basis of the structure shown in fig. 3C, cutting may be performed with a cutting tool along the dicing streets shown in fig. 3D, thereby forming individual dice.
The scribing method has the advantages that the alignment problem between the scribing mark 101 and the sealing bonding layer 102 which are set later is avoided, so that the extra sealing ring distance (usually 20 um) for the alignment can be avoided, and the die yield of the single wafer is improved.
Fig. 3E is a partially enlarged schematic view of an edge portion of a wafer structure according to another exemplary embodiment of the invention. Fig. 3E differs from fig. 3D in that, in fig. 3E, an edge portion (corresponding to the portion 107 in fig. 3E) of the first substrate 202 is not removed, but a portion of the first substrate 202 is removed at a predetermined distance (for example, not more than 3mm, as long as it is ensured that the hermetic bonding layer 102 that can be exposed when dicing is performed can perform an alignment function) from the edge of the first substrate 202 to expose the hermetic bonding layer 102.
Fig. 4 is a schematic structural diagram of two wafers before the incomplete dicing according to an exemplary embodiment of the present invention, wherein the ellipses indicate that more die are not shown. The structure shown in fig. 4 is similar to that shown in fig. 3B.
Other methods of exposing the hermetic bonding layer 102 may be used in addition to the cutting method described with reference to fig. 3A and 3B. The following is an exemplary description with reference to fig. 5A-5F. Fig. 5A-5F are schematic block diagrams illustrating steps of fabricating the structure shown in fig. 3B, according to an exemplary embodiment of the present invention.
As shown in fig. 5A, a substrate 202 is provided.
As shown in fig. 5B, a via hole 104 is etched on one side of the substrate 202 to form a sealing bonding layer 109, and a notch 110 is formed in an edge region of the substrate 202. To save costs, the through-hole 104 may not extend through the substrate 202, and the through-hole 104 is formed simultaneously with the notch 110.
As shown in fig. 5C, a substrate 201 is provided, on one side of which the MEMS device 103 and the sealing bonding layer 102 are disposed.
As shown in fig. 5D, the substrate 201 in fig. 5C and the substrate 202 in fig. 5B are bonded to each other, and at this time, the sealing bonding layer 102 and the sealing bonding layer 109 are bonded to each other.
As shown in fig. 5E, a predetermined thickness of the base material may be removed from the upper side of the base 202 in fig. 5E by a grinding process or the like to remove a portion corresponding to the gap 110 in fig. 5D, thereby exposing the hermetic bonding layer 102 on the base 201.
As shown in fig. 5F, a metal pad 105 is fabricated.
The subsequent cutting operation is the same as the structure shown in fig. 3B.
Based on the above, the method of the present invention can eliminate the scribe alignment mark 101 in fig. 1, so the present invention provides a semiconductor device in which the side of the substrate on which the scribe alignment mark 101 is disposed in the prior art is not provided with the alignment mark for scribing.
Since the scribe alignment mark 101 is often disposed in the same layer and spaced apart from the metal pad 105 in the related art, in the semiconductor module proposed in the present invention, no scribe alignment mark disposed in the same layer and spaced apart from the conductive pad is disposed between the outer edge of the conductive pad and the end surface of the substrate on which the conductive pad is disposed.
In the present invention, a cutting scheme such as that shown in fig. 3A and 3B may be employed instead of the etching scheme shown in fig. 2 in the related art, and therefore, the end surface of the substrate of the semiconductor package obtained based on the cutting scheme such as that shown in fig. 3A and 3B is cut and formed instead of etching, that is, in the present invention, the end surface of the substrate 202 does not have a texture formed based on etching. Fig. 6 is a physical view of an etched surface, and fig. 7 is an enlarged view of the etched surface in fig. 6. As shown in fig. 7, the etched surface has a pore texture. The end surface of the substrate 202 not having a texture based on etching may indicate that the end surface does not have a pore texture.
In the above examples of the present invention, the sealing bonding layers 102 and 109 are both metal bonding layers as an example, but the bonding layer for forming the seal may not be a metal bonding layer. In addition, in the MEMS device packaging structure, a special sealing layer is arranged on the outer side of the metal bonding layer for metal bonding to play a sealing role, and in this case, the cutting method of the invention takes the special sealing layer which is basically exposed in the other part as a cutting guide reference.
In the claims of the present invention, the positional relationship between the first substrate and the second substrate is not clear, and the first substrate may be above the second substrate, or the second substrate may be above the first substrate. For a substrate on which a scribe alignment mark is to be provided in the related art, the upper side of the substrate is the side of one substrate on which the scribe alignment mark is to be provided. Accordingly, in the claims of the present invention, a side of the first substrate on which the scribe alignment mark needs to be provided but the dicing scheme of the present invention is not provided is an upper side of the first substrate, and an upper side of the second substrate is a side opposite to a lower side of the first substrate in the related art.
As can be appreciated by those skilled in the art, the semiconductor assembly according to the present invention may be used to form a filter or an electronic device. The electronic device includes, but is not limited to, intermediate products such as a radio frequency front end and a filtering and amplifying module, and terminal products such as a mobile phone, WIFI and an unmanned aerial vehicle.
It is to be noted that, in the present invention, each numerical range, except when explicitly indicated as not including the end points, can be either the end points or the median of each numerical range, and all fall within the scope of the present invention.
Based on the above, the invention provides the following technical scheme:
1. a semiconductor assembly, comprising:
a first substrate and a second substrate;
a sealing layer disposed between a lower side of the first substrate and an upper side of the second substrate;
at least one of the MEMS devices is configured to,
wherein:
the first substrate, the second substrate and the sealing layer define or enclose at least one accommodating space, and the MEMS device is arranged in the corresponding accommodating space;
the upper side of the first substrate is not provided with alignment marks for scribing.
2. The assembly of claim 1, wherein:
the assembly includes a conductive via through the first substrate;
a conductive bonding pad is arranged on the upper side of the first substrate and communicated with the conductive through hole;
the alignment mark is not provided between an outer edge of the conductive pad and an end surface of the first substrate on an upper side of the first substrate.
3. The assembly of claim 2, wherein:
the sealing layer is a metal bonding layer, and the conductive through hole is aligned with and electrically connected with the bonding layer in the thickness direction of the first substrate.
4. The assembly of claim 2, wherein:
and scribing alignment marks which are arranged on the same layer and spaced apart from the conductive bonding pads are not arranged between the outer edges of the conductive bonding pads and the end face of the first substrate on the upper side of the first substrate.
5. The assembly of any one of claims 1-4, wherein:
the end face of the first substrate does not have a texture formed on the basis of etching.
6. A method of dicing a semiconductor assembly, comprising:
step 1: providing a first substrate, a second substrate, a sealing layer and a MEMS device, wherein the sealing layer is arranged between the lower side of the first substrate and the upper side of the second substrate, the first substrate, the second substrate and the sealing layer define or enclose a containing space, the MEMS device is arranged in the corresponding containing space, and the MEMS device comprises: the sealing layer comprises a first sealing layer arranged on the first substrate and a second sealing layer arranged on the second substrate, and the first sealing layer is suitable for being in sealing connection with the second sealing layer;
and 2, step: removing a predetermined portion of a peripheral region of the first substrate to expose a second sealing layer corresponding to the predetermined portion;
and step 3: and cutting the second sealing layer corresponding to the preset part as an alignment mark.
7. The method of claim 6, wherein:
removing a predetermined portion of the peripheral region of the first substrate includes removing a portion of the first substrate where the outer edge is located.
8. The method of 7, wherein:
to remove the predetermined portion by cutting or etching the first substrate in a direction parallel to a thickness direction of the first substrate.
9. The method of claim 8, wherein:
in step 1, a first sealing layer is not provided on the lower side of the first substrate in a region corresponding to the predetermined portion.
10. The method of 7, wherein:
in step 1, the lower side of a first substrate is a recessed portion at the predetermined portion, the first substrate having a first thickness at a portion corresponding to the recessed portion;
in step 2, a predetermined thickness of the base material is removed from the upper side of the first base to expose the second sealing layer corresponding to the predetermined portion, the predetermined thickness being not less than the first thickness.
11. The method of claim 6, wherein:
a predetermined portion of the peripheral area of the first substrate is spaced apart from the outer edge of the first substrate by a distance in a horizontal direction.
12. The method of claim 11, wherein:
said one distance is not more than 3mm.
13. The method of claim 6, wherein:
the width of the predetermined portion is in the range of 1mm to 10 mm.
14. The method of claim 13, wherein:
the width of the predetermined portion is in the range of 1mm-3.5 mm.
15. A filter comprising a semiconductor assembly according to any of claims 1-5, wherein the MEMS device comprises a resonator.
16. An electronic device comprising a filter according to 15 or a semiconductor component according to any of the claims 1-5.
Although embodiments of the present invention have been shown and described, it would be appreciated by those skilled in the art that changes may be made in these embodiments without departing from the principles and spirit of the invention, the scope of which is defined in the claims and their equivalents.

Claims (16)

1. A semiconductor assembly, comprising:
a first substrate and a second substrate;
a sealing layer disposed between a lower side of the first substrate and an upper side of the second substrate;
at least one of the MEMS devices is configured to,
wherein:
the first substrate, the second substrate and the sealing layer define or enclose at least one accommodating space, and the MEMS device is arranged in the corresponding accommodating space;
the upper side of the first substrate is not provided with alignment marks for scribing.
2. The assembly of claim 1, wherein:
the assembly includes a conductive via through the first substrate;
a conductive bonding pad is arranged on the upper side of the first substrate and communicated with the conductive through hole;
the alignment mark is not provided between an outer edge of the conductive pad and an end surface of the first substrate on an upper side of the first substrate.
3. The assembly of claim 2, wherein:
the sealing layer is a metal bonding layer, and the conductive through hole is aligned with and electrically connected with the bonding layer in the thickness direction of the first substrate.
4. The assembly of claim 2, wherein:
and scribing alignment marks which are arranged on the same layer and spaced apart from the conductive bonding pads are not arranged between the outer edges of the conductive bonding pads and the end face of the first substrate on the upper side of the first substrate.
5. The assembly of any of claims 1-4, wherein:
the end face of the first substrate does not have a texture formed on the basis of etching.
6. A method of dicing a semiconductor assembly, comprising:
step 1: providing a first substrate, a second substrate, a sealing layer and a MEMS device, wherein the sealing layer is arranged between the lower side of the first substrate and the upper side of the second substrate, the first substrate, the second substrate and the sealing layer define or enclose a containing space, and the MEMS device is arranged in the corresponding containing space, wherein: the sealing layer comprises a first sealing layer arranged on the first substrate and a second sealing layer arranged on the second substrate, and the first sealing layer is suitable for being in sealing connection with the second sealing layer;
step 2: removing a predetermined portion of the peripheral region of the first substrate to expose a second sealing layer corresponding to the predetermined portion;
and step 3: and cutting the second sealing layer corresponding to the preset part as an alignment mark.
7. The method of claim 6, wherein:
removing a predetermined portion of the peripheral region of the first substrate includes removing a portion of the first substrate where the outer edge is located.
8. The method of claim 7, wherein:
to remove the predetermined portion by cutting or etching the first substrate in a direction parallel to a thickness direction of the first substrate.
9. The method of claim 8, wherein:
in step 1, a first sealing layer is not provided on the lower side of the first substrate in a region corresponding to the predetermined portion.
10. The method of claim 7, wherein:
in step 1, the lower side of a first substrate is a concave portion at the predetermined portion, and the first substrate has a first thickness at a portion corresponding to the concave portion;
in step 2, a predetermined thickness of the base material is removed from the upper side of the first base to expose the second sealing layer corresponding to the predetermined portion, the predetermined thickness being not less than the first thickness.
11. The method of claim 6, wherein:
a predetermined portion of the peripheral area of the first substrate is spaced apart from an outer edge of the first substrate by a distance in a horizontal direction.
12. The method of claim 11, wherein:
the one distance is not more than 3mm.
13. The method of claim 6, wherein:
the width of the predetermined portion is in the range of 1mm to 10 mm.
14. The method of claim 13, wherein:
the width of the predetermined portion is in the range of 1mm-3.5 mm.
15. A filter comprising a semiconductor assembly according to any of claims 1-5, wherein the MEMS device comprises a resonator.
16. An electronic device comprising a filter according to claim 15 or a semiconductor component according to any of claims 1-5.
CN202110343060.3A 2021-03-30 2021-03-30 Semiconductor assembly and cutting method thereof, filter and electronic equipment Pending CN115140700A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN202110343060.3A CN115140700A (en) 2021-03-30 2021-03-30 Semiconductor assembly and cutting method thereof, filter and electronic equipment
PCT/CN2022/080121 WO2022206331A1 (en) 2021-03-30 2022-03-10 Semiconductor component and dicing method therefor, filter, and electronic device

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Application Number Priority Date Filing Date Title
CN202110343060.3A CN115140700A (en) 2021-03-30 2021-03-30 Semiconductor assembly and cutting method thereof, filter and electronic equipment

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CN115140700A true CN115140700A (en) 2022-10-04

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