CN115148261A

CN115148261A - Memory device

Info

Publication number: CN115148261A
Application number: CN202111433047.3A
Authority: CN
Inventors: 刘纯杰; 吴祖仪
Original assignee: Nuvoton Technology Corp
Current assignee: Nuvoton Technology Corp
Priority date: 2021-03-31
Filing date: 2021-11-29
Publication date: 2022-10-04
Also published as: TW202241006A; TWI756093B

Abstract

The invention provides a memory. A programmable memory array includes a plurality of memory cells coupled to a programming bond pad and a power bond pad. When a first voltage of the programming bonding pad is greater than a second voltage of the power bonding pad, the plurality of memory cells are operated in a programming mode. When the first voltage of the programming bonding pad is less than the second voltage of the power bonding pad, the plurality of memory cells are operated in a normal mode. An ESD protection circuit is used for conducting an ESD current from the power pad to the programming pad when an ESD event occurs. A first path from the power pad to the ESD protection circuit is smaller than a second path from the power pad to the programmable memory array. The invention can realize the prevention of damage from electrostatic discharge pressure.

Description

Memory device

Technical Field

The present invention relates to an electrostatic discharge protection circuit, and more particularly, to an electrostatic discharge protection circuit of a programmable memory.

Background

When the excess charge stored in the electronic insulator finds a path to an object with a different potential (e.g., ground), the sudden and instantaneous flow of current is known as an electrostatic discharge. When electrostatic charges move to an Integrated Circuit (IC), they can act as currents that damage or destroy gate oxides, metals, and junctions. Electrostatic discharge typically occurs when a charged object contacts an integrated circuit, a charged integrated circuit contacts a grounded surface, or a charged machine contacts an integrated circuit.

Electrostatic discharge is a common occurrence during the handling of integrated circuits. Electrostatic charges can accumulate in semiconductor devices of integrated circuits and can cause destructive effects. Electrostatic discharge events (or stresses) can occur during the testing phase of integrated circuit manufacture, when the devices of the integrated circuit are placed on a circuit board, and during the use of the equipment in which the integrated circuit is mounted. Damage to the integrated circuit by electrostatic discharge may partially or sometimes completely halt operation of the integrated circuit.

Disclosure of Invention

The invention provides a memory. The memory includes a power pad, a programming pad, a programmable memory array, and an ESD protection circuit. The programmable memory array includes a plurality of memory cells coupled to the programming bond pads and the power bond pads. When a first voltage of the programming bonding pad is greater than a second voltage of the power bonding pad, the plurality of memory cells are operated in a programming mode. When the first voltage of the programming bonding pad is less than the second voltage of the power bonding pad, the plurality of memory cells are operated in a normal mode. The ESD protection circuit is coupled between the power pad and the programming pad. The ESD protection circuit is used for conducting an ESD current from the power pad to the programming pad when an ESD event occurs. A first path from the power pad to the ESD protection circuit is smaller than a second path from the power pad to the programmable memory array.

Furthermore, the invention provides a memory. The memory includes a power pad, a programming pad, a first ESD protection circuit, and a programmable memory array. The first ESD protection circuit is coupled between the power pad and the programming pad. The programmable memory array includes a plurality of memory cells. Each memory cell includes a P-type transistor having a gate coupled to the power pad and the first esd protection circuit and a source coupled to the program pad. The memory cells are operated in a programming mode when a first voltage of the programming pad is greater than a second voltage of the power pad, and in a normal mode when the first voltage of the programming pad is less than the second voltage of the power pad. A first path from the power pad to the first ESD protection circuit is smaller than a second path from the power pad to the programmable memory array, and the first path partially overlaps the second path.

Drawings

FIG. 1 shows an integrated circuit according to some embodiments of the invention;

FIG. 2A illustrates an ESD protection circuit implemented with diodes according to some embodiments of the present invention;

FIG. 2B illustrates an ESD protection circuit implemented with diodes according to some embodiments of the present invention;

FIG. 2C illustrates an ESD protection circuit implemented with bipolar transistors according to some embodiments of the present invention;

FIG. 2D is a diagram illustrating an ESD protection circuit implemented with bipolar transistors according to some embodiments of the present invention;

FIG. 2E is a diagram illustrating an ESD protection circuit implemented using MOS transistors according to some embodiments of the invention;

FIG. 2F illustrates an ESD protection circuit implemented using MOS transistors according to some embodiments of the invention;

FIG. 2G is a diagram illustrating an ESD protection circuit implemented using MOS transistors according to some embodiments of the invention;

FIG. 3 shows a memory according to some embodiments of the inventions;

FIG. 4 shows a memory according to some embodiments of the inventions.

Reference numerals:

10A, 10B, 10C: a memory;

15: a memory cell;

30: a power bonding pad;

40: a programming bond pad;

50: a ground bonding pad;

70. 70a, 70b, 70c, 70d, 70e, 70f, 70g, 80a, 80b, 80c, 80d, 80e, 80f, 80b: an electrostatic discharge protection circuit;

72c, 72e: a bias unit;

100: an integrated circuit;

110: a substrate;

120. 120a, 120b, 120c: a pin;

125a, 125b, 125c: a metal wire;

130a, 130b: an input/output area;

140: a control circuit;

145: a device region;

150: a programmable memory array;

BJT1, BJT2: a bipolar transistor;

d1, D2, D3, D4: a diode;

m1, M2, M3, M4: a transistor;

MP1, MP2: a P-type transistor;

path1: a first path;

and (4) Path2: a second path;

VDD: a power source;

VPP: a programming signal;

VSS: a ground signal or ground terminal.

Detailed Description

In order to make the aforementioned and other objects, features and advantages of the present invention comprehensible, preferred embodiments accompanied with figures are described in detail below:

as technology advances, electrostatic discharge resistance becomes increasingly important for the fabrication of integrated circuits. However, semiconductor devices scaled down by semiconductor processing techniques and including shallower junction depths and thin gate oxides are less tolerant of electrostatic discharge events. Therefore, an esd protection circuit must be provided at the input/output bond pad (pad) of the ic to avoid damage from esd stress.

Generally, device damage due to an esd event is determined by the device's ability to dissipate discharge energy or to withstand current levels. This is referred to as the electrostatic discharge sensitivity or electrostatic discharge sensitivity of the device. There are three main modes of an esd event, namely, a Human Body Model (HBM), a machine discharge model (MM), and a device charging model (CDM). In these modes of electrostatic discharge, electrostatic charges can be transferred from the body, charged materials, or internal devices of the integrated circuit to the electrostatic discharge sensitive devices, causing damage to the devices within the integrated circuit.

Fig. 1 illustrates an integrated circuit 100 according to some embodiments of the invention. The integrated circuit 100 includes a substrate (or baseboard) 110, pins (or pins) 120, and a memory (or die) 10A disposed on the substrate 110. Memory 10A includes an input/output (I/O) area 130A, control circuitry 140, and a programmable memory array 150.

The i/o area 130a includes a power pad 30, a program pad 40, and a ground pad 50, and each pad is connected to a corresponding pin 120 through a respective metal line. For example, the power pad 30 is connected to the pin 120b via the metal line 125b for providing the power signal VDD to the control circuit 140 and the programmable memory array 150. Furthermore, the ground pad 50 is connected to the pin 120c via a metal line 125c for providing a ground signal (or ground) VSS to the control circuit 140 and the programmable memory array 150. In addition, the program bonding pad 40 is connected to the pin 120a through a metal line 125a for providing a program signal VPP to the control circuit 140 and the programmable memory array 150. In the top view of the memory 10A of fig. 1, the program bonding pads 40 and the power bonding pads 30 are disposed on the top of the programmable memory array 150 and the control circuit 140, respectively, and the ground bonding pads 50 are disposed on the left side of the control circuit 140. For simplicity of illustration, fig. 1 only describes the esd protection mechanism associated with the programming signal VPP.

Programmable memory array 150 is formed from a plurality of memory cells 15. Each memory cell 15 is a programmable memory cell. In some embodiments, the memory unit 15 may be a flash memory. In some embodiments, the memory cell 15 may be a one-time program (OTP) memory cell. When the voltage level of the programming signal VPP from the pin 120a is greater than the voltage level of the power supply VDD (i.e., VPP > VDD), the memory cell 15 operates in a programming mode, and a user can program the programmable memory array 150 through the control circuit 140. Conversely, when the voltage level of the programming signal VPP (e.g., pin 120a is floating) is lower than the voltage level of the power supply VDD (i.e., VPP < VDD), the memory cell 15 operates in the normal mode, and the control circuit 140 can read and/or write to the programmable memory array 150 according to the application programs of various products.

Compared to the conventional memory, the i/o region 130A of the memory 10A further includes an esd protection circuit 70 disposed between the power pad 30 and the programming pad 40 for providing esd protection to the memory cell 15. For example, the memory cell 15 includes a P-type transistor MP1. The source and the base (bulk) of the P-type transistor MP1 are connected to the program pad 40, and the gate of the P-type transistor MP1 is connected to the power pad 30. Therefore, when the CDM mode ESD event occurs, the ESD current flows from the inside of the device through the power pad 30 to the programming pad 40 through the ESD protection circuit 70, thereby preventing the ESD current from flowing to the memory cell 15 and breaking down the gate of the P-type transistor MP1. It is noted that the first Path1 from the power pad 30 to the esd protection circuit 70 is smaller (shorter) than the second Path2 from the power pad 30 to the memory cell 15 of the programmable memory array 150. In addition, the first Path1 does not overlap the second Path2.

Fig. 2A illustrates an esd protection circuit 70a implemented using diodes according to some embodiments of the invention. The esd protection circuit 70a includes diodes D1 and D2 for providing CDM mode bi-directional esd protection between

bond pads

30 and 40. The anode of the diode D1 is coupled to the power pad 30, and the cathode of the diode D1 is coupled to the cathode of the diode D2. In addition, the anode of the diode D2 is coupled to the programming pad 40. In some embodiments, diode D1 is disposed proximate to power pad 30, and diode D2 is disposed proximate to programming pad 40.

Fig. 2B shows an esd protection circuit 70B implemented with diodes according to some embodiments of the invention. The esd protection circuit 70b includes diodes D3 and D4. Diodes D3 and D4 of fig. 2B are Zener (Zener) diodes having higher reverse breakdown voltages than diodes D1 and D2 of fig. 2A. In addition, the arrangement positions of the diodes D3 and D4 can be similar to the diodes D1 and D2 of fig. 2A.

Fig. 2C shows an esd protection circuit 70C implemented using bipolar transistors according to some embodiments of the invention. The esd protection circuit 70c includes a bipolar transistor BJT1 and a bias unit 72c. The bipolar transistor BJT1 is a PNP transistor. The emitter of the bipolar transistor BJT1 is coupled to the power pad 30, and the base thereof is coupled to the bias unit 72c. In addition, the collector of the bipolar transistor BJT1 is coupled to the programming pad 40. When an esd event occurs, the bias unit 72c controls the bipolar transistor BJT1 to be turned on, so that an esd current flows from the power pad 30 to the programming pad 40 through the esd protection circuit 70c.

Fig. 2D illustrates an esd protection circuit 70D implemented with bipolar transistors according to some embodiments of the invention. The esd protection circuit 70d includes a bipolar transistor BJT2. The bipolar transistor BJT2 is an NPN transistor. The bipolar transistor BJT2 has a collector coupled to the power pad 30, a base coupled to the ground VSS and an emitter coupled to the programming pad 40. When an esd event occurs, an esd current flows from the power pad 30 to the programming pad 40 through the BJT2.

Fig. 2E illustrates an esd protection circuit 70E implemented with MOS transistors according to some embodiments of the invention. The esd protection circuit 70e includes a transistor M1 and a bias unit 72e. In this embodiment, the transistor M1 is a P-type transistor. The source of the transistor M1 is coupled to the power pad 30, the gate is coupled to the bias cell 72e, and the drain is coupled to the program pad 40. In addition, the base of the transistor M1 is coupled to the bias unit 72e. When an ESD event occurs, the biasing unit 72e controls the transistor M1 to be turned on, so that an electrostatic current flows from the power pad 30 to the program pad 40 through the transistor M1.

Fig. 2F illustrates an esd protection circuit 70F implemented using MOS transistors according to some embodiments of the invention. The electrostatic discharge protection circuit 70f includes a transistor M2. In this embodiment, the transistor M2 is an N-type transistor. The drain of the transistor M2 is coupled to the power pad 30 and the source is coupled to the programming pad 40. In addition, the base and the gate of the transistor M2 are both coupled to the ground terminal VSS. When an ESD event occurs, an ESD current flows from the power pad 30 to the program pad 40 through the transistor M2.

Fig. 2G shows an esd protection circuit 70G implemented using MOS transistors according to some embodiments of the invention. The electrostatic discharge protection circuit 70g includes transistors M3 and M4. In this embodiment, transistors M3 and M4 are P-type transistors. The source, gate and base of the transistor M3 are coupled to the power pad 30, and the drain is coupled to the transistor M4. In addition, the drain, gate and base of the transistor M4 are coupled to the program pad 40, and the source is coupled to the transistor M3. In this embodiment, the transistors M3 and M4 are connected as diodes, as shown in FIG. 2A. In addition, the placement of the transistors M3 and M4 can be similar to the diodes D1 and D2 of fig. 2A.

FIG. 3 shows a memory 10B according to some embodiments of the invention. Memory 10B includes input/output region 130B, control circuitry 140, and programmable memory array 150. The configuration of the memory 10B is similar to the memory 10A of fig. 1. In comparison with the memory 10A of fig. 1, the device region 145 of the memory 10B having the control circuit 140 and the programmable memory array 150 is surrounded by the i/o region 130B. In addition, the power pads 30 are disposed on the left side of the control circuit 140, and the ground pads 50 are disposed on the bottom of the control circuit 140 and the programmable memory array 150. In the embodiment of the present invention, the locations of the power pads 30, the programming pads 40, the ground pads 50, the control circuit 140, and the programmable memory array 150 are only examples, and are not intended to limit the present invention. The power pads 30, the program pads 40, the ground pads 50, the control circuit 140, and the programmable memory array 150 may be arranged at suitable locations according to the application.

As previously described, the programmable memory array 150 is formed from a plurality of memory cells 15. Each memory cell 15 is a programmable memory cell. In some embodiments, the memory cells 15 may be flash memory or one-time-programmable memory cells. When the voltage level of the programming signal VPP from the programming bonding pad 40 is greater than the voltage level of the power supply VDD from the power bonding pad 30 (i.e., VPP > VDD), the memory cell 15 operates in a programming mode. On the other hand, when the voltage level of the program signal VPP is less than the voltage level of the power supply VDD (i.e., VPP < VDD), the memory cell 15 may operate in the normal mode.

In fig. 3, the esd protection circuit 70 is disposed in the i/o region 130b and coupled between the power pad 30 and the programming pad 40 for providing bi-directional esd protection to the power pad 30 and the programming pad 40. In addition, the esd protection circuit 70 may be implemented using a diode, a bipolar transistor and/or a MOS transistor, as shown in fig. 2A, 2B, 2C, 2D, 2E, 2F and 2G. In some embodiments, a plurality of esd protection circuits 70 connected in parallel may be disposed between the power pad 30 and the programming pad 40. For example, the esd protection circuit 70 of the first cell is disposed between the power pad 30 and the program pad 40 and close to the power pad 30, i.e., the distance between the esd protection circuit 70 of the first cell and the power pad 30 is smaller than the distance between the esd protection circuit 70 of the first cell and the program pad 40. In addition, the second unit of the esd protection circuit 70 is disposed between the power pad 30 and the programming pad 40 and close to the programming pad 40, i.e. the distance between the second unit of the esd protection circuit 70 and the programming pad 40 is smaller than the distance between the first unit of the esd protection circuit 70 and the power pad 30.

As described previously, the first Path1 from the power bonding pad 30 to the electrostatic discharge protection circuit 70 is smaller (shorter) than the second Path2 from the power bonding pad 30 to the memory cell 15. In addition, the first Path1 does not overlap the second Path2. When the CDM mode ESD event occurs, the ESD protection circuit 70 can prevent the ESD current from damaging the memory cell 15. Similar to the P-type transistor MP1 of the memory cell 15, some devices of the control circuit 140 are coupled to the programming pad 40 and the power pad 30, such as the P-type transistor MP2. Therefore, the ESD protection circuit 70 can also prevent the control circuit 140 from being damaged by the ESD current.

In the i/o area 130b, the esd protection circuit 80a is coupled and disposed between the power pad 30 and the ground pad 50. The esd protection circuit 80b is coupled and disposed between the program bonding pad 40 and the ground bonding pad 50. When an esd event occurs in the HBM mode, the esd protection circuits 80a and 80B can protect the power pad 30, the program pad 40, and the ground pad 50 from esd current damage to the internal circuits of the memory 10B. In some embodiments, the ESD protection circuits 80a and 80B may include clamp (clamp) units to protect the internal circuits of the memory 10B. Generally, the clamping unit can be safely discharged to the ground pad 50 by limiting the voltage and allowing the high current of the electrostatic discharge.

FIG. 4 shows a memory 10C according to some embodiments of the invention. The configuration of the memory 10C is similar to the memory 10B of fig. 3. Compared to the memory 10B of fig. 3, the esd protection circuit 70 of the memory 10C is disposed in the device region 145. Thus, compared to the conventional memory, no additional area (as shown by reference numeral 135) is required for disposing the ESD protection circuit 70. In addition, the first Path1 from the power pad 30 to the esd protection circuit 70 partially overlaps the second Path2 from the power pad 30 to the memory cell 15 of the programmable memory array 150, as shown by reference numeral 410. In other words, the gate of the transistor MP1 is directly coupled to the ESD protection circuit 70 without passing through the power pad 30. Furthermore, when the memory 10C is integrated as an integrated circuit (ic) module with an IP (internet protocol) function, the ic does not need to provide an esd protection circuit to protect the memory cell 15.

In the embodiment of the invention, by disposing the esd protection circuit 70 between the power pad 30 and the programming pad 40, the memory cell 15 that needs to be programmed by the programming signal VPP can be prevented from being damaged by the electrostatic current, so that the reliability of the memory can be improved. In some embodiments, the esd protection circuit 70 may be disposed in a device region (e.g., device region 145) to improve protection of the device region from esd events.

Although the present invention has been described with reference to the preferred embodiments, it should be understood that various changes and modifications can be made therein by those skilled in the art without departing from the spirit and scope of the invention as defined by the appended claims.

Claims

1. A memory, comprising:

a power bonding pad;

a programming bond pad;

a programmable memory array including a plurality of memory cells coupled to the programming bond pad and the power bond pad, wherein the plurality of memory cells operate in a programming mode when a first voltage of the programming bond pad is greater than a second voltage of the power bond pad, and the plurality of memory cells operate in a normal mode when the first voltage of the programming bond pad is less than the second voltage of the power bond pad; and

an ESD protection circuit coupled between the power pad and the programming pad for conducting an ESD current from the power pad to the programming pad when an ESD event occurs;

wherein a first path from the power pad to the ESD protection circuit is smaller than a second path from the power pad to the programmable memory array.

2. The memory of claim 1, wherein each of the memory cells comprises:

a P-type transistor having a gate coupled to the power pad and a source coupled to the program pad.

3. The memory of claim 1, wherein the esd protection circuit comprises:

a first diode having a first anode and a first cathode coupled to the power pad; and

a second diode having a second anode coupled to the programming bond pad and a second cathode coupled to the first cathode.

4. The memory of claim 1, wherein the esd protection circuit comprises a first cell and a second cell, wherein the first cell and the second cell are connected in parallel between the programming pad and the power pad.

5. The memory of claim 4, wherein a distance between the first cell and the programming pad is less than a distance between the first cell and the power pad, and a distance between the second cell and the programming pad is greater than a distance between the second cell and the power pad.

6. A memory, comprising:

a power bonding pad;

a programming bond pad;

a first ESD protection circuit coupled between the power pad and the programming pad; and

a programmable memory array comprising a plurality of memory cells, wherein each of the memory cells comprises:

a P-type transistor having a gate coupled to the power pad and the first ESD protection circuit and a source coupled to the program pad;

wherein the plurality of memory cells are operated in a programming mode when a first voltage of the programming pad is greater than a second voltage of the power pad, and in a normal mode when the first voltage of the programming pad is less than the second voltage of the power pad;

wherein a first path from the power pad to the first ESD protection circuit is smaller than a second path from the power pad to the programmable memory array, and the first path partially overlaps the second path.

7. The memory of claim 6, wherein the first ESD protection circuit comprises:

a second diode having a second anode coupled to the programming pad and a second cathode coupled to the first cathode.

8. The memory of claim 6, wherein the first ESD protection circuit comprises a first cell and a second cell connected in parallel between the program pad and the power pad, wherein a distance between the first cell and the program pad is smaller than a distance between the first cell and the power pad, and a distance between the second cell and the program pad is larger than a distance between the second cell and the power pad.

9. The memory of claim 6, further comprising:

a ground pad coupled to the programmable memory array;

a second ESD protection circuit coupled between the power pad and the ground pad; and

a third ESD protection circuit coupled between the ground pad and the program pad.

10. The memory of claim 6, wherein the first ESD protection circuit conducts an ESD current from the programmable memory array to the program pad through the power pad when an ESD event occurs.