CN115100997A - Shifting register and driving method thereof, grid driving circuit and display device - Google Patents
Shifting register and driving method thereof, grid driving circuit and display device Download PDFInfo
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- CN115100997A CN115100997A CN202210937354.3A CN202210937354A CN115100997A CN 115100997 A CN115100997 A CN 115100997A CN 202210937354 A CN202210937354 A CN 202210937354A CN 115100997 A CN115100997 A CN 115100997A
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- 239000003990 capacitor Substances 0.000 claims description 8
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- 238000001514 detection method Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000004973 liquid crystal related substance Substances 0.000 description 2
- 230000003247 decreasing effect Effects 0.000 description 1
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- 238000003384 imaging method Methods 0.000 description 1
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
- G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
- G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
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Abstract
The application provides a shift register, a driving method thereof, a grid driving circuit and a display device, and relates to the technical field of display. The shift register includes: the charging module is electrically connected with a touch signal line and a first node and is configured to keep the potential of the first node under the control of a touch signal of the touch signal line in a non-display stage; an input module; a first reset module; an output module; a pull-down control module; a pull-up control module; and a pull-down module.
Description
Technical Field
The present application relates to the field of display technologies, and in particular, to a shift register, a driving method thereof, a gate driving circuit, and a display device.
Background
In actual use of a GOA (Gate Driver On Array, Array substrate row Driver) circuit, since a display device needs to be used with other functions, such as a touch function, a display signal in a GOA circuit signal needs to be suspended to cooperate with other functions.
However, the current display device is prone to the cross striation phenomenon, resulting in poor user experience.
Disclosure of Invention
The embodiment of the application provides a shift register, a driving method thereof, a gate driving circuit and a display device.
In order to achieve the above purpose, the embodiment of the present application adopts the following technical solutions:
in one aspect, there is provided a shift register, including:
the charging module is electrically connected with a touch signal line and a first node and is configured to keep the potential of the first node under the control of a touch signal of the touch signal line in a non-display stage;
an input module electrically connected to an input signal line and the first node, and configured to write an input signal of the input signal line into the first node under control of the input signal line in a display stage and the non-display stage;
a first reset module electrically connected to a first reset signal line, a power supply signal line, and the first node, and configured to write a power supply signal of the power supply signal line to the first node under control of a reset signal of the first reset signal line in the display phase;
an output module electrically connected to a clock signal line, the first node, and an output signal line, and configured to write a clock signal of the clock signal line into the output signal line under control of a voltage of the first node in the display stage and the non-display stage;
a pull-down control module electrically connected to the first node, a second node and the power signal line, and configured to write the power signal of the power signal line into the second node under control of a voltage of the first node in the display phase;
a pull-up control module electrically connected to a control signal line and the second node, and configured to write the control signal of the control signal line into the second node under control of a control signal of the control signal line in the display stage;
a pull-down module electrically connected to the power signal line, the second node, and the output signal line, and configured to write the power signal of the power signal line to the output signal line under control of a voltage of the second node in the display phase.
Optionally, the shift register further includes:
a second reset module electrically connected to a second reset signal line, the first node, the power signal line, and the output signal line, and configured to write the power signal of the power signal line to the first node and the output signal line, respectively, under control of a reset signal of the second reset signal line.
Optionally, the charging module includes a twelfth transistor and a thirteenth transistor;
a control electrode and a first electrode of the twelfth transistor are electrically connected with the touch signal line, and a second electrode of the twelfth transistor is electrically connected with a first electrode of the thirteenth transistor;
a control electrode and a second electrode of the thirteenth transistor are both electrically connected to the first node.
Optionally, the charging module includes a twelfth transistor and a thirteenth transistor;
a control electrode of the twelfth transistor is electrically connected with a second electrode of the thirteenth transistor, a first electrode of the twelfth transistor is electrically connected with the touch signal line, and a second electrode of the twelfth transistor is electrically connected with the first node;
the control electrode of the thirteenth transistor is electrically connected with the first node, and the first electrode is electrically connected with the touch signal line.
Optionally, the input module includes a first transistor;
and the control electrode and the first electrode of the first transistor are electrically connected with the input signal line, and the second electrode of the first transistor is electrically connected with the first node.
Optionally, the first reset module includes a second transistor;
a control electrode of the second transistor is electrically connected to the first reset signal line, a first electrode is electrically connected to the power signal line, and a second electrode is electrically connected to the first node.
Optionally, the output module includes a third transistor and a capacitor;
a control electrode of the third transistor is electrically connected to the first node, a first electrode of the third transistor is electrically connected to the clock signal line, and a second electrode of the third transistor is electrically connected to the output signal line;
the first end of the capacitor is electrically connected with the first node, and the second end of the capacitor is electrically connected with the second pole of the third transistor.
Optionally, the pull-down control module includes a sixth transistor and an eighth transistor;
a control electrode of the sixth transistor is electrically connected to the first node, a first electrode is electrically connected to the power signal line, and a second electrode is electrically connected to the second node;
a control electrode of the eighth transistor is electrically connected to the first node, the first electrode is electrically connected to the power signal line, and the second electrode is electrically connected to the second node.
Optionally, the pull-up control module includes a fifth transistor and a ninth transistor;
a control electrode of the fifth transistor is electrically connected to a second electrode of the ninth transistor, a first electrode of the fifth transistor is electrically connected to the control signal line, and a second electrode of the fifth transistor is electrically connected to the second node;
and the control electrode and the first electrode of the ninth transistor are both electrically connected with the control signal line.
Optionally, the pull-down module includes a tenth transistor and an eleventh transistor;
a control electrode of the tenth transistor is electrically connected to the second node, a first electrode is electrically connected to the power signal line, and a second electrode is electrically connected to the first node;
a control electrode of the eleventh transistor is electrically connected to the second node, a first electrode is electrically connected to the power signal line, and a second electrode is electrically connected to the output signal line.
Optionally, the second reset module includes a fourth transistor and a seventh transistor;
a control electrode of the fourth transistor is electrically connected to the second reset signal line, a first electrode is electrically connected to the power signal line, and a second electrode is electrically connected to the first node;
a control electrode of the seventh transistor is electrically connected to the second reset signal line, a first electrode is electrically connected to the power signal line, and a second electrode is electrically connected to the output signal line.
In another aspect, a gate driving circuit is provided, which includes a plurality of cascaded shift registers.
In another aspect, a display device is provided, which includes the gate driving circuit.
In another aspect, a driving method is provided for driving the shift register;
the method comprises the following steps:
writing a touch signal into the touch signal line and writing an input signal into the input signal line in a non-display stage; in the display stage, an input signal is written into an input signal line, a control signal is written into a control signal line, a clock signal is written into a clock signal line, a reset signal is written into a first reset signal line, and a power supply signal is written into a power supply signal line.
An embodiment of the present application provides a shift register, including: the charging module is electrically connected with the touch signal line and the first node and is configured to keep the potential of the first node under the control of the touch signal line in a non-display stage; an input module electrically connected to the input signal line and the first node, and configured to write an input signal of the input signal line into the first node under control of the input signal line in a display stage and a non-display stage; a first reset module electrically connected to the first reset signal line, the power signal line and the first node, and configured to write a power signal of the power signal line into the first node under control of a reset signal of the first reset signal line in a display phase; an output module electrically connected to the clock signal line, the first node and the output signal line, and configured to write a clock signal of the clock signal line into the output signal line under control of a voltage of the first node in a display stage and a non-display stage; a pull-down control module electrically connected to the first node, the second node and the power signal line, and configured to write a power signal of the power signal line into the second node under control of a voltage of the first node in a display stage; a pull-up control module electrically connected to the control signal line and the second node, and configured to write the control signal of the control signal line into the second node under control of the control signal line in a display stage; and a pull-down module electrically connected to the power signal line, the second node and the output signal line, and configured to write a power signal of the power signal line into the output signal line under control of a voltage of the second node in a display stage. Like this, the charging module can charge first node PU at first-order potential under the control of the touch signal of touch signal line TH at the non-display stage, specifically during the touch stage, so that first node PU does not leak electricity, thereby can keep the potential of first node, make output voltage unlikely to be too low, the pixel charging of display device is as far as possible not influenced, and then reduce or even avoid the display device to appear the horizontal stripe under LH display mode, improve user experience by a wide margin.
The above description is only an overview of the technical solutions of the present application, and the present application may be implemented in accordance with the content of the description so as to make the technical means of the present application more clearly understood, and the detailed description of the present application will be given below in order to make the above and other objects, features, and advantages of the present application more clearly understood.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings used in the embodiments or the prior art descriptions will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.
Fig. 1 is a schematic diagram of a shift register according to an embodiment of the present disclosure;
FIG. 2 is a diagram of another shift register according to an embodiment of the present disclosure;
FIG. 3 is a schematic diagram of a cascade of two shift registers shown in FIG. 1 according to an embodiment of the present disclosure;
fig. 4 is a driving timing diagram of a shift register according to an embodiment of the present application;
fig. 5 to 8 are schematic views illustrating a driving principle of the shift register of fig. 1 and 2 at the driving timing of fig. 4.
Detailed Description
The technical solutions in the embodiments of the present application will be described clearly and completely with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only some embodiments of the present application, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the embodiments of the present application, the words "first", "second", "third", "fourth", "fifth", "sixth", "seventh", "eighth", "ninth", "tenth", "eleventh", "twelfth", "thirteenth", etc. are used to distinguish the same or similar items with substantially the same function and effect, and are used only for clearly describing technical solutions of the embodiments of the present application, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features.
In the embodiments of the present application, the gate of the transistor is referred to as a control electrode, and one of the source and the drain is referred to as a first electrode and the other is referred to as a second electrode. In the embodiments of the present application, the first electrodes of all the transistors are referred to as drains, and the second electrodes are referred to as sources.
In embodiments of the present application, the term "electrically connected" may mean that two components are directly electrically connected, or that two components are electrically connected via one or more other components.
An embodiment of the present application provides a shift register, as shown in fig. 1 and fig. 2, the shift register includes:
the charging module 1 is electrically connected to the touch signal line TH and the first node PU, and configured to maintain a potential of the first node PU under control of a touch signal of the touch signal line TH in a non-display stage.
And an Input module 2 electrically connected to the Input signal line Input and the first node PU, and configured to write an Input signal of the Input signal line Input into the first node PU in the display stage and the non-display stage under control of an Input signal of the Input signal line Input.
The first Reset module 3 is electrically connected to the first Reset signal line Reset, the power signal line VGL, and the first node PU, and configured to write the power signal of the power signal line VGL into the first node PU under the control of the Reset signal of the first Reset signal line Reset in the display phase.
And the Output module 4 is electrically connected with the clock signal line CLK, the first node PU and the Output signal line Output, and is configured to write the clock signal of the clock signal line CLK into the Output signal line Output under the control of the voltage of the first node PU at the display stage and the non-display stage.
And a pull-down control module 5 electrically connected to the first node PU, the second node PD and the power signal line VGL, and configured to write a power signal of the power signal line VGL into the second node PD under the control of the voltage of the first node PU during the display period.
And a pull-up control module 6 electrically connected to the control signal line GCH and the second node PD, and configured to write the control signal of the control signal line GCH into the second node PD under the control of the control signal line GCH in the display stage.
The pull-down module 7 is electrically connected to the power signal line VGL, the second node PD, and the Output signal line Output, and is configured to write the power signal of the power signal line VGL into the Output signal line Output under the control of the voltage of the second node in the display stage.
It should be noted that specific circuit structures of the charging module, the input module, the first reset module, the output module, the pull-down control module, the pull-up control module, and the pull-down module are not limited, as long as the corresponding functions are satisfied.
The first node and the second node are defined only for convenience of describing the circuit configuration, and the first node and the second node are not an actual circuit unit.
The 8CLK GOA model in the related art is taken as an example for explanation. In the 8CLK GOA circuit, the first nodes PU of 4 GOA columns are all at a first-order potential, and the clock signal line CLK is input at a low level during the touch phase. Although it is desired to maintain the potential of the first node PU during the touch phase, the voltage of the first node PU may be decreased due to leakage of the first node PU. When the touch stage is finished, the clock signal line CLK inputs a high level, but the second-order voltage rise of the first node PU of the 4 rows of GOAs is insufficient relative to other rows, so that the voltage Output by the Output signal line Output of the 4 rows is low, the charging of the pixels corresponding to the 4 rows is affected, and the display device has horizontal stripes.
In order to solve the above problem, in the shift register provided in the embodiment of the present application, the charging module can charge the first node PU at the first-order potential under the control of the touch signal line TH in the non-display stage, specifically, in the touch stage, so that the first node PU does not leak electricity, and the potential of the first node can be maintained, so that the output voltage is not too low, the pixel charging of the display device is not affected as much as possible, and then horizontal stripes when the display device is in the LH display mode are reduced or even avoided, thereby greatly improving the user experience.
It should be noted that, the display time can be dispersed and inserted into the touch scanning time by using the LH division method, that is, the display stage and the touch stage are performed alternately within a period of time. In the display stage, the input module, the first reset module, the output module, the pull-down control module, the pull-up control module and the pull-down module are all in an open state, and the touch detection module is in a closed state, so that display is performed but touch operation is not performed. In the touch control stage, the first reset module, the output module, the pull-down control module, the pull-up control module and the pull-down module are all in a closed state, and the touch control detection module and the input module are all in an open state, so that touch control operation is performed without display.
The LH segmentation mode can support real-time 120Hz touch scanning.
Optionally, referring to fig. 1 and 2, the shift register further includes: the second reset module 8 is electrically connected to the second reset signal line STV0, the first node PU, the power supply signal line VGL, and the Output signal line Output, and configured to write the power supply signal of the power supply signal line VGL into the first node PU and the Output signal line Output, respectively, under the control of a reset signal of the second reset signal line STV 0.
Alternatively, as shown in fig. 1, the charging module 1 includes a twelfth transistor T12 and a thirteenth transistor T13; a control electrode and a first electrode of the twelfth transistor T12 are both electrically connected to the touch signal line TH, and a second electrode is electrically connected to a first electrode of the thirteenth transistor T13; a control electrode and a second electrode of the thirteenth transistor T13 are both electrically connected to the first node PU.
Alternatively, referring to fig. 2, the charging module 1 includes a twelfth transistor T12 and a thirteenth transistor T13; a control electrode of the twelfth transistor T12 is electrically connected to the second electrode of the thirteenth transistor T13, the first electrode is electrically connected to the touch signal line TH, and the second electrode is electrically connected to the first node PU; a control electrode of the thirteenth transistor T13 is electrically connected to the first node PU, and the first electrode is electrically connected to the touch signal line TH.
Alternatively, referring to fig. 1 and 2, the input block 2 includes a first transistor T1;
the control electrode and the first electrode of the first transistor T1 are both electrically connected to the Input signal line Input, and the second electrode is electrically connected to the first node PU.
Alternatively, referring to fig. 1 and 2, the first reset module 3 includes a second transistor T2; a control electrode of the second transistor T2 is electrically connected to the first Reset signal line Reset, a first electrode is electrically connected to the power supply signal line VGL, and a second electrode is electrically connected to the first node PU.
Alternatively, referring to fig. 1 and 2, the output module 4 includes a third transistor T3 and a capacitor C; a control electrode of the third transistor T3 is electrically connected to the first node PU, the first electrode is electrically connected to the clock signal line CLK, and the second electrode is electrically connected to the Output signal line Output; the first terminal of the capacitor C is electrically connected to the first node PU, and the second terminal is electrically connected to the second pole of the third transistor T3.
Alternatively, referring to fig. 1 and 2, the pull-down control module 5 includes a sixth transistor T6 and an eighth transistor T8; a control electrode of the sixth transistor T6 is electrically connected to the first node PU, the first electrode is electrically connected to the power supply signal line VGL, and the second electrode is electrically connected to the second node PD; the eighth transistor T8 has a control electrode electrically connected to the first node PU, a first electrode electrically connected to the power supply signal line VGL, and a second electrode electrically connected to the second node PD.
Alternatively, referring to fig. 1 and 2, the pull-up control module 6 includes a fifth transistor T5 and a ninth transistor T9; a control electrode of the fifth transistor T5 is electrically connected to the second pole of the ninth transistor T9, the first pole is electrically connected to the control signal line GCH, and the second pole is electrically connected to the second node PD; a control electrode and a first electrode of the ninth transistor T9 are both electrically connected to the control signal line GCH.
Alternatively, referring to fig. 1 and 2, the pull-down module 7 includes a tenth transistor T10 and an eleventh transistor T11; a control electrode of the tenth transistor T10 is electrically connected to the second node PD, a first electrode is electrically connected to the power supply signal line VGL, and a second electrode is electrically connected to the first node PU; a control electrode of the eleventh transistor T11 is electrically connected to the second node PD, a first electrode is electrically connected to the power supply signal line VGL, and a second electrode is electrically connected to the Output signal line Output.
Alternatively, referring to fig. 1 and 2, the second reset module 8 includes a fourth transistor T4 and a seventh transistor T7; a control electrode of the fourth transistor T4 is electrically connected to the second reset signal line STV0, the first electrode is electrically connected to the power supply signal line VGL, and the second electrode is electrically connected to the first node PU; the control electrode of the seventh transistor T7 is electrically connected to the second reset signal line STV0, the first electrode is electrically connected to the power supply signal line VGL, and the second electrode is electrically connected to the Output signal line Output.
In order to make the manufacturing process uniform and facilitate a driving method of a subsequent circuit to be simpler, the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, the ninth transistor, the tenth transistor, the eleventh transistor, the twelfth transistor and the thirteenth transistor are all N-type transistors. Of course, all the transistors may be P-type transistors, and the design principle of the transistors in the case of P-type transistors is similar to that of the present application, and also falls within the protection scope of the present application.
The type of the transistor is not limited, and the transistor may be a thin film transistor, which may be a low temperature polysilicon thin film transistor, an oxide thin film transistor, or the like.
The embodiment of the application also provides a gate driving circuit, which comprises a plurality of cascaded shift registers.
The specific number of the cascaded shift registers is not limited, and for example, the gate driving circuit may include two cascaded shift registers as shown in fig. 3, and of course, may also include other numbers of cascaded shift registers, which is based on the practical application.
The gate driver circuit including two cascaded shift registers will be described as an example.
Referring to fig. 3, the Output signal line Output of the nth row shift register is electrically connected to the Input signal line Input of the N +2 th row shift register, that is, the Output signal of the Output signal line Output of the nth row shift register can be used as the Input signal of the N +2 th row shift register; the Output signal line Output of the N +2 th row shift register is electrically connected to the first Reset signal line Reset of the nth row shift register, that is, the Output signal of the Output signal line Output of the N +2 th row shift register can be used as the Reset signal of the nth row shift register.
In the gate driving circuit provided in the embodiment of the application, the charging module of the shift register can charge the first node PU at the first-order potential under the control of the touch signal line TH in the non-display stage, specifically, in the touch stage, so that the first node PU does not leak electricity, the potential of the first node can be maintained, the output voltage is not too low, the pixel charging of the display device is not affected as much as possible, horizontal stripes when the display device is in the LH display mode are reduced or even avoided, and user experience is greatly improved.
An embodiment of the present application further provides a display device including the gate driving circuit.
The display device may be a display device having a touch function, or may also be a display device having a folding or rolling function, or may also be a display device having both a touch function and a folding function, which is not limited herein. The display device may be a flexible display device (also referred to as a flexible screen) or a rigid display device (i.e., a display screen that cannot be bent), which is not limited herein.
The Display device may be an OLED Display device, a Micro LED Display device, or a Mini LED Display device, and may also be an LCD (Liquid Crystal Display) Display device, for example: ADS (Advanced Super Dimension Switch) type liquid crystal display device.
The display device can be any product or component with a display function, such as a television, a digital camera, a mobile phone, a tablet computer and the like; the display device can also be applied to the fields of identity recognition, medical instruments and the like, and products which are popularized or have good popularization prospects comprise security identity authentication, intelligent door locks, medical image acquisition and the like. The display device has the advantages of extremely low probability of cross-striation risk, low cost, good display effect, long service life, high stability, high contrast, good imaging quality, high product quality and the like.
Embodiments of the present application further provide a driving method for driving the shift register.
The method comprises the following steps:
s1, in the non-display stage, writing a touch signal into the touch signal line, and writing an input signal into the input signal line.
S2, in the display stage, writes an input signal to the input signal line, writes a control signal to the control signal line, writes a clock signal to the clock signal line, writes a reset signal to the first reset signal line, and writes a power supply signal to the power supply signal line.
It should be noted that, the above steps S1 and S2 are not limited to the order, and may be performed first in step S1 and then in step S2, or may be performed first in step S2 and then in step S1, specifically taking practical application as a standard.
The operation principle of the shift register shown in fig. 1 and 2 provided in this embodiment will be described in detail below with reference to the timing chart of each signal line shown in fig. 4, taking the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, the ninth transistor, the tenth transistor, the twelfth transistor, and the thirteenth transistor as N-type transistors as examples. Note that the timing of each signal line shown in fig. 4 is the timing of the shift register shown in fig. 1 and 2 during forward scanning, but the shift register shown in fig. 1 and 2 may be operated under reverse scanning, and the timing of each signal line operated under reverse scanning may be changed accordingly. In fig. 5 to 8, the transistor is off by an "x" mark. Here, the display device will be described by taking an example in which the display device does not include the second reset function, that is, the fourth transistor and the seventh transistor are not considered.
In the display phase, the phases t1-t3 in FIG. 4 are performed.
At a stage t1 in fig. 4, a high level is Input to both the Input signal line Input and the control signal line GCH, and a low level is Input to each of the clock signal line CLK, the first Reset signal line Reset, the touch signal line TH, and the power signal line VGL. At this time, referring to fig. 5, the first transistor T1, the ninth transistor T9, the third transistor T3, the sixth transistor T6, and the eighth transistor T8 are all turned on, and the second transistor T2, the fourth transistor T4, the fifth transistor T5, the seventh transistor T7, the tenth transistor T10, the eleventh transistor T11, the twelfth transistor T12, and the thirteenth transistor T13 are all turned off. Since the first transistor T1 is turned on, the voltage of the first node PU is raised; since the voltage of the first node PU is at a high level, the third transistor T3, the sixth transistor T6, and the eighth transistor T8 are all turned on; since both the sixth transistor T6 and the eighth transistor T8 are turned on, the voltage of the second node PD is at a low level.
At a stage t2 in fig. 4, a high level is Input to both the clock signal line CLK and the control signal line GCH, and a low level is Input to each of the Input signal line Input, the first Reset signal line Reset, the touch signal line TH, and the power signal line VGL. At this time, referring to fig. 6, the ninth transistor T9, the third transistor T3, the sixth transistor T6, and the eighth transistor T8 are all turned on, and the first transistor T1, the second transistor T2, the fourth transistor T4, the fifth transistor T5, the seventh transistor T7, the tenth transistor T10, the eleventh transistor T11, the twelfth transistor T12, and the thirteenth transistor T13 are all turned off. Since the PU point has been raised at the stage T1, the third transistor T3, the sixth transistor T6 and the eighth transistor T8 are still turned on; since the third transistor T3 is turned on, the high level of the clock signal line CLK is Output to the Output signal line Output at this time.
At a stage t3 in fig. 4, a high level is Input to the first Reset signal line Reset and the control signal line GCH, and a low level is Input to the Input signal line Input, the clock signal line CLK, the touch signal line TH, and the power signal line VGL. At this time, referring to fig. 7, the second transistor T2, the fifth transistor T5, the ninth transistor T9, the tenth transistor T10, and the eleventh transistor T11 are all turned on, and the third transistor T3, the sixth transistor T6, the eighth transistor T8, the first transistor T1, the fourth transistor T4, the seventh transistor T7, the twelfth transistor T12, and the thirteenth transistor T13 are all turned off. Since the second transistor T2 is turned on, the power of the first node PU is pulled down; since the fifth transistor T5 and the ninth transistor T9 are turned on so that the voltage of the second node PD is raised, the tenth transistor T10 and the eleventh transistor T11 are both turned on, and at this time, a low level is Output to the Output signal line Output through the eleventh transistor T11.
In the non-display stage, the stages t4-t5 as in FIG. 4 are performed.
At a stage t4 in fig. 4, a high level is Input to both the Input signal line Input and the touch signal line TH, and a low level is Input to each of the first Reset signal line Reset, the clock signal line CLK, the control signal line GCH, and the power signal line VGL. At this time, referring to fig. 8, the first transistor T1, the twelfth transistor T12, the thirteenth transistor T13, the sixth transistor T6, the eighth transistor T8, and the third transistor T3 are all turned on, and the ninth transistor T9, the second transistor T2, the fourth transistor T4, the fifth transistor T5, the seventh transistor T7, the tenth transistor T10, and the eleventh transistor T11 are all turned off. Since the first transistor T1 is turned on, the potential of the first node PU is raised, so that the third transistor T3, the sixth transistor T6 and the eighth transistor T8 are all turned on, and since the sixth transistor T6 and the eighth transistor T8 are all turned on, the low level of the power signal line VGL pulls down the voltage of the first node PU, and then since the twelfth transistor T12 and the thirteenth transistor T13 are turned on, the voltage of the first node PU is kept from being pulled down, thereby reducing or even avoiding the occurrence of horizontal striations; at the same time, since the third transistor T3 is turned on, the clock signal line CLK outputs a low level to the Output signal line Output.
At a stage t5 in fig. 4, a high level is Input to the clock signal line CLK and the touch signal line TH, and a low level is Input to the first Reset signal line Reset, the Input signal line Input, the control signal line GCH, and the power signal line VGL. At this time, referring to fig. 8, since the third transistor T3 is turned on, the clock signal line CLK outputs a high level to the Output signal line Output.
As shown in fig. 1 and 2, before the t1 stage of the display stage, a high level may be Input to the second Reset signal line STV0 and the control signal line GCH, and a low level may be Input to the Input signal line Input, the touch signal line TH, the first Reset signal line Reset, the clock signal line CLK, and the power supply signal line VGL. At this time, the fourth transistor T4, the seventh transistor T7, and the ninth transistor T9 are all turned on, and the first transistor T1, the twelfth transistor T12, the thirteenth transistor T13, the sixth transistor T6, the eighth transistor T8, the third transistor T3, the second transistor T2, the fifth transistor T5, the tenth transistor T10, and the eleventh transistor T11 are all turned off. Since the fourth transistor T4 is turned on, the voltage of the first node PU is reset; since the seventh transistor T7 is turned on, the Output signal line Output outputs a low level.
The sizes of the twelfth transistor and the thirteenth transistor can be small, so that the display device can reduce or even avoid stripes, and meanwhile, a narrow frame is achieved.
When a Touch signal (Touch signal) of the Touch signal line TH is turned on, the Touch signal line TH inputs a high level, the twelfth transistor T12 is turned on, and at this time, for a row of GOAs in which the first node PU is at a first-order potential, the Touch signal of the Touch signal line TH charges the first node PU, the first nodes PU of other rows of GOAs are at a low potential, and the thirteenth transistor T13 is turned off, and cannot charge the first nodes PU of other rows of GOAs, so that noise can be avoided.
The embodiment of the application provides a driving method, and through the driving method, the charging module can charge the first node PU at a first-order potential under the control of a touch signal line TH in a non-display stage, specifically, a touch stage, so that the first node PU does not leak electricity, the potential of the first node can be maintained, the output voltage is not too low, the pixel charging of the display device is not affected as much as possible, and then cross striations of the display device in an LH display mode are reduced or even avoided, and the user experience is greatly improved.
Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the application.
In the description provided herein, numerous specific details are set forth. However, it is understood that embodiments of the application may be practiced without these specific details. In some instances, well-known methods, structures and techniques have not been shown in detail in order not to obscure an understanding of this description.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, and not to limit the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions in the embodiments of the present application.
Claims (14)
1. A shift register, comprising:
the charging module is electrically connected with a touch signal line and a first node and is configured to keep the potential of the first node under the control of a touch signal of the touch signal line in a non-display stage;
an input module electrically connected to an input signal line and the first node, and configured to write an input signal of the input signal line into the first node under control of the input signal line in a display stage and the non-display stage;
a first reset module electrically connected to a first reset signal line, a power supply signal line, and the first node, and configured to write a power supply signal of the power supply signal line to the first node under control of a reset signal of the first reset signal line in the display phase;
an output module electrically connected to a clock signal line, the first node, and an output signal line, and configured to write a clock signal of the clock signal line into the output signal line under control of a voltage of the first node in the display stage and the non-display stage;
a pull-down control module electrically connected to the first node, a second node and the power signal line, and configured to write the power signal of the power signal line into the second node under control of a voltage of the first node in the display phase;
a pull-up control module electrically connected to a control signal line and the second node, and configured to write the control signal of the control signal line into the second node under control of a control signal of the control signal line in the display stage;
a pull-down module electrically connected to the power signal line, the second node, and the output signal line, and configured to write the power signal of the power signal line to the output signal line under control of a voltage of the second node in the display phase.
2. The shift register of claim 1, further comprising:
a second reset module electrically connected to a second reset signal line, the first node, the power signal line, and the output signal line, and configured to write the power signal of the power signal line to the first node and the output signal line, respectively, under control of a reset signal of the second reset signal line.
3. The shift register of claim 1, wherein the charging module comprises a twelfth transistor and a thirteenth transistor;
a control electrode and a first electrode of the twelfth transistor are electrically connected with the touch signal line, and a second electrode of the twelfth transistor is electrically connected with a first electrode of the thirteenth transistor;
a control electrode and a second electrode of the thirteenth transistor are both electrically connected to the first node.
4. The shift register according to claim 1, wherein the charging module includes a twelfth transistor and a thirteenth transistor;
a control electrode of the twelfth transistor is electrically connected with a second electrode of the thirteenth transistor, a first electrode of the twelfth transistor is electrically connected with the touch signal line, and a second electrode of the twelfth transistor is electrically connected with the first node;
the control electrode of the thirteenth transistor is electrically connected with the first node, and the first electrode is electrically connected with the touch signal line.
5. The shift register of claim 1, wherein the input block comprises a first transistor;
and the control electrode and the first electrode of the first transistor are electrically connected with the input signal line, and the second electrode of the first transistor is electrically connected with the first node.
6. The shift register of claim 1, wherein the first reset module comprises a second transistor;
a control electrode of the second transistor is electrically connected to the first reset signal line, a first electrode is electrically connected to the power signal line, and a second electrode is electrically connected to the first node.
7. The shift register according to claim 1, wherein the output module includes a third transistor and a capacitor;
a control electrode of the third transistor is electrically connected to the first node, a first electrode of the third transistor is electrically connected to the clock signal line, and a second electrode of the third transistor is electrically connected to the output signal line;
the first end of the capacitor is electrically connected with the first node, and the second end of the capacitor is electrically connected with the second pole of the third transistor.
8. The shift register according to claim 1, wherein the pull-down control module includes a sixth transistor and an eighth transistor;
a control electrode of the sixth transistor is electrically connected to the first node, the first electrode is electrically connected to the power signal line, and the second electrode is electrically connected to the second node;
a control electrode of the eighth transistor is electrically connected to the first node, the first electrode is electrically connected to the power signal line, and the second electrode is electrically connected to the second node.
9. The shift register of claim 1, wherein the pull-up control module comprises a fifth transistor and a ninth transistor;
a control electrode of the fifth transistor is electrically connected to a second electrode of the ninth transistor, a first electrode of the fifth transistor is electrically connected to the control signal line, and a second electrode of the fifth transistor is electrically connected to the second node;
and the control electrode and the first electrode of the ninth transistor are both electrically connected with the control signal line.
10. The shift register of claim 1, wherein the pull-down module comprises a tenth transistor and an eleventh transistor;
a control electrode of the tenth transistor is electrically connected to the second node, a first electrode is electrically connected to the power signal line, and a second electrode is electrically connected to the first node;
a control electrode of the eleventh transistor is electrically connected to the second node, a first electrode is electrically connected to the power signal line, and a second electrode is electrically connected to the output signal line.
11. The shift register according to claim 2, wherein the second reset module includes a fourth transistor and a seventh transistor;
a control electrode of the fourth transistor is electrically connected to the second reset signal line, a first electrode is electrically connected to the power signal line, and a second electrode is electrically connected to the first node;
a control electrode of the seventh transistor is electrically connected to the second reset signal line, a first electrode is electrically connected to the power signal line, and a second electrode is electrically connected to the output signal line.
12. A gate drive circuit comprising a plurality of cascaded shift registers according to any one of claims 1 to 11.
13. A display device comprising the gate driver circuit according to claim 12.
14. A driving method for driving the shift register according to any one of claims 1 to 11;
the method comprises the following steps:
writing a touch signal into the touch signal line and writing an input signal into the input signal line in a non-display stage; in the display stage, an input signal is written into an input signal line, a control signal is written into a control signal line, a clock signal is written into a clock signal line, a reset signal is written into a first reset signal line, and a power supply signal is written into a power supply signal line.
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| CN202210937354.3A CN115100997A (en) | 2022-08-05 | 2022-08-05 | Shifting register and driving method thereof, grid driving circuit and display device |
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| CN202210937354.3A CN115100997A (en) | 2022-08-05 | 2022-08-05 | Shifting register and driving method thereof, grid driving circuit and display device |
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