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CN115099186A - Chip verification method and device, electronic equipment and storage medium - Google Patents

Chip verification method and device, electronic equipment and storage medium Download PDF

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Publication number
CN115099186A
CN115099186A CN202210784582.1A CN202210784582A CN115099186A CN 115099186 A CN115099186 A CN 115099186A CN 202210784582 A CN202210784582 A CN 202210784582A CN 115099186 A CN115099186 A CN 115099186A
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sub
period
chip
verified
target performance
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崔昭华
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Aixin Yuanzhi Semiconductor Shanghai Co Ltd
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Aixin Yuanzhi Semiconductor Shanghai Co Ltd
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    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00Computer-aided design [CAD]
    • G06F30/30Circuit design
    • G06F30/39Circuit design at the physical level
    • G06F30/398Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2115/00Details relating to the type of the circuit
    • G06F2115/02System on chip [SoC] design

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  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
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  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
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Abstract

The disclosure provides a chip verification method, a chip verification device, an electronic device and a storage medium, wherein the method comprises the following steps: acquiring a transmission time period of performance data of a chip to be verified; determining at least one first subinterval and a second subinterval in each first subinterval according to the transmission interval; determining an expected target performance index of a second sub-period in the corresponding first sub-period according to the corresponding duration of each first sub-period and the set target performance index; and running the chip to be verified according to the set target performance indexes and the expected target performance indexes to obtain the monitoring target performance indexes of the chip to be verified in the first sub-periods, so that the monitoring target performance indexes of the chip to be verified in the first sub-periods can be in accordance with the real periodic transmission performance through the set target performance indexes of the first sub-periods and the expected target performance of the second sub-periods.

Description

Chip verification method and device, electronic equipment and storage medium
Technical Field
The present disclosure relates to the field of integrated circuit technologies, and in particular, to a chip verification method and apparatus, an electronic device, and a storage medium.
Background
The SOC (System-on-a-Chip) Chip is a Chip of an integrated circuit, can effectively reduce the development cost of electronic/information System products, shorten the development period, and improve the competitiveness of the products, and is the most important product development mode to be adopted in the future industry. In the design process of the SOC chip, whether the performance index meets the design requirement is a very critical design task, and how to model and simulate the performance characteristics of the chip quickly and accurately is a very important design challenge.
In the related art, after the integration of subsystems and a top-level system of the SOC chip is completed, the performance of the SOC chip is verified and simulated through EDA (Electronic Design Automation), but since EDA verification simulation can only fit the transmission characteristics of the system from the aspect of average transmission, and the actual transmission characteristics of the chip are often not the average transmission, the transmission performance of the chip cannot be simulated accurately by the verification method of average transmission.
Disclosure of Invention
The present disclosure is directed to solving, at least to some extent, one of the technical problems in the related art.
The disclosure provides a chip verification method to solve the problem that the transmission performance of a chip cannot be accurately simulated in the related art.
According to a first aspect of the present disclosure, there is provided a chip verification method, including: acquiring a transmission time period of performance data of a chip to be verified; determining at least one first sub-period and a second sub-period in each first sub-period according to the transmission period; determining an expected target performance index of a second sub-period in the corresponding first sub-period according to the corresponding duration of each first sub-period and a set target performance index; and operating the chip to be verified according to each set target performance index and each expected target performance index so as to obtain the monitoring target performance index of the chip to be verified in each first sub-period.
As a possible implementation manner of the embodiment of the present disclosure, the determining, according to the duration corresponding to each of the first sub-periods and the set target performance index, an expected target performance index of a second sub-period in the corresponding first sub-period includes: for each first sub-period, comparing the duration of the first sub-period with the duration of the corresponding second sub-period to obtain a duration ratio; and taking the product of each time length ratio and the set target performance index of the corresponding first sub-period as the expected target performance index of the second sub-period in the corresponding first sub-period.
As a possible implementation manner of the embodiment of the present disclosure, the determining, according to the transmission time interval, at least one first sub-time interval and a second sub-time interval in each first sub-time interval includes: the transmission time interval is segmented to obtain a plurality of first sub-time intervals; setting a second sub-period in any first sub-period in the plurality of first sub-periods, wherein the duration of the second sub-period is less than that of any first sub-period.
As a possible implementation manner of the embodiment of the present disclosure, the operating the chip to be verified according to each set target performance index and each expected target performance index to obtain a monitored target performance index of the chip to be verified in each first sub-period includes: according to each set target performance index and each expected target performance index, parameter setting is carried out in a verification example of the chip to be verified; according to the verification example after the parameter setting, operating the chip to be verified to acquire the transmission behavior information of the chip to be verified in each first sub-period; and determining the monitoring target performance index of the chip to be verified in each first sub-period according to the transmission behavior information of each first sub-period.
As a possible implementation manner of the embodiment of the present disclosure, the obtaining a transmission time period of performance data of a chip to be verified includes: acquiring a historical transmission log of the performance data of the chip to be verified; and determining the transmission time period of the performance data of the chip to be verified according to the historical transmission log.
According to a second aspect of the embodiments of the present disclosure, there is provided a chip verification apparatus including: the acquisition module is used for acquiring the transmission time interval of the performance data of the chip to be verified; a first determining module, configured to determine at least one first sub-period and a second sub-period in each first sub-period according to the transmission period; the second determining module is used for determining an expected target performance index of a second sub-period in the corresponding first sub-period according to the duration corresponding to each first sub-period and the set target performance index; and the operation module is used for operating the chip to be verified according to each set target performance index and each expected target performance index so as to obtain the monitoring target performance index of the chip to be verified in each first sub-period.
As a possible implementation manner of the embodiment of the present disclosure, the second determining module is further configured to: for each first sub-period, comparing the duration of the first sub-period with the duration of the corresponding second sub-period to obtain a duration ratio; and taking the product of each time length ratio and the set target performance index of the corresponding first sub-period as the expected target performance index of the second sub-period in the corresponding first sub-period.
As a possible implementation manner of the embodiment of the present disclosure, the first determining module is further configured to: the transmission time interval is segmented to obtain a plurality of first sub-time intervals; setting a second sub-period in any first sub-period in the plurality of first sub-periods, wherein the duration of the second sub-period is less than that of any first sub-period.
As a possible implementation manner of the embodiment of the present disclosure, the running module is further configured to: according to each set target performance index and each expected target performance index, parameter setting is carried out in a verification example of the chip to be verified; according to the verification example after the parameter setting, operating the chip to be verified to acquire the transmission behavior information of the chip to be verified in each first sub-period; and determining the monitoring target performance index of the chip to be verified in each first sub-period according to the transmission behavior information of each first sub-period.
As a possible implementation manner of the embodiment of the present disclosure, the obtaining module is further configured to: acquiring a historical transmission log of the performance data of the chip to be verified; and determining the transmission time period of the performance data of the chip to be verified according to the historical transmission log.
According to a third aspect of the present disclosure, there is provided an electronic device comprising: at least one processor; and a memory communicatively coupled to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to execute the chip verification method provided in the embodiment of the first aspect of the present disclosure.
According to a fourth aspect of the present disclosure, there is provided a computer-readable storage medium, wherein instructions, when executed by a processor of an electronic device, enable the electronic device to perform the chip verification method set forth in the embodiments of the first aspect of the present disclosure.
According to a fifth aspect of the present disclosure, there is provided a computer program product, comprising a computer program, which, when executed by a processor of an electronic device, enables the electronic device to perform the chip verification method set forth in the embodiments of the first aspect.
Additional aspects and advantages of the disclosure will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the disclosure.
Drawings
The foregoing and/or additional aspects and advantages of the present disclosure will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which:
FIG. 1 is a flow diagram illustrating a method for chip verification in accordance with an exemplary embodiment;
FIG. 2 is a flow diagram illustrating another method of chip verification according to an exemplary embodiment;
FIG. 3 is a flow diagram illustrating another method of chip verification according to an exemplary embodiment;
FIG. 4 is a flow diagram illustrating another method of chip verification according to an exemplary embodiment;
FIG. 5 is a schematic diagram of a chip verification apparatus according to an exemplary embodiment;
fig. 6 is a block diagram illustrating an electronic device of a chip verification method according to an example embodiment.
Detailed Description
Reference will now be made in detail to the embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the drawings are exemplary and intended to be illustrative of the present disclosure, and should not be construed as limiting the present disclosure.
In the related art, after the integration of subsystems and a top-level system of an SOC chip is completed, the performance of the SOC chip is verified and simulated through EDA (Electronic Design Automation), but because EDA verification simulation can only fit the transmission characteristics of the system from the aspect of average transmission, for example, the read-write bandwidth characteristics of a specified system, verification simulation is performed through a method of limiting the flow, and the actual transmission characteristics of the chip often do not exist in the form of average transmission, but exist in the form of random burst characteristics with peaks and valleys, the transmission performance of the chip cannot be accurately simulated through the verification method of average transmission.
The following describes the chip verification method, apparatus, electronic device, and storage medium provided in the present disclosure in detail with reference to the accompanying drawings.
Fig. 1 is a flow chart illustrating a chip verification method according to an exemplary embodiment. It should be noted that the chip verification method can be applied to a chip verification apparatus. The chip verification device may be, for example, a hardware device that can be connected to the chip through a bus or the like, or a controller in the hardware device, or control software in the hardware device, and may be set according to actual needs, which is not limited in this disclosure.
As shown in fig. 1, the chip verification method includes the following steps:
step 101, obtaining a transmission time period of performance data of a chip to be verified.
The chip to be verified may be an SOC chip or other chips capable of performing chip verification by using the chip verification method provided by the embodiment of the present disclosure, which is not limited by the present disclosure, and the embodiment of the present disclosure takes the chip as the SOC chip for illustration.
In the embodiment of the present disclosure, the transmission period may be a time period of the whole transmission process of the performance data of the chip to be verified, and as an example, the transmission period of the performance data of the chip to be verified may be determined according to a historical transmission period of the chip to be verified.
Step 102, determining at least one first sub-period and a second sub-period in each first sub-period according to the transmission period.
In order to simulate the transmission performance of the chip and conform to the real periodic transmission performance, in the embodiment of the disclosure, the transmission time interval may be divided into at least one first sub-time interval, and a second sub-time interval is set in each first sub-time interval.
And 103, determining an expected target performance index of a second sub-period in the corresponding first sub-period according to the duration corresponding to each first sub-period and the set target performance index.
Further, a set target performance index may be set for each first sub-period, that is, the set target performance index is used as a constraint condition of the first sub-period, that is, the transmission performance of the control node of the chip to be verified in the range of the first sub-period is required to be less than or equal to the set target performance index, for example, taking the set target performance index as a target bandwidth, the transmission bandwidth of the control node of the SOC chip in the range of the first sub-period is less than or equal to the target bandwidth.
Furthermore, in order to make the transmission performance of the control node of the chip to be verified within the range of the first sub-period less than or equal to the set target performance index, the expected target performance index of the second sub-period in the corresponding first sub-period may be determined according to the time length corresponding to each first sub-period and the set target performance index.
And step 104, operating the chip to be verified according to each set target performance index and each expected target performance index so as to obtain the monitoring target performance index of the chip to be verified in each first sub-period.
As an example, according to each set target performance index and each expected target performance index, performing parameter setting in a verification example of a chip to be verified, and according to the verification example after the parameter setting, operating the chip to be verified to obtain transmission behavior information of the chip to be verified in each first sub-period; and determining the monitoring target performance index of the chip to be verified in each first sub-period according to the transmission behavior information of each first sub-period.
That is to say, in the chip verification environment, according to each set target performance index and each expected target performance index, a corresponding parameter is set in the verification example of the chip to be verified, further, according to the verification example after the parameter setting, the operation of the chip to be verified is controlled, so that the chip to be verified performs transmission process simulation according to each set target performance index and each expected target performance index, so as to obtain the transmission behavior information of the chip to be verified in each first sub-period, and further, the transmission behavior information is analyzed, so as to obtain the monitoring target performance index of the chip to be verified in each first sub-period. The transmission behavior information is any information required for chip verification, such as a transmission time point, a data transmission total amount, and the like.
In summary, the transmission time interval of the performance data of the chip to be verified is obtained; determining at least one first subinterval and a second subinterval in each first subinterval according to the transmission interval; determining an expected target performance index of a second sub-period in the corresponding first sub-period according to the corresponding duration of each first sub-period and a set target performance index; and running the chip to be verified according to the set target performance indexes and the expected target performance indexes to obtain the monitoring target performance indexes of the chip to be verified in the first sub-periods, so that the monitoring target performance indexes of the chip to be verified in the first sub-periods can be in accordance with the real periodic transmission performance through the set target performance indexes of the first sub-periods and the expected target performance of the second sub-periods.
To clearly illustrate how to determine the expected target performance indicator of the second sub-period in the corresponding first sub-period, the present disclosure proposes another chip verification method, as shown in fig. 2, fig. 2 is a flowchart of another chip verification method according to an exemplary embodiment, in the embodiment of the present disclosure, for each first sub-period, a ratio of a duration of the first sub-period to a duration of the corresponding second sub-period is determined, and according to the ratio of the duration to the set target performance indicator of the first sub-period, the expected target performance indicator of the corresponding second sub-period is determined, and the embodiment shown in fig. 2 may include the following steps:
step 201, obtaining a transmission time period of performance data of a chip to be verified.
Step 202, according to the transmission time interval, at least one first sub-time interval and a second sub-time interval in each first sub-time interval are determined.
Step 203, for each first sub-period, comparing the duration of the first sub-period with the duration of the corresponding second sub-period to obtain a duration ratio.
In the embodiment of the present disclosure, each first sub-period may correspond to a duration, a second sub-period in each first sub-period also corresponds to a duration, the duration corresponding to the second sub-period is less than the duration corresponding to the corresponding first sub-period, the durations corresponding to the first sub-periods may be the same or different, the durations corresponding to the second sub-periods may be the same or different, and the present disclosure is not limited specifically.
In the embodiment of the present disclosure, the duration of each first sub-period may be compared with the duration of the corresponding second sub-period to obtain a corresponding duration ratio.
And step 204, taking the product of each time length ratio and the set target performance index of the corresponding first sub-period as the expected target performance index of the second sub-period in the corresponding first sub-period.
For example, with the time length of one of the first sub-periods being Ta, the set target performance indicator of the first sub-period being freq _ a, the time length of the second one of the first sub-periods being Tb, the ratio of the time length of the first sub-period to the time length of the corresponding second sub-period being Ta/Tb, and the desired target performance of the second one of the first sub-periods being freq _ B (Ta/Tb).
Step 205, operating the chip to be verified according to each set target performance index and each expected target performance index to obtain the monitoring target performance index of the chip to be verified in each first sub-period.
It should be noted that the execution processes of steps 201 to 202 and step 205 may be implemented by any one of the embodiments of the present disclosure, and the embodiments of the present disclosure do not limit this, and are not described again.
In summary, for each first sub-period, the duration of the first sub-period is compared with the duration of the corresponding second sub-period to obtain a duration ratio; and taking the product of each time length ratio and the set target performance index of the corresponding first sub-period as the expected target performance index of the second sub-period in the corresponding first sub-period, thereby determining the expected target performance index of the second sub-period in the corresponding first sub-period according to the time length corresponding to each first sub-period and the set target performance index, enabling the monitoring target performance index of the chip to be verified in each first sub-period to have peak-to-valley mutation, and simultaneously meeting the requirement of the set target performance index.
To clearly illustrate how to determine at least one first sub-period and a second sub-period in each first sub-period according to a transmission period, the present disclosure proposes another chip verification method, as shown in fig. 3, where fig. 3 is a schematic flow chart of another chip verification method according to an exemplary embodiment, in an embodiment of the present disclosure, a plurality of transmission periods may be divided to obtain a plurality of first sub-periods, and a second sub-period is set in each first sub-period, and the embodiment shown in fig. 3 may include the following steps:
step 301, obtaining a transmission time period of performance data of a chip to be verified.
Step 302, the transmission time interval is divided to obtain a plurality of first sub-time intervals.
In the embodiment of the present disclosure, the transmission period may be divided equally, or divided unequally, so as to obtain a plurality of first sub-periods. For example, the duration of the first sub-period may be between 1 microsecond and 5 microseconds.
Step 303, setting a second sub-period in any first sub-period of the plurality of first sub-periods.
And the duration of the second sub-period is less than the duration of any first sub-period.
Furthermore, for each first subinterval in the plurality of first subintervals, a second subinterval is set in each first subinterval, wherein the duration of the second subinterval is less than the duration of any one of the first subintervals.
And step 304, determining the expected target performance index of the second sub-period in the corresponding first sub-period according to the duration corresponding to each first sub-period and the set target performance index.
Step 305, operating the chip to be verified according to each set target performance index and each expected target performance index so as to obtain the monitoring target performance index of the chip to be verified in each first sub-period.
It should be noted that the execution processes of step 301, step 304 to step 305 may be implemented by any one of the embodiments of the present disclosure, and the embodiments of the present disclosure do not limit this, and are not described again.
In summary, the transmission time interval is divided to obtain a plurality of first sub-time intervals, and for any first sub-time interval in the plurality of first sub-time intervals, a second sub-time interval is set in any first sub-time interval, so that the transmission time interval can be decomposed into the plurality of sub-time intervals to set corresponding target performance indexes on the plurality of sub-time intervals, and performance verification with a greater degree of freedom is achieved.
In order to clearly illustrate how to obtain the transmission time period of the performance data of the chip to be verified, the present disclosure proposes another chip verification method, as shown in fig. 4, where fig. 4 is a schematic flow chart of another chip verification method according to an exemplary embodiment, in an embodiment of the present disclosure, the transmission time period of the performance data of the chip to be verified may be determined according to a historical transmission log of the performance data of the chip to be verified, and the embodiment shown in fig. 4 may include the following steps:
step 401, obtaining a historical transmission log of performance data of a chip to be verified.
In the embodiment of the present disclosure, the transmission log may include performance data transmission information of the chip to be verified, for example, a transmission period, a transmission process, and the like of the performance data may be included.
As an example, the transmission time period, the transmission process, and the like of the historical performance data of the chip to be verified may be written into a log file to obtain a historical transmission log to be verified, and the historical transmission log of the performance data of the chip to be verified may be extracted to obtain a historical transmission log of the performance data of the chip to be verified.
Step 402, determining the transmission time interval of the performance data of the chip to be verified according to the historical transmission log.
Furthermore, the historical transmission log is analyzed, the transmission time interval of the historical performance data of the chip to be verified in the historical transmission log can be extracted, and the transmission time interval of the historical performance data of the chip to be verified is used as the transmission time interval of the performance data of the heart rate to be verified. In order to improve the accuracy of the transmission time period of the performance data of the chip to be verified, the transmission time period of the historical performance data can be acquired for multiple times, the average value of the corresponding transmission time period is determined according to the transmission time periods of the historical performance data acquired for multiple times, and the average value of the transmission time period of the historical performance data is used as the transmission time period of the performance data of the chip to be verified.
Step 403, determining at least one first sub-period and a second sub-period in each first sub-period according to the transmission period.
Step 404, determining an expected target performance index of a second sub-period in the corresponding first sub-period according to the duration corresponding to each first sub-period and the set target performance index.
Step 405, operating the chip to be verified according to each set target performance index and each expected target performance index to obtain the monitoring target performance index of the chip to be verified in each first sub-period.
It should be noted that the execution process of step 403 to step 405 may be implemented by any way in each embodiment of the present disclosure, and this is not limited by the embodiment of the present disclosure and is not described again.
In conclusion, according to the historical transmission log of the performance data of the chip to be verified, the transmission time period of the performance data of the chip to be verified can be determined.
The chip verification method of the embodiment of the disclosure obtains the transmission time interval of the performance data of the chip to be verified; determining at least one first subinterval and a second subinterval in each first subinterval according to the transmission interval; determining an expected target performance index of a second sub-period in the corresponding first sub-period according to the corresponding duration of each first sub-period and the set target performance index; and operating the chip to be verified according to the set target performance indexes and the expected target performance indexes to obtain the monitoring target performance indexes of the chip to be verified in the first sub-periods. Therefore, the monitoring target performance index of the chip to be verified in each first sub-period can be made to accord with the real periodic transmission performance through the set target performance index of the first sub-period and the expected target performance of the second sub-period.
In order to implement the above embodiments, the present disclosure further provides a chip verification apparatus.
Fig. 5 is a schematic structural diagram of a chip verification apparatus according to an exemplary embodiment.
As shown in fig. 5, the chip verification apparatus 500 includes: an acquisition module 510, a first determination module 520, a second determination module 530, and an execution module 540.
The obtaining module 510 is configured to obtain a transmission time period of performance data of a chip to be verified; a first determining module 520, configured to determine at least one first sub-period and a second sub-period in each first sub-period according to the transmission period; a second determining module 530, configured to determine, according to the duration corresponding to each first sub-period and the set target performance index, an expected target performance index of a second sub-period in the corresponding first sub-period; the running module 540 is configured to run the chip to be verified according to each set target performance index and each expected target performance index, so as to obtain a monitored target performance index of the chip to be verified at each first sub-period.
As a possible implementation manner of the embodiment of the present disclosure, the second determining module 530 is further configured to: for each first sub-period, comparing the duration of the first sub-period with the duration of the corresponding second sub-period to obtain a duration ratio; and taking the product of each time length ratio and the set target performance index of the corresponding first sub-period as the expected target performance index of the second sub-period in the corresponding first sub-period.
As a possible implementation manner of the embodiment of the present disclosure, the first determining module 520 is further configured to: the transmission time interval is segmented to obtain a plurality of first sub-time intervals; and aiming at any one first subinterval in the plurality of first subintervals, setting a second subinterval in any one first subinterval, wherein the duration of the second subinterval is less than that of any one first subinterval.
As a possible implementation manner of the embodiment of the present disclosure, the running module 540 is further configured to: setting parameters in a verification example of a chip to be verified according to each set target performance index and each expected target performance index; according to the verification example after the parameter setting, operating the chip to be verified to acquire the transmission behavior information of the chip to be verified in each first sub-period; and determining the monitoring target performance index of the chip to be verified in each first sub-period according to the transmission behavior information of each first sub-period.
The chip verification device of the embodiment of the disclosure obtains the transmission time interval of the performance data of the chip to be verified; determining at least one first subinterval and a second subinterval in each first subinterval according to the transmission interval; determining an expected target performance index of a second sub-period in the corresponding first sub-period according to the corresponding duration of each first sub-period and the set target performance index; and operating the chip to be verified according to the set target performance indexes and the expected target performance indexes to obtain the monitoring target performance indexes of the chip to be verified in the first sub-periods. Therefore, the monitoring target performance index of the chip to be verified in each first sub-period can be made to accord with the real periodic transmission performance through the set target performance index of the first sub-period and the expected target performance of the second sub-period.
In order to implement the foregoing embodiments, the present disclosure further provides an electronic device, as shown in fig. 6, where fig. 6 is a block diagram of an electronic device of a chip verification method according to an exemplary embodiment. As shown in fig. 6, the electronic device 600 may include:
a memory 610 and a processor 620, a bus 630 connecting different components (including the memory 610 and the processor 620), wherein the memory 610 stores a computer program, and when the processor 620 executes the program, the chip verification method according to the embodiment of the disclosure is implemented.
Bus 630 represents one or more of any of several types of bus structures, including a memory bus or memory controller, a peripheral bus, an accelerated graphics port, and a processor or local bus using any of a variety of bus architectures. By way of example, such architectures include, but are not limited to, Industry Standard Architecture (ISA) bus, micro-channel architecture (MAC) bus, enhanced ISA bus, Video Electronics Standards Association (VESA) local bus, and Peripheral Component Interconnect (PCI) bus.
Electronic device 600 typically includes a variety of computer-readable media. Such media may be any available media that is accessible by electronic device 600 and includes both volatile and nonvolatile media, removable and non-removable media.
Memory 610 may also include computer system readable media in the form of volatile memory, such as Random Access Memory (RAM)640 and/or cache memory 650. The electronic device 600 may further include other removable/non-removable, volatile/nonvolatile computer system storage media. By way of example only, storage system 660 may be used to read from and write to non-removable, nonvolatile magnetic media (not shown in FIG. 6, and commonly referred to as a "hard disk drive"). Although not shown in FIG. 6, a magnetic disk drive for reading from and writing to a removable, nonvolatile magnetic disk (e.g., a "floppy disk") and an optical disk drive for reading from or writing to a removable, nonvolatile optical disk (e.g., a CD-ROM, DVD-ROM, or other optical media) may be provided. In these cases, each drive may be connected to bus 630 by one or more data media interfaces. Memory 610 may include at least one program product having a set (e.g., at least one) of program modules that are configured to carry out the functions of embodiments of the disclosure.
A program/utility 680 having a set (at least one) of program modules 670 may be stored, for example, in memory 610, such program modules 670 including, but not limited to, an operating system, one or more application programs, other program modules, and program data, each of which examples or some combination thereof may comprise an implementation of a network environment. The program modules 670 generally perform the functions and/or methods of the embodiments described in this disclosure.
The electronic device 600 may also communicate with one or more external devices 690 (e.g., keyboard, pointing device, display 691, etc.), with one or more devices that enable a user to interact with the electronic device 600, and/or with any devices (e.g., network card, modem, etc.) that enable the electronic device 600 to communicate with one or more other computing devices. Such communication may be through input/output (I/O) interfaces 692. Also, the electronic device 600 may communicate with one or more networks (e.g., a Local Area Network (LAN), a Wide Area Network (WAN), and/or a public network such as the Internet) via the network adapter 693. As shown in FIG. 6, the network adapter 693 communicates with the other modules of the electronic device 600 via the bus 630. It should be appreciated that although not shown in FIG. 6, other hardware and/or software modules may be used in conjunction with the electronic device 600, including but not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data backup storage systems, to name a few.
The processor 620 executes various functional applications and data processing by executing programs stored in the memory 610.
It should be noted that, for the implementation process and the technical principle of the electronic device of the embodiment, reference is made to the foregoing explanation of the chip verification method in the embodiment of the present disclosure, and details are not described herein again.
The electronic equipment provided by the embodiment of the disclosure acquires the transmission time interval of the performance data of the chip to be verified; determining at least one first subinterval and a second subinterval in each first subinterval according to the transmission interval; determining an expected target performance index of a second sub-period in the corresponding first sub-period according to the corresponding duration of each first sub-period and the set target performance index; and operating the chip to be verified according to the set target performance indexes and the expected target performance indexes to obtain the monitoring target performance indexes of the chip to be verified in the first sub-periods. Therefore, the monitoring target performance index of the chip to be verified in each first sub-period can be made to accord with the real periodic transmission performance through the set target performance index of the first sub-period and the expected target performance of the second sub-period.
In order to implement the above embodiments, the embodiments of the present disclosure also provide a computer-readable storage medium.
Wherein the instructions in the computer readable storage medium, when executed by a processor of the electronic device, enable the electronic device to perform the chip verification method as previously described.
To implement the above embodiments, the present disclosure also provides a computer program product, which, when executed by a processor of an electronic device, enables the electronic device to perform the chip verification method as described above.
Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This disclosure is intended to cover any variations, uses, or adaptations of the disclosure following, in general, the principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.
It will be understood that the present disclosure is not limited to the precise arrangements described above and shown in the drawings and that various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.

Claims (13)

1. A method of chip verification, comprising:
acquiring a transmission time period of performance data of a chip to be verified;
determining at least one first sub-period and a second sub-period in each first sub-period according to the transmission period;
determining an expected target performance index of a second sub-period in the corresponding first sub-period according to the corresponding duration of each first sub-period and a set target performance index;
and operating the chip to be verified according to each set target performance index and each expected target performance index so as to obtain the monitoring target performance index of the chip to be verified in each first sub-period.
2. The method of claim 1, wherein determining the desired target performance indicator for the second sub-period of the corresponding first sub-period according to the duration and the set target performance indicator for each of the first sub-periods comprises:
for each first sub-period, comparing the duration of the first sub-period with the duration of the corresponding second sub-period to obtain a duration ratio;
and taking the product of each time length ratio and the set target performance index of the corresponding first sub-period as the expected target performance index of the second sub-period in the corresponding first sub-period.
3. The method of claim 1, wherein determining at least one first sub-period and a second sub-period of each first sub-period according to the transmission period comprises:
the transmission time interval is segmented to obtain a plurality of first sub-time intervals;
setting a second sub-period in any first sub-period in the plurality of first sub-periods, wherein the duration of the second sub-period is less than that of any first sub-period.
4. The method according to any one of claims 1 to 3, wherein the operating the chip to be verified according to each set target performance index and each expected target performance index to obtain a monitored target performance index of the chip to be verified in each first sub-period comprises:
according to each set target performance index and each expected target performance index, parameter setting is carried out in a verification example of the chip to be verified;
according to the verification example after the parameter setting, operating the chip to be verified to acquire the transmission behavior information of the chip to be verified in each first sub-period;
and determining the monitoring target performance index of the chip to be verified in each first sub-period according to the transmission behavior information of each first sub-period.
5. The method according to any one of claims 1 to 3, wherein the obtaining of the transmission period of the performance data of the chip to be verified comprises:
acquiring a historical transmission log of the performance data of the chip to be verified;
and determining the transmission time period of the performance data of the chip to be verified according to the historical transmission log.
6. A chip verification apparatus, comprising:
the acquisition module is used for acquiring the transmission time interval of the performance data of the chip to be verified;
a first determining module, configured to determine at least one first sub-period and a second sub-period in each first sub-period according to the transmission period;
the second determining module is used for determining an expected target performance index of a second sub-period in the corresponding first sub-period according to the duration corresponding to each first sub-period and the set target performance index;
and the operation module is used for operating the chip to be verified according to each set target performance index and each expected target performance index so as to obtain the monitoring target performance index of the chip to be verified in each first sub-period.
7. The apparatus of claim 6, wherein the second determining module is further configured to:
for each first sub-period, comparing the duration of the first sub-period with the duration of the corresponding second sub-period to obtain a duration ratio;
and taking the product of each time length ratio and the set target performance index of the corresponding first sub-period as the expected target performance index of the second sub-period in the corresponding first sub-period.
8. The apparatus of claim 6, wherein the first determining module is further configured to:
segmenting the transmission time interval to obtain a plurality of first sub-time intervals;
setting a second sub-period in any first sub-period in the plurality of first sub-periods, wherein the duration of the second sub-period is less than that of any first sub-period.
9. The apparatus of any of claims 6-8, wherein the operation module is further configured to:
setting parameters in a verification example of the chip to be verified according to each set target performance index and each expected target performance index;
according to the verification example after the parameter setting, operating the chip to be verified to acquire the transmission behavior information of the chip to be verified in each first sub-period;
and determining the monitoring target performance index of the chip to be verified in each first sub-period according to the transmission behavior information of each first sub-period.
10. The apparatus according to any one of claims 6-8, wherein the obtaining module is further configured to:
acquiring a historical transmission log of the performance data of the chip to be verified;
and determining the transmission time period of the performance data of the chip to be verified according to the historical transmission log.
11. An electronic device, comprising:
at least one processor; and
a memory communicatively coupled to the at least one processor; wherein,
the memory stores instructions executable by the at least one processor to enable the at least one processor to perform the chip verification method of any one of claims 1-5.
12. A computer-readable storage medium whose instructions, when executed by a processor of an electronic device, enable the electronic device to perform the chip verification method of any one of claims 1-5.
13. A computer program product comprising a computer program which, when executed by a processor of an electronic device, enables the electronic device to perform the chip verification method according to any one of claims 1-5.
CN202210784582.1A 2022-07-05 2022-07-05 Chip verification method and device, electronic equipment and storage medium Pending CN115099186A (en)

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Publication number Priority date Publication date Assignee Title
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CN114528792A (en) * 2022-02-18 2022-05-24 杭州爱芯元智科技有限公司 Chip verification method and device, electronic equipment and storage medium

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CN105823976A (en) * 2015-01-09 2016-08-03 中芯国际集成电路制造(上海)有限公司 Method for detecting chip and verifying chip testing result
CN105550445A (en) * 2015-12-12 2016-05-04 中国航空工业集团公司西安航空计算技术研究所 Encoding/decoding chip based virtual verification method
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