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CN115084248A - Trench structure of shielded gate trench type MOSFET and forming method - Google Patents

Trench structure of shielded gate trench type MOSFET and forming method Download PDF

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Publication number
CN115084248A
CN115084248A CN202210514547.8A CN202210514547A CN115084248A CN 115084248 A CN115084248 A CN 115084248A CN 202210514547 A CN202210514547 A CN 202210514547A CN 115084248 A CN115084248 A CN 115084248A
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groove
dielectric layer
polysilicon
trench
mosfet
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金梦静
石磊
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/4238—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the surface lay-out
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/435—Resistive materials for field effect devices, e.g. resistive gate for MOSFET or MESFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
    • H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement

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Abstract

The invention discloses a shielded gate trench MOSFET and a process method thereof, wherein the process method comprises the following steps: etching to form a groove; then depositing a first dielectric layer in the groove and filling the first polysilicon; step two, carrying out back etching on the first polycrystalline silicon in the groove; etching the first dielectric layer on the inner wall of the groove; depositing a second dielectric layer in the etched groove; fifthly, back etching is carried out on the second dielectric layer in the groove; depositing a third dielectric layer in the groove, wherein the third dielectric layer is attached to the side wall of the residual space in the groove; step seven, depositing a second polycrystalline silicon layer; eighthly, etching back the deposited second polycrystalline silicon layer; and step nine, depositing an interlayer medium in the groove to fill the groove with the interlayer medium. The structure formed by the invention has lower grid width and can reduce the grid-source capacitance connected in parallel.

Description

Trench structure of shielded gate trench type MOSFET and forming method
Technical Field
The invention relates to the field of semiconductor integrated circuit manufacturing, in particular to a trench structure of a shielded gate trench type MOSFET.
The invention also relates to a forming method of the trench structure of the shielded gate trench type MOSFET.
Background
The groove type double-layer gate MOSFET is used as a power device and has the characteristics of high breakdown voltage, low on-resistance and high switching speed. The trench of the shielded gate trench type MOSFET is divided into an upper part and a lower part, and the lower part of the trench is filled with polysilicon to form a shielded gate. The shielded gate groove type MOSFET is used as a power device and has the characteristics of high breakdown voltage, low on-resistance and high switching speed.
The most important research direction of MOSFETs is to reduce the power consumption, including conduction loss and switching loss. The output capacitance of the shielded gate trench MOSFET is the sum of the gate-drain capacitance Cgd and the gate-source capacitance Cgs: coss ═ Cgd + Cgs. The larger output capacitance causes longer turn-off time under transient response and higher switching loss, so the output capacitance becomes one of the main factors limiting the operating frequency and switching loss of the device, and the output capacitance Coss of the trench MOSFET needs to be reduced. At low frequency, the impedance of the input capacitor is very large, Cgs is approximately open-circuit, most of the input signal falls on Cgs, the input signal induces charges of equal and opposite signs at two ends of the grid-source flashlight Cgs, channel charges change along with the change of the input signal, and therefore leakage current increment is generated, and at high frequency, the input impedance of the fringe-grid-source capacitor Cgs falls along with the increase of frequency, and the gate current falls along with the increase of frequency.
Disclosure of Invention
The invention aims to provide a trench structure of a shielded gate trench type MOSFET.
The invention also provides a forming method of the groove structure of the shielded gate groove type MOSFET.
In order to solve the above problems, the process method for forming the trench structure of the shielded gate trench MOSFET according to the present invention comprises:
comprises the following steps:
providing a semiconductor substrate, wherein the semiconductor substrate is provided with a front surface and a back surface; the reverse side of the semiconductor substrate is used as a drain region of the MOSFET; forming an epitaxial layer on the front surface of the semiconductor substrate, and etching the epitaxial layer to form a groove; then depositing a first dielectric layer in the groove to be attached to the inner wall and the bottom of the groove, and then filling the groove with first polysilicon;
secondly, etching back the first polycrystalline silicon in the groove to enable the top surface of the first polycrystalline silicon reserved in the groove to be located in the middle of the depth of the groove;
etching the first dielectric layer on the inner wall of the groove, removing the first dielectric layer on the inner wall of the groove above the top surface of the reserved first polysilicon, and over-etching the first dielectric layer on the inner wall of the groove to ensure that the top surface of the first dielectric layer on the inner wall of the groove is lower than the top surface of the reserved first polysilicon;
depositing a second dielectric layer in the etched groove, wherein the second dielectric layer fills the residual space of the groove;
fifthly, back etching is carried out on the second dielectric layer in the groove;
depositing a third dielectric layer in the groove, wherein the third dielectric layer is attached to the side wall of the residual space in the groove;
step seven, depositing a second polycrystalline silicon layer;
eighthly, etching back the deposited second polycrystalline silicon layer;
and step nine, depositing an interlayer medium in the groove to fill the groove with the interlayer medium.
Further, in the first step, the first dielectric layer is an insulating dielectric layer.
Furthermore, the first dielectric layer is a silicon oxide layer.
Further, in the second step, after the first polysilicon is etched back, the remaining first polysilicon is used as a shielding gate of the trench-type MOFET.
Further, in the third step, after the first dielectric layer is over-etched, the first dielectric layers on two sides of the polysilicon in the middle of the lower portion of the trench are lower than the first polysilicon, so that two accommodating spaces are formed between two sides of the first polysilicon and the inner wall of the trench.
Further, in the fourth step, the second dielectric layer is an insulating dielectric layer and is used as an isolation between the first polysilicon and the second polysilicon.
Further, in the fourth step, the second dielectric layer is a silicon oxide layer or a silicon nitride layer.
Further, in the fifth step, when the second dielectric layer is etched back, the second dielectric layer inside the trench is removed by etching back, and the second dielectric layer with a certain thickness is reserved above the first polysilicon; the remaining thickness provides effective electrical isolation between the second polysilicon and the first polysilicon.
Further, in the sixth step, the third dielectric layer is an insulating dielectric layer and is used as an isolation between the second polysilicon and the epitaxy.
Further, the third dielectric layer is silicon oxide.
Further, in the seventh step, the deposited second polysilicon is formed to a certain thickness inside the trench, but the trench is not filled, and the thickness of the second polysilicon deposited on the inner wall of the trench meets the requirement of the lateral width of the gate.
Further, in the eighth step, after the second polysilicon is etched back, the second polysilicon at the bottom of the trench is etched and removed, only the second polysilicon attached to the inner walls of the two sides of the trench is remained, and the second polysilicon on the surface of the semiconductor substrate is completely removed.
Further, in the ninth step, an interlayer dielectric is deposited in the trench, and the second polysilicon is located on two sides of the interlayer dielectric to form a two-piece trench gate; after the interlayer dielectric is formed, well injection, source region injection, contact hole formation and front metal deposition are further included to form a front electrode; and forming the drain electrode of the MOSFET after the back surface of the semiconductor substrate is thinned.
The trench structure of the shielded gate trench type MOSFET formed by the process method comprises the following steps:
providing a semiconductor substrate, and forming a lightly doped epitaxial layer of a first conduction type on the semiconductor substrate;
forming a groove in the epitaxial layer, wherein the groove is provided with a shielding grid structure and a grid structure of the MOSFET, and an upper structure and a lower structure are formed in the groove;
the shielding gate structure is positioned at the lower part of the groove and consists of a first dielectric layer and first polycrystalline silicon positioned in the groove, the first dielectric layer forms an isolation layer between the first polycrystalline silicon and the inner wall of the groove, and the first polycrystalline silicon is wrapped in the groove in a U shape;
the grid structure is positioned above the shielding grid structure and is isolated from the shielding grid structure by a second dielectric layer; the grid structure consists of two parts of second polycrystalline silicon, and the two parts of second polycrystalline silicon are respectively positioned at two sides of the groove close to the inner wall of the groove; the second polysilicon is isolated from the inner wall of the groove by a third dielectric layer;
the groove is filled with an interlayer medium, and the interlayer medium is positioned in the groove between the two parts of the second polysilicon to form isolation between the two parts of the second polysilicon;
the lateral width of the interlayer dielectric is larger than that of the first polysilicon positioned below the interlayer dielectric.
According to the trench structure of the shielded gate trench MOSFET, gate polycrystalline silicon positioned at the middle upper part of a trench is divided into a left part and a right part, and an interlayer medium is filled between the two parts. By dividing the formed two parts of grid polysilicon, the transverse width of the grid polysilicon is reduced, thereby reducing Cgs in parallel connection.
Drawings
FIGS. 1 to 9 are schematic views of the process steps of the present invention.
FIG. 10 is a cross-sectional gate-source capacitance parameter diagram of the inventive structure and a conventional structure.
FIG. 11 is a flow chart of the process steps of the present invention.
Description of the reference numerals
1 is an epitaxial layer, 2 is a first dielectric layer, 3 is a first polysilicon (shield gate), 4 is a heavily doped substrate, 5 is a drain, 6 is a second dielectric layer, 7 is a third dielectric layer (gate dielectric layer), 8 is a second polysilicon (gate), 9 is an interlayer dielectric, 10 is a well, and 11 is a source region.
Detailed Description
The following detailed description of the present invention is given with reference to the accompanying drawings, and the technical solution of the present invention is clearly and completely described, but the present invention is not limited to the following embodiments. It is to be understood that the embodiments described are only a few embodiments of the present invention, and not all embodiments. Advantages and features of the present invention will become apparent from the following description and from the claims. It is noted that the drawings are in greatly simplified form and that non-precision ratios are used for convenience and clarity only to aid in the description of the embodiments of the invention. All other embodiments obtained by a person skilled in the art without making any inventive step are within the scope of protection of the present invention.
It is to be understood that the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity, and the same reference numerals denote the same elements throughout. It will be understood that when an element or layer is referred to as being "on" …, "adjacent to …," "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on …," "directly adjacent to …," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.
In order to make the technical means, the creation characteristics, the achievement purposes and the effects of the invention easy to understand, the invention is further explained below by combining the specific drawings.
As shown in fig. 9, the trench structure of the shielded gate trench MOSFET of the present invention includes an upper portion and a lower portion, wherein the shielded gate structure is located at the middle lower portion of the trench, and the gate structure of the MOSFET is located above the shielded gate structure.
The shielding gate structure is composed of a first dielectric layer such as silicon oxide and first polysilicon, the first dielectric layer forms an insulating isolation layer between the first polysilicon and the inner wall of the trench, the first polysilicon is wrapped in the trench in a U shape, and a second dielectric layer is arranged above the first polysilicon and can be made of silicon oxide.
The grid structure is positioned above the shielding grid structure and is isolated from the shielding grid structure by the second dielectric layer. The grid structure is composed of two parts of second polysilicon which are arranged in the left and right directions at the upper part in the groove. The two parts of second polysilicon are respectively positioned at two sides of the groove close to the inner wall of the groove; the second polysilicon is isolated from the inner wall of the trench by a third dielectric layer, such as a silicon oxide film, serving as a gate dielectric layer.
And filling the groove with an interlayer medium, wherein the interlayer medium is positioned in the groove between the two parts of the second polysilicon to form isolation between the two parts of the second polysilicon.
The groove is positioned in an epitaxial layer of the semiconductor substrate, a well region and a source region of the MOSFET are also arranged in the epitaxial layer at two sides of the outer part of the groove, and a channel region of the MOSFET is formed in the well region when the MOSFET works. The source region is above the well region.
Other structures such as metal layer contact holes are consistent with the traditional groove type MOSFET, and are not described again.
The invention is realized by adopting the following process method of one embodiment, and synchronously refers to the attached drawings 1-9:
step one, a silicon substrate is provided, which can also be a semiconductor substrate made of other materials, and the silicon substrate has a front surface and a back surface (or a back surface). The reverse side of the silicon substrate is used as a drain region of the MOSFET; forming an epitaxial layer on the front surface of the silicon substrate, and etching the epitaxial layer to form a groove; then, a first dielectric layer is deposited in the groove, for example, silicon oxide is attached to the inner wall and the bottom of the groove, and then the groove is filled with first polysilicon.
And step two, etching back the first polysilicon in the groove to enable the top surface of the first polysilicon remained in the groove to be positioned in the middle position of the depth of the groove, namely filling the depth of the groove to a half position. And forming a shielding grid by the first polysilicon remained after etching.
And step three, etching the first dielectric layer on the inner wall of the groove, removing the first dielectric layer on the inner wall of the groove above the top surface of the reserved first polysilicon, and over-etching the first dielectric layer on the inner wall of the groove to enable the top surface of the first dielectric layer on the inner wall of the groove to be lower than the top surface of the reserved first polysilicon to form a convex shape.
And fourthly, depositing a second dielectric layer, such as silicon oxide, in the etched groove. And the second dielectric layer is filled in the residual space of the groove.
And fifthly, etching back the second dielectric layer in the groove, wherein a certain thickness is reserved on the second dielectric layer etched back to the top of the first polysilicon, and the reserved second dielectric layer is used as effective isolation between the shielding gate and a subsequent gate.
And step six, forming a third dielectric layer, such as silicon oxide, on the inner wall of the groove by adopting a thermal oxidation method. And the third dielectric layer is attached to the side wall of the residual space in the groove and used as a gate dielectric layer.
And step seven, depositing a second polysilicon layer, wherein the second polysilicon layer covers the inner wall and the bottom of the groove and reaches a certain thickness to meet the requirement of serving as the grid of the MOSFET.
And step eight, etching back the deposited second polycrystalline silicon layer, removing the second polycrystalline silicon layer at the bottom of the groove and on the surface of the substrate, and only keeping the second polycrystalline silicon layer on the left side wall and the right side wall in the groove, thereby forming a grid of the left part and the right part. The two parts of grid electrodes are opposite and vertical from left to right, and an accommodating space is formed between the two parts of grid electrodes.
And step nine, depositing an interlayer medium in the groove to fill the groove with the interlayer medium.
The interlayer dielectric completely fills the remaining accommodating space between the left gate and the right gate in the trench. After the interlayer dielectric is formed, the subsequent conventional process is also included, including trap injection, source region injection, contact hole formation and front metal deposition to form a front electrode; and forming the drain electrode of the MOSFET after the back surface of the semiconductor substrate is thinned.
Comparing the structure of the invention with the traditional structure, as shown in fig. 10, the gate-source capacitance is calculated, in the figure, t0 is the distance from the central line of the trench to the inner wall of the trench, t1 is the thickness of the left and right gates, and epsilon ox is the dielectric constant of the gate dielectric layer.
Then the gate-source capacitance CgsA of the existing structure is calculated as follows:
CgsA＝Cgs1(t0-t1,εox)+Cgs2(t1,εox)；
the gate-source capacitance CgsB of the structure of the invention is as follows:
CgsB＝Cgs3(t1,εox)；
the difference between the two:
ΔCgs≈CgsA-CgsB＞0。
by the structure of the invention, the transverse width of the grid is reduced, thereby reducing the Cgs connected in parallel.
The above are merely preferred embodiments of the present invention, and are not intended to limit the present invention. Various modifications and alterations to this invention will become apparent to those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims (14)

1. A process method for a trench structure of a shielded gate trench MOSFET is characterized by comprising the following steps: comprises the following steps:
providing a semiconductor substrate, wherein the semiconductor substrate is provided with a front surface and a back surface; the reverse side of the semiconductor substrate is used as a drain region of the MOSFET; forming an epitaxial layer on the front surface of the semiconductor substrate, and etching the epitaxial layer to form a groove; then depositing a first dielectric layer in the groove to be attached to the inner wall and the bottom of the groove, and then filling the groove with first polysilicon;
step two, carrying out back etching on the first polysilicon in the groove to enable the top surface of the first polysilicon reserved in the groove to be positioned in the middle of the depth of the groove;
etching the first dielectric layer on the inner wall of the groove, removing the first dielectric layer on the inner wall of the groove above the top surface of the reserved first polysilicon, and over-etching the first dielectric layer on the inner wall of the groove to ensure that the top surface of the first dielectric layer on the inner wall of the groove is lower than the top surface of the reserved first polysilicon;
depositing a second dielectric layer in the etched groove, wherein the second dielectric layer fills the residual space of the groove;
fifthly, back etching is carried out on the second dielectric layer in the groove;
depositing a third dielectric layer in the groove, wherein the third dielectric layer is attached to the side wall of the residual space in the groove;
step seven, depositing a second polycrystalline silicon layer;
eighthly, etching back the deposited second polycrystalline silicon layer;
and step nine, depositing an interlayer medium in the groove to fill the groove with the interlayer medium.
2. The process of fabricating a trench structure for a shielded gate trench MOSFET of claim 1 further comprising: in the first step, the first dielectric layer is an insulating dielectric layer.
3. The process of fabricating a trench structure for a shielded gate trench MOSFET of claim 2 further comprising: the first dielectric layer is a silicon oxide layer.
4. The process of fabricating a trench structure for a shielded gate trench MOSFET of claim 1 further comprising: in the second step, after the first polysilicon is etched back, the retained first polysilicon is used as a shielding gate of the trench MOFET.
5. The process of fabricating a trench structure for a shielded gate trench MOSFET of claim 1 further comprising: in the third step, after the first dielectric layer is over-etched, the first dielectric layers on two sides of the polysilicon in the middle of the lower part of the trench are lower than the first polysilicon, so that two containing spaces are formed between two sides of the first polysilicon and the inner wall of the trench.
6. The process of fabricating a trench structure for a shielded gate trench MOSFET of claim 1 further comprising: in the fourth step, the second dielectric layer is an insulating dielectric layer and is used as the isolation between the first polysilicon and the second polysilicon.
7. The process of fabricating a trench structure for a shielded gate trench MOSFET of claim 6 further comprising: in the fourth step, the second dielectric layer is a silicon oxide layer or a silicon nitride layer.
8. The process of fabricating a trench structure for a shielded gate trench MOSFET of claim 1 further comprising: in the fifth step, when the second dielectric layer is etched back, the second dielectric layer in the groove is removed by etching back, and the second dielectric layer with a certain thickness is reserved above the first polysilicon; the remaining thickness provides effective electrical isolation between the second polysilicon and the first polysilicon.
9. The process of fabricating a trench structure for a shielded gate trench MOSFET of claim 1 further comprising: in the sixth step, the third dielectric layer is an insulating dielectric layer and is used as the isolation between the second polysilicon and the epitaxy.
10. The process of fabricating a trench structure for a shielded gate trench MOSFET of claim 9 further comprising: the third dielectric layer is silicon oxide.
11. The process of fabricating a trench structure for a shielded gate trench MOSFET of claim 1 further comprising: in the seventh step, the deposited second polysilicon is formed to a certain thickness in the trench, but the trench is not filled, and the thickness of the second polysilicon deposited on the inner wall of the trench meets the requirement of the lateral width of the gate.
12. The process of fabricating a trench structure for a shielded gate trench MOSFET of claim 1 further comprising: in the eighth step, after the second polysilicon is etched back, the second polysilicon at the bottom of the trench is etched and removed, only the second polysilicon attached to the inner walls of the two sides of the trench is remained, and the second polysilicon on the surface of the semiconductor substrate is completely removed.
13. The process of fabricating a trench structure for a shielded gate trench MOSFET of claim 1 further comprising: in the ninth step, an interlayer medium is deposited in the groove, and the second polysilicon is positioned at two sides of the interlayer medium to form a two-piece groove grid; after the interlayer dielectric is formed, well injection, source region injection, contact hole formation and front metal deposition are further included to form a front electrode; and forming the drain electrode of the MOSFET after the back surface of the semiconductor substrate is thinned.
14. A trench structure of a shielded gate trench type MOSFET is characterized in that: the method comprises the following steps:
providing a semiconductor substrate, and forming a lightly doped epitaxial layer of a first conduction type on the semiconductor substrate;
forming a groove in the epitaxial layer, wherein the groove is provided with a shielding grid structure and a grid structure of the MOSFET, and an upper structure and a lower structure are formed in the groove;
the shielding gate structure is positioned at the lower part of the groove and consists of a first dielectric layer and first polycrystalline silicon which are positioned in the groove, the first dielectric layer forms an isolation layer between the first polycrystalline silicon and the inner wall of the groove, and the first polycrystalline silicon is wrapped in the groove in a U shape;
the grid structure is positioned above the shielding grid structure and is isolated from the shielding grid structure by a second dielectric layer; the grid structure consists of two parts of second polycrystalline silicon, and the two parts of second polycrystalline silicon are respectively positioned at two sides of the groove close to the inner wall of the groove; the second polysilicon is isolated from the inner wall of the groove by a third dielectric layer;
the groove is filled with an interlayer medium, and the interlayer medium is positioned in the groove between the two parts of the second polysilicon to form isolation between the two parts of the second polysilicon;
the lateral width of the interlayer dielectric is larger than that of the first polysilicon positioned below the interlayer dielectric.
CN202210514547.8A 2022-05-11 2022-05-11 Trench structure of shielded gate trench type MOSFET and forming method Pending CN115084248A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117059658A (en) * 2023-10-09 2023-11-14 深圳市锐骏半导体股份有限公司 Trench structure of shielding gate trench semiconductor device, manufacturing method and simulation method
CN117637480A (en) * 2023-11-13 2024-03-01 中晶新源(上海)半导体有限公司 SGT-MOSFET device and manufacturing process thereof

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117059658A (en) * 2023-10-09 2023-11-14 深圳市锐骏半导体股份有限公司 Trench structure of shielding gate trench semiconductor device, manufacturing method and simulation method
CN117059658B (en) * 2023-10-09 2024-02-20 深圳市锐骏半导体股份有限公司 Trench structure of shielding gate trench semiconductor device, manufacturing method and simulation method
CN117637480A (en) * 2023-11-13 2024-03-01 中晶新源(上海)半导体有限公司 SGT-MOSFET device and manufacturing process thereof
CN117637480B (en) * 2023-11-13 2024-05-28 中晶新源(上海)半导体有限公司 Shielded gate trench MOSFET device and manufacturing process thereof

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