CN115078968A - Chip test circuit, self-test chip and chip test system - Google Patents
Chip test circuit, self-test chip and chip test system Download PDFInfo
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- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2855—Environmental, reliability or burn-in testing
- G01R31/286—External aspects, e.g. related to chambers, contacting devices or handlers
- G01R31/2868—Complete testing stations; systems; procedures; software aspects
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- G—PHYSICS
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- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2855—Environmental, reliability or burn-in testing
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- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2855—Environmental, reliability or burn-in testing
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- G01R31/2879—Environmental, reliability or burn-in testing related to electrical or environmental aspects, e.g. temperature, humidity, vibration, nuclear radiation related to electrical aspects, e.g. to voltage or current supply or stimuli or to electrical loads
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Abstract
The embodiment of the application provides a chip test circuit, a self-test chip and a chip test system, wherein the chip test circuit comprises: the device comprises a control module, a mode generating module, an excitation generating module and a detecting module. The control module generates an excitation source and a test mode signal according to a test signal sent by external equipment, the excitation generating module generates an excitation signal according to the excitation source and acts on an analog circuit module of a tested chip, the mode generating module generates a test mode according to the test mode signal and acts on a digital circuit module of the tested chip, the detection module can obtain a first running state according to a first test result of the digital circuit module and obtain a second running state according to a second test result of the analog circuit module, so that the aging test on the tested chip is automatically completed and a test result is obtained according to the test signal input by the external equipment, the test complexity is simplified, and the test efficiency is improved.
Description
Technical Field
The embodiment of the application relates to the technical field of chip testing, in particular to a chip testing circuit, a self-testing chip and a chip testing system.
Background
To meet reliability requirements, integrated circuit chips must be subjected to Burn-in testing before being shipped from a factory. The aging test is to apply certain stress, such as current, voltage, temperature and the like, to the chip within a certain time to remove defective products and ensure the reliability of the products.
As shown in fig. 1, a conventional Burn-in test system includes an MCU/ASIC controller, in which Burn-in control software is run, and the MCU/ASIC controller is in communication connection with a chip to be tested through an I/O communication signal line to output a control signal to control the chip to be tested to complete a test.
However, in the conventional burn-in test system, complicated test control software and hardware board level systems need to be developed, and high manpower and material resources are invested.
Disclosure of Invention
In view of the above problems, embodiments of the present application provide a chip testing circuit, a self-testing chip, and a chip testing system, which solve the problem that a chip burn-in testing system needs to develop complex test control software and a hardware board-level system, and simplify the chip burn-in testing system.
In a first aspect of an embodiment of the present application, a chip test circuit is provided, including: the device comprises a control module, a mode generating module, an excitation generating module and a detecting module;
the control module is used for receiving a test signal from external equipment; generating an excitation source and a test mode signal according to the test signal; outputting the excitation source to the excitation generating module and outputting the test pattern signal to the pattern generating module;
the mode generating module is used for receiving the test mode signal, generating a test mode according to the test mode signal and outputting the test mode to the digital circuit module of the tested chip;
the excitation generating module is used for receiving the excitation source, generating an excitation signal according to the excitation source and outputting the excitation signal to the analog circuit module of the tested chip;
the detection module is used for receiving a first test result from the digital circuit module of the tested chip and a second test result from the analog circuit module of the tested chip; obtaining a first running state of the digital circuit module according to the first test result, and obtaining a second running state of the analog circuit module according to the second test result; outputting the first operating state and the second operating state to the external device.
Optionally, the chip test circuit further includes:
the test design module is connected between the control module and the chip to be tested;
the control module is also used for generating a control signal according to the test signal and outputting the control signal to the test design module;
the test design module is used for receiving the control signal, generating a test design debugging signal according to the control signal and testing the chip to be tested according to the test design debugging signal;
the detection module is further configured to receive a third operating state from the chip under test and output the third operating state to the external device.
Optionally, the test design module includes a test design controller and a test design control circuit;
the test design controller is used for receiving the control signal, generating a test design debugging signal according to the control signal and outputting the test design debugging signal to the test design control circuit;
and the test design control circuit is used for receiving the test design debugging signal and testing the chip to be tested according to the test design debugging signal.
Optionally, the detecting module obtains a first operating state of the digital circuit module according to the first test result, and further includes:
the detection module compares the first test result with a preset first result; and obtaining the first running state under the condition that the first test result is matched with the preset first result.
Optionally, the detecting module obtains a second operating state of the analog circuit module according to the second test result, and further includes:
the detection module compares the second test result with a preset second result; and obtaining the second running state under the condition that the second test result is matched with the preset second result.
Optionally, the test pattern generated by the pattern generation module according to the test pattern signal at least includes: one of an aging test mode, an automatic aging test mode, an aging test design debug mode, and an aging function debug mode is not activated.
Optionally, the control module includes a plurality of input terminals, each of which is configured to receive a high level signal or a low level signal output by the external device, and a plurality of the high level signals or the low level signals are combined into a level signal sequence according to a receiving order, and the level signal sequence is determined as the test signal.
In a second aspect of the embodiments of the present application, there is further provided a self-test chip, including a chip to be tested, and the chip test circuit according to any one of the first aspect of the embodiments of the present application, where the chip test circuit is disposed inside the chip to be tested.
An embodiment of the present application further provides a chip testing system, including: an upper computer and at least one self-test chip as described in the second aspect of the embodiments of the present application;
the upper computer is connected with the control module and the detection module of the self-test chip;
the upper computer is used for outputting a test signal to the control module; receiving the running state of the self-testing chip sent by the detection module; the operating states include at least a first operating state of a digital circuit module of the self-test chip, a second operating state of an analog circuit module of the self-test chip, and a third operating state of the self-test chip.
According to the technical scheme, the control module generates the excitation source and the test mode signal according to the test signal sent by the external equipment, the excitation generating module generates the excitation signal according to the excitation source and acts on the analog circuit module of the tested chip, the mode generating module generates the test mode according to the test mode signal and acts on the digital circuit module of the tested chip, and the detecting module can obtain the first running state according to the first test result of the digital circuit module and obtain the second running state according to the second test result of the analog circuit module. Therefore, the aging test of the tested chip is automatically completed and the test result is obtained according to the test signal input by the external equipment, complex test control software and a hardware board-level system do not need to be developed aiming at the tested chip, the test complexity is simplified, and the test efficiency is improved.
The foregoing description is only an overview of the technical solutions of the embodiments of the present application, and in order that the technical means of the embodiments of the present application can be clearly understood, the embodiments of the present application are specifically described below in order to make the foregoing and other objects, features, and advantages of the embodiments of the present application more clearly understandable.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings without creative efforts.
FIG. 1 is a schematic diagram of a prior art burn-in test system;
FIG. 2 is a schematic diagram of a chip test circuit according to an embodiment of the present application;
FIG. 3 is a schematic diagram of another chip test circuit according to an embodiment of the present application;
FIG. 4 is a schematic diagram of a self-test chip according to an embodiment of the present application;
fig. 5 is a schematic diagram of a chip testing system according to an embodiment of the present application.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs; the terminology used in the description of the application herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application; the terms "comprising" and "having," and any variations thereof, in the description and claims of this application and the description of the figures are intended to cover non-exclusive inclusions.
Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the application. The appearances of the phrase "an embodiment" in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. It is explicitly and implicitly understood by one skilled in the art that the embodiments described herein may be combined with other embodiments.
Furthermore, the terms "first," "second," and the like in the description and claims of the present application or in the above-described drawings are used for distinguishing between different objects and not necessarily for describing a particular sequential order, and may explicitly or implicitly include one or more of the features.
In the description of the present application, it should be noted that, unless otherwise explicitly stated or limited, the terms "mounted," "connected," and "connected" are to be interpreted broadly, for example, that "connected" or "connection" of a circuit structure may refer to an electrical connection or a signal connection, in addition to a physical connection, for example, a direct connection, i.e., a physical connection, or an indirect connection via at least one element therebetween, as long as the circuit is connected, or communication between two elements is achieved; signal connection in addition to signal connection through circuitry, may also refer to signal connection through a media medium, such as radio waves. The specific meaning of the above terms in the present application can be understood in a specific case by those of ordinary skill in the art.
In order to make the technical solutions better understood by those skilled in the art, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings.
The production process of the integrated circuit chip has certain characteristics of complexity, precision and the like, so that the integrated circuit chip can leave defects in the manufacturing process, and for some chips with strict reliability requirements, in order to avoid the problem that the chip fails early when applied to a circuit, the chip is generally required to be subjected to an aging test before leaving a factory.
For example, for a vehicle-specification chip, an aging test is performed before the chip is delivered from a factory, so that a problem chip can be found and screened out in time, and the high reliability of a final product is ensured. Among them, High Temperature Operating Life (HTOL) is used in the aging test to evaluate the endurance of the chip under super-heat for a period of time.
In the conventional Burn-in test system, the chip to be tested is usually connected to the MCU/ASIC controller through an I/O communication signal line, and the MCU/ASIC controller runs Burn in control software for outputting a test signal to test the chip to be tested. It can be seen that in the conventional burn-in test system, professional test equipment needs to be used, corresponding test control software needs to be developed according to the functions of the tested chips, and the test equipment is damaged when a high-temperature operation life test is performed, which causes the loss of the test equipment to also increase significantly with the number of the tested chips.
Based on the above-mentioned defects of the conventional burn-in test system, the embodiment of the present application provides a chip test circuit 1, which can automatically complete the burn-in test of a tested chip and obtain a test result according to a test signal input by an external device, without developing a complex test control software and hardware board-level system for the tested chip. It should be noted that the chip under test generally includes the digital circuit module 80 and the analog circuit module 70, and the digital circuit module 80 and the analog circuit module 70 need to be tested separately during chip testing.
Referring to fig. 2, the chip test circuit 1 of the present embodiment may include: a control module 10, a pattern generation module 30, an excitation generation module 20 and a detection module 40.
The control module 10 is configured to receive a test signal from an external device; generating an excitation source and a test mode signal according to the test signal; the stimulus source is output to the stimulus generation module 20, and the test pattern signal is output to the pattern generation module 30.
Specifically, the control module 10 may include a plurality of input terminals, as shown in fig. 2, the control module 10 includes input terminals I/O1 to I/Om, the input terminals I/O1 to I/Om are connected to the external device, each of the input terminals is configured to receive a high level signal or a low level signal output by the external device, the plurality of high level signals or the plurality of low level signals are combined into a level signal sequence according to a receiving sequence, and the level signal sequence is determined as the test signal.
For example, assuming that the input terminals include I/O1, I/O2, I/O3 and I/O4, if the external device outputs low level 0 to the control module 10 through I/O1, outputs high level 1 to the control module 10 through I/O2, outputs high level 1 to the control module 10 through I/O3, and outputs high level 1 to the control module 10 through I/O4, it is said that the control module 10 combines the level signals received by 4 input terminals, and the obtained level signal sequence is 0111, that is, the test signal received by the control module 10 is 0111.
After receiving the test signal, the control module 10 respectively generates and converts an excitation source to be sent to the excitation generating module 20 and a test pattern signal to be sent to the pattern generating module 30 according to the test signal. The specific conversion manner may be, for example, conversion according to a preset conversion correspondence, or direct forwarding, which is not specifically limited in this embodiment.
After receiving the test mode signal, the mode generating module 30 generates a test mode according to the test mode signal, and outputs the test mode to the digital circuit module 80 of the chip under test.
Wherein the test patterns are generated according to different chip test requirements. Optionally, the test pattern generated by the pattern generating module 30 according to the test pattern signal at least includes: one of an aging test mode, an automatic aging test mode, an aging test design debug mode, and an aging function debug mode is not activated.
After receiving the excitation source, the excitation generating module 20 generates an excitation signal according to the excitation source, and outputs the excitation signal to the analog circuit module 70 of the chip under test. In this embodiment, the analog circuit module 70 may include one or more analog circuits, such as the analog circuit 1, the analog circuit n, and the analog circuit m. The excitation signal may include a square wave signal, a sine wave signal, a pulse signal, or the like, and the excitation generating module 20 may generate excitation signals of different forms according to the requirements of different analog circuits, which is not limited specifically herein.
After the tested chip completes the test according to the excitation signal and the test mode, the digital circuit module 80 outputs a first test result, and the analog circuit module 70 outputs a second test result. In practical applications, in the case that an external device inputs a test signal through a plurality of I/O input terminals, the first test result of the digital circuit block 80 may be output to the external device through a plurality of I/O output terminals, and similarly, the second test result of the analog circuit block 70 may also be output to the external device through a plurality of I/O output terminals. The external device obtains the operating state of each digital circuit in the digital circuit module 80 according to the output of different I/O output terminals, and obtains the operating state of each analog circuit in the analog circuit module 70.
The detection module 40 receives a first test result from the digital circuit module 80 of the chip under test and a second test result from the analog circuit module 70 of the chip under test; a first operation state of the digital circuit module 80 can be obtained according to the first test result, and a second operation state of the analog circuit module 70 can be obtained according to the second test result; outputting the first operating state and the second operating state to the external device.
It is understood that the first operating state and the second operating state may each include a state of abnormal operation or normal operation. Specifically, the detecting module 40 obtains the first operating state of the digital circuit module 80 according to the first test result, and further includes: the detection module 40 compares the first test result with a preset first result; and obtaining the first running state under the condition that the first test result is matched with the preset first result. The detecting module 40 obtains a second operating state of the analog circuit module 70 according to the second test result, and further includes: the detection module 40 compares the second test result with a preset second result; and obtaining the second running state under the condition that the second test result is matched with the preset second result.
In this embodiment, as shown in fig. 3, the chip test circuit 1 may further include: the test design module is connected between the control module 10 and the chip to be tested; the control module 10 is further configured to generate a control signal according to the test signal, and output the control signal to the test design module; and the test design module is used for receiving the control signal, generating a test design debugging signal according to the control signal and testing the tested chip according to the test design debugging signal.
Specifically, the test design module may include a test design controller 50 and a test design control circuit 60; the test design controller 50 is configured to receive the control signal, generate the test design debug signal according to the control signal, and output the test design debug signal to the test design control circuit 60; the test design control circuit 60 is configured to receive the test design debug signal, and test the chip under test according to the test design debug signal.
The test result of the tested chip is the third operating state of the tested chip, and the third operating state is also output to the detection module 40, so that the detection module 40 outputs the third operating state to the external device.
In one example, assuming 4 test patterns are defined using I/O0, I/O1, as shown in Table 1, the 4 test patterns may include: no Burn-in active Mode, Auto Burn-in Mode, Burn-in design Debug Mode, and Burn-in function Debug Mode are not enabled.
TABLE 1
| I/O0，I/O1 | Test mode |
| 00 | No Burn in active |
| 01 | Auto Burn in |
| 10 | Burn in DFT Debug Mode |
| 11 | Burn in FUNC Debug Mode |
Wherein, the aging test mode is not started, which means that the aging test is not entered. In the automatic burn-in test mode, an automatic round-robin test burn-in test design debugging mode and a burn-in function debugging mode alternately complete DFT (design For test) test and function test. The burn-in test design debugging mode is to control the digital circuit module 80 to test the analog circuit module 70, wherein n functional modes can be generated, each functional mode is run for m time, and the functional modes are debugged. The burn-in function debug mode is for testing and debugging the digital circuit block 80.
It should be noted that the present embodiment is not limited to adopt 4 test modes, the number of specific test modes may be configured according to different chips to be tested, and 2 may be defined by high and low level signals input by m I/O input terminals m A test mode is initiated.
In the chip test circuit 1 of this embodiment, the control module 10, the pattern generation module 30, the excitation generation module 20, and the detection module 40 are arranged, so that the control module 10 generates an excitation source and a test pattern signal according to a test signal sent by an external device, the excitation generation module 20 generates an excitation signal according to the excitation source and acts on the analog circuit module 70 of the chip to be tested, the pattern generation module 30 generates a test pattern according to the test pattern signal and acts on the digital circuit module 80 of the chip to be tested, and the detection module 40 can obtain a first operation state according to a first test result of the digital circuit module 80 and obtain a second operation state according to a second test result of the analog circuit module 70. Therefore, the aging test of the tested chip is automatically completed and the test result is obtained according to the test signal input by the external equipment, complex test control software and a hardware board-level system do not need to be developed aiming at the tested chip, the test complexity is simplified, and the test efficiency is improved.
As shown in fig. 4, an embodiment of the present application further provides a self-test chip, which includes a chip to be tested, and the chip test circuit 1 as described in the above embodiments, where the chip test circuit 1 is disposed inside the chip to be tested.
According to the self-testing chip, the chip testing circuit 1 is built in the tested chip, so that the tested chip and the chip testing circuit 1 can be designed and simulated at the same time, weak links of the tested chip in current and power consumption design can be found in time and modified before the tested chip is subjected to chip production through the simulation result of the chip testing circuit 1, and the reliability and the qualification rate of the chip can be improved.
As shown in fig. 5, an embodiment of the present application further provides a chip testing system, including: an upper computer and at least one self-test chip as described in the above embodiments; the upper computer is connected with the control module and the detection module of the self-test chip; the upper computer is used for outputting a test signal to the control module; receiving the running state of the self-testing chip sent by the detection module; the operating states include at least a first operating state of a digital circuit module of the self-test chip, a second operating state of an analog circuit module of the self-test chip, and a third operating state of the self-test chip.
In practical application, the number of the self-test chips in the chip test system may be multiple, as shown in fig. 5, the chip test system includes self-test chips 1 to 6, chip test circuits 1 to 6 as described in the above embodiments are provided inside each self-test chip, and an input end of each chip test circuit is connected to a test circuit board (not shown in the figure), so that the test circuit board can simultaneously perform burn-in test on the multiple self-test chips, and a test process and a test mode of each self-test chip are the same.
Therefore, the chip test system of the embodiment only needs one test circuit board, the upper computer inputs the control signal to the input end of the chip test circuit through the test circuit board, the aging test of the self-test chip is completed, complex test control software and hardware board-level systems do not need to be developed for the tested chip, the test complexity is simplified, the chip test system of the embodiment can support more chips to be in cascade connection and synchronous test, and the test efficiency is improved.
In the several embodiments provided in the present application, it should be understood that the disclosed system, apparatus and method may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative, and for example, a module or a unit may be divided into only one logical function, and may be implemented in other ways, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.
Each functional unit or module in the embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit may be implemented in the form of hardware, or may also be implemented in the form of a software functional unit.
The integrated unit, if implemented in the form of a software functional unit and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present application may be substantially implemented or contributed to by the prior art, or all or part of the technical solution may be embodied in a software product, which is stored in a storage medium and includes instructions for causing a computer device (which may be a personal computer, a server, a network device, or the like) or a processor (processor) to execute all or part of the steps of the method of the embodiments of the present application. And the aforementioned storage medium includes: various media capable of storing program codes, such as a usb disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk, or an optical disk.
The above embodiments are only used for illustrating the technical solutions of the present application, and not for limiting the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions in the embodiments of the present application.
Claims (9)
1. A chip test circuit, comprising: the device comprises a control module, a mode generation module, an excitation generation module and a detection module;
the control module is used for receiving a test signal from external equipment; generating an excitation source and a test mode signal according to the test signal; outputting the excitation source to the excitation generating module and outputting the test pattern signal to the pattern generating module;
the mode generating module is used for receiving the test mode signal, generating a test mode according to the test mode signal and outputting the test mode to the digital circuit module of the tested chip;
the excitation generating module is used for receiving the excitation source, generating an excitation signal according to the excitation source and outputting the excitation signal to the analog circuit module of the tested chip;
the detection module is used for receiving a first test result from the digital circuit module of the chip to be tested and a second test result from the analog circuit module of the chip to be tested; obtaining a first running state of the digital circuit module according to the first test result, and obtaining a second running state of the analog circuit module according to the second test result; outputting the first operating state and the second operating state to the external device.
2. The chip test circuit according to claim 1, further comprising:
the test design module is connected between the control module and the chip to be tested;
the control module is also used for generating a control signal according to the test signal and outputting the control signal to the test design module;
the test design module is used for receiving the control signal, generating a test design debugging signal according to the control signal and testing the chip to be tested according to the test design debugging signal;
the detection module is further configured to receive a third operating state from the chip under test and output the third operating state to the external device.
3. The chip test circuit according to claim 2, wherein the test design module comprises a test design controller and a test design control circuit;
the test design controller is used for receiving the control signal, generating a test design debugging signal according to the control signal and outputting the test design debugging signal to the test design control circuit;
the test design control circuit is used for receiving the test design debugging signal and testing the tested chip according to the test design debugging signal.
4. The chip test circuit according to claim 1, wherein the detection module obtains a first operating status of the digital circuit module according to the first test result, further comprising:
the detection module compares the first test result with a preset first result; and obtaining the first running state under the condition that the first test result is matched with the preset first result.
5. The chip test circuit according to claim 1, wherein the detection module obtains a second operating status of the analog circuit module according to the second test result, further comprising:
the detection module compares the second test result with a preset second result; and obtaining the second running state under the condition that the second test result is matched with the preset second result.
6. The chip test circuit according to claim 1, wherein the test pattern generated by the pattern generation module according to the test pattern signal at least comprises: one of an aging test mode, an automatic aging test mode, an aging test design debug mode, and an aging function debug mode is not activated.
7. The chip test circuit according to claim 1, wherein the control module comprises a plurality of input terminals, each of the input terminals is configured to receive a high level signal or a low level signal output from the external device, the plurality of high level signals or the plurality of low level signals are combined into a level signal sequence according to a receiving order, and the level signal sequence is determined as the test signal.
8. A self-test chip, comprising a chip under test, and a chip test circuit as claimed in any one of claims 1 to 7, the chip test circuit being disposed inside the chip under test.
9. A chip test system, comprising: a host computer and at least one self-test chip as claimed in claim 8;
the upper computer is connected with the control module and the detection module of the self-test chip;
the upper computer is used for outputting a test signal to the control module; receiving the running state of the self-testing chip sent by the detection module; the operating states include at least a first operating state of a digital circuit module of the self-test chip, a second operating state of an analog circuit module of the self-test chip, and a third operating state of the self-test chip.
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