CN115033172A - Storage module control method, device, equipment and storage medium - Google Patents
Storage module control method, device, equipment and storage medium Download PDFInfo
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Abstract
The application discloses a storage module management and control method, device, equipment and storage medium, which relate to the technical field of computers and comprise the following steps: sending a configuration information acquisition instruction to the dual in-line memory module so that the dual in-line memory module reads target configuration information from the register after receiving the configuration information acquisition instruction; receiving target configuration information sent by a dual-in-line storage module, and carrying out corresponding verification operation on the target configuration information to obtain a verification result; and sending a corresponding signal control instruction to the power supply switching chip based on the verification result so that the power supply switching chip provides corresponding voltage to the dual in-line type storage module based on the signal control instruction. According to the method and the device, the configuration information of the dual in-line storage module is used for checking, and the corresponding signal control instruction is sent to the power supply switching chip according to the checking result, so that the current state is controlled by controlling the voltage provided to the dual in-line storage module, and the data safety is improved.
Description
Technical Field
The present invention relates to the field of computer technologies, and in particular, to a method, an apparatus, a device, and a storage medium for managing and controlling a storage module.
Background
Since computers have memories in von neumann architectures, memories and hard disks have been very important in computers. Unlike a large-capacity hard disk, the memory has a remarkable access speed, but cannot store stored information after power failure, so that the memory plays a role of a transfer station in the long-term development process of computer hardware. Like other hardware, the memory follows the morgan law, from the appearance of the most ancient SIMM (single in-line memory module) to the DDR (Double Data Rate SDRAM), and then iteration is performed based on the DDR, and the memory standard and specification change greatly. With the rapid development of information technology, the memory technology has been developed to the era of DDR5 (a computer memory specification). The DDR5 first child memory interface chip RCD (Residual Current Device, register clock driver)/DB (data buffer), the highest rate supported is 4800Mbps (megabits per second), which is 1.5 times of the highest rate of DDR4 (a memory specification); the interface voltage is as low as 1.1V, and the energy consumption is lower; by adopting an innovative signal calibration protocol and an innovative equalization technology, the integrity of the memory signal is greatly improved.
Compared with the DDR4 memory module, the DDR5 memory module is innovative in architecture, and requires other dedicated chips in addition to the memory particles and the memory interface chip. DDR5 manufacturers have first introduced three supporting chips, namely, DDR5 PMIC (Power Management IC), TS (Transparent substrate chip) and SPD Hub (negative protective device Hub), which can provide auxiliary functions such as multi-channel Power supply and Management, multi-point temperature detection, I3C (advanced Inter Integrated Circuit) serial bus and routing for DDR5 memory modules. The matched chips and the memory interface chip together assist the DDR5 memory module to realize comprehensive improvement in the aspects of speed, capacity, energy conservation, reliability and the like, and meet the higher requirements of a new generation of server, desktop computer and portable computer on a memory system.
The emerging I3C transport protocol has multiple points: the I3C bus may support a multi-master (multi-master); the I3C bus is compatible with legacy I2C devices; supporting soft interrupts; lower power consumption than the I2C bus; the speed is faster, and the device can support 12.5 MHZ. Therefore, the application of the I3C technology to the DDR5 is a necessary trend.
MCTP (Management Component Transport Protocol) is a "data link layer" Protocol established on a physical layer basis and independent of mutual communication between intelligent devices in computers of various media, and is convenient for platform Management developers to rapidly and economically develop and deploy a platform Management subsystem accessible to CIM (Common Information Model). MCTP defines a transport layer protocol independent of the physical medium, the link layer is defined in the series of MCTP binding protocols, and the supported physical medium types include: PCIe (peripheral component interconnect express, a high-speed Serial computer extension Bus standard), SMBus (System Management Bus), USB (Universal Serial Bus), BT (Block Transfer), I3C, and the like.
In the existing solution, a BMC (Baseboard Management Controller) is used as a master (master device), and acquires relevant information of the DIMM through an SMBus, including device measurement point temperature, power state, software configuration information, and the like. In this process, a conventional design is to add a level shift chip (level shift), mainly to solve the problem of the level difference between the BMC and the DIMM. Because the two parts are not completely coupled, information cannot be shared, and if the DIMM is not in the white list of the system configuration, the CPLD (Complex Programmable Logic Device) still uses the VR Controller to normally supply power to the DIMM at this time. Meanwhile, the information communication between the BMC and the DIMM cannot be cut off, and huge hidden danger is caused to the information safety of the system. In the whole topological link, only one master can be provided for BMC, and the transmission rate of data on the link is limited by SMBus, usually about 400K. The whole link is designed to be an open circuit, and when data abnormality occurs at the DIMM end, the maximum response of the BMC is that the SMBus address cannot be searched, and no further response can be carried out.
Disclosure of Invention
In view of the above, the present invention provides a method, an apparatus, a device and a storage medium for managing and controlling a storage module, which can improve data security. The specific scheme is as follows:
in a first aspect, the present application discloses a memory module management and control method, applied to a complex programmable logic device, including:
sending a configuration information acquisition instruction to a dual in-line memory module so that the dual in-line memory module reads target configuration information from a register after receiving the configuration information acquisition instruction;
receiving the target configuration information sent by the dual in-line storage module, and carrying out corresponding verification operation on the target configuration information to obtain a verification result;
and sending a corresponding signal control instruction to a power supply switching chip based on the verification result so that the power supply switching chip provides corresponding voltage to the dual in-line memory module based on the signal control instruction.
Optionally, the receiving the target configuration information sent by the dual inline memory module and performing a corresponding checking operation on the target configuration information to obtain a checking result includes:
receiving frame data which is sent by the dual in-line storage module and obtained by converting the target configuration information through a first preset format;
and carrying out corresponding checking operation on the frame data to obtain a checking result.
Optionally, the performing a corresponding checking operation on the frame data to obtain a checking result includes:
reading the target configuration information in the frame data;
matching the target configuration information with information stored in a local preset white list;
when the information corresponding to the target configuration information is matched in the preset white list, the verification result is that the verification is passed;
and when the information corresponding to the target configuration information is not matched in the preset white list, the verification result is verification failure.
Optionally, the sending a corresponding signal control instruction to the power switching chip based on the verification result includes:
when the verification result is that the verification is passed, sending the signal control instruction for improving the target signal to the power supply switching chip;
and when the verification result is verification failure, sending the signal control instruction for reducing the target signal to the power supply switching chip.
Optionally, the sending a corresponding signal control instruction to a power switching chip based on the verification result so that the power switching chip provides a corresponding voltage to the dual inline memory module based on the signal control instruction includes:
sending the signal control instruction for improving the target signal to the power switching chip so that the power switching chip can provide a preset voltage for the dual in-line memory module; the preset voltage is the voltage of the dual in-line type memory module during normal work;
and sending the signal control instruction for reducing the target signal to the power switching chip so that the power switching chip stops supplying voltage to the dual in-line memory module.
Optionally, after the sending a corresponding signal control instruction to the power switching chip based on the verification result so that the power switching chip provides a corresponding voltage to the dual inline memory module based on the signal control instruction, the method further includes:
converting the frame data passing the verification through a second preset format to obtain converted frame data;
and sending the converted frame data to a substrate management controller or a central processing unit through a wiring selector switch, so that when the signal control instruction for improving the target signal is sent to the power switching chip in the verification process, the substrate management controller or the central processing unit performs data interaction with the dual in-line type storage module through an upgraded system management bus and performs corresponding preset processing operation when monitoring that the corresponding data changes.
Optionally, after sending the corresponding signal control instruction to the power switching chip based on the verification result, the method further includes:
and receiving feedback information corresponding to the signal control instruction, which is returned by the power supply switching chip after the signal control instruction is received.
In a second aspect, the present application discloses a memory module management and control apparatus, which is applied to a complex programmable logic device, and includes:
the first instruction sending module is used for sending a configuration information acquisition instruction to the dual in-line type storage module so that the dual in-line type storage module reads target configuration information from a register after receiving the configuration information acquisition instruction;
the information receiving module is used for receiving the target configuration information sent by the dual in-line storage module;
the information checking module is used for carrying out corresponding checking operation on the target configuration information to obtain a checking result;
and the second instruction sending module is used for sending a corresponding signal control instruction to the power supply switching chip based on the verification result so that the power supply switching chip can provide corresponding voltage to the dual in-line storage module based on the signal control instruction.
In a third aspect, the present application discloses an electronic device, comprising:
a memory for storing a computer program;
a processor for executing the computer program to implement the steps of the memory module managing and controlling method as disclosed in the foregoing.
In a fourth aspect, the present application discloses a computer readable storage medium for storing a computer program; wherein the computer program, when executed by a processor, implements a storage module management and control method as disclosed in the foregoing.
Therefore, the application provides a storage module management and control method, which comprises the following steps: sending a configuration information acquisition instruction to a dual in-line memory module so that the dual in-line memory module reads target configuration information from a register after receiving the configuration information acquisition instruction; receiving the target configuration information sent by the dual in-line storage module, and performing corresponding verification operation on the target configuration information to obtain a verification result; and sending a corresponding signal control instruction to a power supply switching chip based on the verification result so that the power supply switching chip provides corresponding voltage to the dual in-line memory module based on the signal control instruction. Therefore, the validity of the dual in-line type memory module is verified by using the acquired configuration information of the dual in-line type memory module, and then the corresponding signal control instruction is sent to the power supply switching chip according to the verification result, so that the power supply switching chip provides corresponding voltage for the dual in-line type memory module based on the signal control instruction, the use state of the dual in-line type memory module is controlled, and the data safety is improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
FIG. 1 is a flow chart of a memory module management and control method disclosed in the present application;
FIG. 2 is a schematic diagram of a management component transport protocol method;
FIG. 3 is a diagram illustrating a method for monitoring the status of a dual inline memory module;
FIG. 4 is a schematic diagram of a dual inline memory module control method disclosed herein;
FIG. 5 is a flowchart of a specific memory module management and control method disclosed herein;
FIG. 6 is a flowchart of a specific memory module management and control method disclosed herein;
fig. 7 is a schematic structural diagram of a storage module management and control apparatus provided in the present application;
fig. 8 is a block diagram of an electronic device provided in the present application.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Currently, the BMC is used as a master to acquire relevant information of the DIMM through the SMBus, including device measurement point temperature, power state, software configuration information, and the like. In this process, a conventional design is to add a level conversion chip, mainly to solve the problem of level difference between the BMC and the DIMM. Because the two parts are not completely coupled, information cannot be shared, and if the DIMM is not in the white list of the system configuration, the CPLD still uses the VR Controller to normally supply power to the DIMM at this time. Meanwhile, the information communication between the BMC and the DIMM cannot be cut off, and huge hidden danger is caused to the information safety of the system. In the whole topological link, only one master can be provided for BMC, and the transmission rate of data on the link is limited by SMBus, usually about 400K. The whole link is designed to be an open circuit, when data abnormality occurs at the end of the DIMM, the maximum response of the BMC is that an SMBus address cannot be searched, and further response cannot be carried out. Therefore, the storage module management and control method can improve the data security.
The embodiment of the invention discloses a storage module control method, which is applied to a complex programmable logic device and is shown in figure 1, and the method comprises the following steps:
step S11: and sending a configuration information acquisition instruction to the dual in-line memory module so that the dual in-line memory module reads the target configuration information from the register after receiving the configuration information acquisition instruction.
In this embodiment, a configuration information obtaining instruction is first sent to the dual inline memory module, so that the dual inline memory module reads target configuration information from a register after receiving the configuration information obtaining instruction. It can be understood that under the MCTP protocol, the complex programmable logic device is used as a master to send a configuration information acquisition instruction to the dual in-line memory module. And after receiving the configuration information acquisition instruction, the dual in-line storage module reads the target configuration information of the dual in-line storage module from a local register.
It should be noted that, as shown in fig. 2, the main features of the control method for CPLD to receive and transmit data under the MCTP protocol in the prior art are: taking a CPLD as a master, sending a configuration information acquisition command to a DIMM through an I3C 0 (namely, a first upgrade system management bus), reading target configuration information from a register after the DIMM receives the configuration information acquisition command, sending the target configuration information to the CPLD in a frame data format, carrying out verification operation on the frame data by the CPLD, namely judging whether the DIMM device is in a white list of a system according to the frame data, if the DIMM device is in the white list of the system, indicating that the verification is passed, sending a verification result to a BMC through an I3C1 (namely, a second upgrade system management bus), and determining whether to open an I3C 2 (namely, a third upgrade system management bus) for carrying out information communication with the DIMM according to the verification result.
The current DIMM state monitoring process is shown in fig. 3, where BMC is used as a master, and related information of the DIMM, including device measurement point temperature, power state, software configuration information, etc., is obtained through SMBus, and a level shift chip (level shift) is designed at the same time, so as to solve the problem of different levels between the BMC and the DIMM, but the information cannot be shared because the two parts are not completely coupled. If the DIMM is not in the white list of the system configuration, the CPLD can still normally supply power to the DIMM at the moment. Meanwhile, the information communication between the BMC and the DIMM cannot be cut off, and huge hidden danger is caused to the information safety of the system. SMBus _ SDA is data under SMBus communication protocol, and SMBus _ SCL is a clock under SMBus communication protocol.
Step S12: and receiving the target configuration information sent by the dual in-line storage module, and carrying out corresponding verification operation on the target configuration information to obtain a verification result.
In this embodiment, after sending a configuration information obtaining instruction to a dual inline memory module, the target configuration information sent by the dual inline memory module is received, and corresponding verification operation is performed on the target configuration information to obtain a verification result. Specifically, after the target configuration information sent by the dual in-line memory module is received, the target configuration information is compared with information in the preset white list, and the comparison result is a verification result. For example, if the comparison is successful, it is indicated that the dual in-line memory module device is in the preset white list, that is, the dual in-line memory module device is a legal device currently, and the check is passed.
Step S13: and sending a corresponding signal control instruction to a power supply switching chip based on the verification result so that the power supply switching chip provides corresponding voltage to the dual in-line memory module based on the signal control instruction.
In this embodiment, after the verification result is obtained, a corresponding signal control instruction is sent to the power switching chip based on the verification result, so that the power switching chip provides a corresponding voltage to the dual in-line memory module based on the signal control instruction. It can be understood that, since the verification result includes two results, namely, a verification pass result and a verification fail result, it is necessary to determine to send a corresponding signal control instruction to the power switching chip according to the actually obtained verification result. The signal control instruction corresponds to the voltage provided by the power supply switching chip to the dual in-line memory module.
It should be noted that, as shown in fig. 4, a configuration information obtaining command is sent to the DIMM through I3C 0, the DIMM, after receiving the configuration information obtaining command, reads the target configuration information from the register, and sends the target configuration information to the CPLD in a frame data format, the CPLD performs a check operation on the frame data, that is, determines whether the DIMM device is in a white list of the system according to the frame data, that is, a check process, unlike the conventional MCTP, the CPLD determines the level of an enable (start) signal, that is, a switch of a VR Controller, according to the check result. If the DIMM is in a white list of the system, continuously raising enable to ensure that the VR Controller ensures the electricity consumption of the DIMM in normal operation; if the DIMM is not in the white list of the system, the switch of the VR Controller which pulls down the enable is closed, and the electricity which is normally operated by the DIMM is cut off. When the check is passed, the I3C1 sends the check result to the BMC or the CPU through the Bus Switch (power switching chip), and the BMC or the CPU determines whether to start the I3C 2 for information communication with the DIMM according to the check result. If the received verification result is that the DIMM is in a white list of the system equipment, performing data communication with the DIMM through I3C 2; if the received verification result is that the DIMM is not in the white list of the system device, at the moment, the VR Controller is in a closed state, the DIMM is powered off, and the BMC or the CPU cannot communicate with the DIMM through the I3C 2, so that the safety of system data is ensured.
It can be understood that, according to PDG (a specification about CPU usage) requirement of Eagle Stream platform, CPLD will pull up enable signal when timing sequence enters a certain stage, so as to make VR Controller ensure power consumption of DIMM for normal operation, thereby ensuring DIMM to enter normal operation state.
Therefore, the application provides a storage module management and control method, which comprises the following steps: sending a configuration information acquisition instruction to a dual in-line memory module so that the dual in-line memory module reads target configuration information from a register after receiving the configuration information acquisition instruction; receiving the target configuration information sent by the dual in-line storage module, and carrying out corresponding verification operation on the target configuration information to obtain a verification result; and sending a corresponding signal control instruction to a power supply switching chip based on the verification result so that the power supply switching chip provides corresponding voltage to the dual in-line memory module based on the signal control instruction. Therefore, the method and the device check the legality of the dual in-line memory module by using the acquired configuration information of the dual in-line memory module, and then send the corresponding signal control command to the power switching chip according to the check result, so that the power switching chip provides the corresponding voltage to the dual in-line memory module based on the signal control command, the use state of the dual in-line memory module is controlled, and the data safety is improved.
Referring to fig. 5, an embodiment of the present invention discloses a storage module management and control method, and compared with the previous embodiment, the present embodiment further describes and optimizes the technical solution.
Step S21: and sending a configuration information acquisition instruction to the dual in-line memory module so that the dual in-line memory module reads the target configuration information from the register after receiving the configuration information acquisition instruction.
Step S22: and receiving frame data which is sent by the dual in-line storage module and obtained by converting the target configuration information through a first preset format.
In this embodiment, frame data obtained by converting the target configuration information by a first preset format, which is sent by the dual in-line memory module, is received. It can be understood that, after reading the target configuration information of the dual in-line memory module, the dual in-line memory module needs to convert the target configuration information through a first preset format to obtain frame data of the first preset format, so that the complex programmable logic device receives the frame data.
Step S23: and reading the target configuration information in the frame data.
In this embodiment, after receiving the frame data, the frame data is read to obtain the target configuration information of the dual inline memory module. It is understood that the target configuration information includes information of a device model, a device manufacturer, and the like.
Step S24: and matching the target configuration information with information stored in a local preset white list to obtain a verification result.
In this embodiment, after the target configuration information is read, the target configuration information is matched with information stored in a local preset white list, so as to obtain a verification result. As shown in fig. 6, the target configuration information is matched with information stored in a local preset white list, and when the information corresponding to the target configuration information is matched in the preset white list, the verification result is that the verification is passed; and when the information corresponding to the target configuration information is not matched in the preset white list, the verification result is verification failure.
Step S25: and sending a corresponding signal control instruction to a power supply switching chip based on the verification result so that the power supply switching chip provides corresponding voltage to the dual in-line memory module based on the signal control instruction.
In this embodiment, after the verification result is obtained, a corresponding signal control instruction is sent to the power switching chip based on the verification result, so that the power switching chip provides a corresponding voltage to the dual in-line memory module based on the signal control instruction. It can be understood that, when the verification result is that the verification passes, the signal control instruction for increasing a target signal (i.e. enable signal) is sent to the power switching chip, so that the power switching chip provides a preset voltage to the dual in-line memory module; when the verification result is verification failure, sending the signal control instruction for reducing the target signal to the power supply switching chip; so that the power switching chip stops supplying voltage to the dual inline memory module. And after sending a corresponding signal control instruction to a power supply switching chip based on the verification result, receiving feedback information (PWRGD) corresponding to the signal control instruction, which is returned by the power supply switching chip after receiving the signal control instruction. For example, if the signal control instruction for improving the target signal is sent to the power switching chip, the received feedback information indicates that the power switching chip is in a normal working state, that is, a preset voltage is provided to the dual in-line memory module; and if the signal control instruction for reducing the target signal is sent to the power supply switching chip, the received feedback information indicates that the power supply switching chip is in a closed state, namely, the voltage supply to the dual in-line type storage module is stopped.
It is noted that the predetermined voltage is a voltage of the dual inline memory module during normal operation, for example, 12V.
Step S26: and converting the frame data when the verification passes through a second preset format to obtain converted frame data.
In this embodiment, if the signal control instruction for increasing the target signal is sent to the power switching chip when the verification passes, so that the power switching chip provides a preset voltage to the dual in-line memory module, the frame data when the verification passes is converted through a second preset format, so as to obtain converted frame data. It can be understood that, the CPLD locally converts the frame data in the second preset format to obtain converted frame data.
Step S27: and sending the converted frame data to a substrate management controller or a central processing unit through a wiring selector switch, so that when the signal control instruction for improving the target signal is sent to the power switching chip in the verification process, the substrate management controller or the central processing unit performs data interaction with the dual in-line type storage module through an upgraded system management bus and performs corresponding preset processing operation when monitoring that the corresponding data changes.
In this embodiment, after the converted frame data is obtained, the converted frame data is sent to a substrate management controller or a central processing unit through a connection switch, so that when the signal control instruction for improving the target signal is sent to the power switching chip through verification, the substrate management controller or the central processing unit performs data interaction with the dual in-line storage module through an upgraded system management bus, and performs corresponding preset processing operation when monitoring that corresponding data changes.
Specifically, the converted frame data is selectively sent to a substrate management controller or a central processing unit through a wiring selector switch according to actual conditions, the substrate management controller or the central processing unit realizes data interaction with the dual in-line memory module through I3C 2, for example, information such as temperature, current, voltage, power consumption and the like, then the substrate management controller or the central processing unit respectively monitors corresponding data, for example, the substrate management controller monitors equipment measuring point temperature, the central processing unit monitors power consumption information and the like, and corresponding preset processing operation is performed when the corresponding data is monitored to be changed.
It can be understood that, when the verification is passed, the converted frame data is sent to a baseboard management controller or a central processing unit through a wiring selector switch; if the verification fails, the DIMM is in a power-down state at the moment, and the converted frame data does not need to be sent to a substrate management controller or a central processing unit. When the wiring selector switch is used for carrying out data interaction with the substrate management controller or the central processing unit, different I3C are used as physical media for data transmission.
It should be noted that, by using I3C as the physical medium for MCTP transmission, the signal transmission rate of DDR5 can be guaranteed, and at the same time, the signal is monitored by CPLD; when the CPLD monitors that the DIMM is not in a white list of the system equipment through I3C 0, the VR Controller is directly closed through an enable signal, so that the DIMM is in a dynamically monitored state. The problem that the data transmission rate of the MCTP over SMBus is too low is solved, and the problem that DIMMs cannot be controlled in the using process is solved.
For details of the step S21, reference may be made to corresponding contents disclosed in the foregoing embodiments, and details are not repeated here.
Therefore, the configuration information acquisition instruction is sent to the dual in-line storage module in the embodiment of the application; receiving frame data which is sent by the dual in-line storage module and obtained by converting the target configuration information through a first preset format; reading the target configuration information in the frame data; matching the target configuration information with information stored in a local preset white list to obtain a verification result; sending a corresponding signal control instruction to a power supply switching chip based on the verification result; converting the frame data passing the verification through a second preset format to obtain converted frame data; and the converted frame data is sent to a substrate management controller or a central processing unit through a wiring selector switch, so that when the signal control instruction for improving the target signal is sent to the power switching chip during verification, the substrate management controller or the central processing unit performs data interaction with the dual in-line type storage module through an upgraded system management bus and performs corresponding preset processing operation when monitoring that corresponding data changes, and the data safety is improved.
Referring to fig. 7, an embodiment of the present application further discloses a storage module management and control apparatus correspondingly, which is applied to a complex programmable logic device, and includes:
a first instruction sending module 11, configured to send a configuration information obtaining instruction to a dual inline memory module, so that the dual inline memory module reads target configuration information from a register after receiving the configuration information obtaining instruction;
an information receiving module 12, configured to receive the target configuration information sent by the dual in-line memory module;
the information checking module 13 is configured to perform a corresponding checking operation on the target configuration information to obtain a checking result;
and a second instruction sending module 14, configured to send a corresponding signal control instruction to the power switching chip based on the verification result, so that the power switching chip provides a corresponding voltage to the dual in-line memory module based on the signal control instruction.
As can be seen, the present application includes: sending a configuration information acquisition instruction to a dual in-line memory module so that the dual in-line memory module reads target configuration information from a register after receiving the configuration information acquisition instruction; receiving the target configuration information sent by the dual in-line storage module, and performing corresponding verification operation on the target configuration information to obtain a verification result; and sending a corresponding signal control instruction to a power supply switching chip based on the verification result so that the power supply switching chip provides corresponding voltage to the dual in-line type storage module based on the signal control instruction. Therefore, the method and the device check the legality of the dual in-line memory module by using the acquired configuration information of the dual in-line memory module, and then send the corresponding signal control command to the power switching chip according to the check result, so that the power switching chip provides the corresponding voltage to the dual in-line memory module based on the signal control command, the use state of the dual in-line memory module is controlled, and the data safety is improved.
In some specific embodiments, the first instruction sending module 11 specifically includes:
the first instruction sending unit is used for sending a configuration information acquisition instruction to the dual in-line memory module, so that the dual in-line memory module reads target configuration information from a register after receiving the configuration information acquisition instruction.
In some specific embodiments, the information receiving module 12 specifically includes:
and the frame data receiving unit is used for receiving frame data which is sent by the dual in-line type storage module and obtained by converting the target configuration information through a first preset format.
In some specific embodiments, the information checking module 13 specifically includes:
a configuration information reading unit configured to read the target configuration information in the frame data;
the matching unit is used for matching the target configuration information with information stored in a local preset white list;
the verification passing unit is used for passing the verification when the information corresponding to the target configuration information is matched in the preset white list;
and the verification failure unit is used for passing the verification result when the information corresponding to the target configuration information is matched in the preset white list.
In some specific embodiments, the second instruction sending module 14 specifically includes:
the first signal control instruction sending unit is used for sending the signal control instruction for improving a target signal to the power switching chip when the verification result is that the verification is passed so that the power switching chip can provide a preset voltage for the dual in-line memory module; the preset voltage is the voltage of the dual in-line type memory module during normal work;
a second signal control instruction sending unit, configured to send, to the power switching chip, the signal control instruction for reducing the target signal when the verification result is a verification failure, so that the power switching chip stops providing voltage to the dual in-line memory module;
the frame data conversion unit is used for converting the frame data passing the verification through a second preset format to obtain converted frame data;
the converted frame data sending unit is used for sending the converted frame data to a substrate management controller or a central processing unit through a wiring selector switch, so that when the signal control instruction for improving the target signal is sent to the power switching chip in the verification process, the substrate management controller or the central processing unit performs data interaction with the dual in-line type storage module through an upgraded system management bus, and performs corresponding preset processing operation when monitoring that the corresponding data changes;
and the feedback signal receiving unit is used for receiving feedback information which is returned by the power supply switching chip after receiving the signal control instruction and corresponds to the signal control instruction.
Further, the embodiment of the application also provides electronic equipment. FIG. 8 is a block diagram illustrating an electronic device 20 according to an exemplary embodiment, and nothing in the figure should be taken as a limitation on the scope of use of the present application.
Fig. 8 is a schematic structural diagram of an electronic device 20 according to an embodiment of the present disclosure. The electronic device 20 may specifically include: at least one processor 21, at least one memory 22, a power supply 23, a communication interface 24, an input output interface 25, and a communication bus 26. The memory 22 is configured to store a computer program, and the computer program is loaded and executed by the processor 21 to implement relevant steps in the storage module management and control method disclosed in any of the foregoing embodiments. In addition, the electronic device 20 in this embodiment may be specifically an electronic computer.
In this embodiment, the power supply 23 is configured to provide a working voltage for each hardware device on the electronic device 20; the communication interface 24 can create a data transmission channel between the electronic device 20 and an external device, and a communication protocol followed by the communication interface is any communication protocol applicable to the technical solution of the present application, and is not specifically limited herein; the input/output interface 25 is configured to obtain external input data or output data to the outside, and a specific interface type thereof may be selected according to specific application requirements, which is not specifically limited herein.
In addition, the storage 22 is used as a carrier for resource storage, and may be a read-only memory, a random access memory, a magnetic disk or an optical disk, etc., and the resources stored thereon may include an operating system 221, a computer program 222, etc., and the storage manner may be a transient storage or a permanent storage.
The operating system 221 is used for managing and controlling each hardware device on the electronic device 20 and the computer program 222, and may be Windows Server, Netware, Unix, Linux, or the like. The computer program 222 may further include a computer program that can be used to perform other specific tasks in addition to the computer program that can be used to perform the storage module management method executed by the electronic device 20 disclosed in any of the foregoing embodiments.
Further, an embodiment of the present application further discloses a storage medium, where a computer program is stored in the storage medium, and when the computer program is loaded and executed by a processor, the steps of the storage module management and control method disclosed in any of the foregoing embodiments are implemented.
The embodiments are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same or similar parts among the embodiments are referred to each other. The device disclosed by the embodiment corresponds to the method disclosed by the embodiment, so that the description is simple, and the relevant points can be referred to the method part for description.
Finally, it should also be noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
The storage module management and control method, apparatus, device and storage medium provided by the present invention are described in detail above, and specific examples are applied herein to explain the principle and implementation of the present invention, and the description of the above embodiments is only used to help understanding the method and core ideas of the present invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present invention.
Claims (10)
1. A method for managing and controlling a memory module is applied to a complex programmable logic device and comprises the following steps:
sending a configuration information acquisition instruction to a dual in-line memory module so that the dual in-line memory module reads target configuration information from a register after receiving the configuration information acquisition instruction;
receiving the target configuration information sent by the dual in-line storage module, and performing corresponding verification operation on the target configuration information to obtain a verification result;
and sending a corresponding signal control instruction to a power supply switching chip based on the verification result so that the power supply switching chip provides corresponding voltage to the dual in-line memory module based on the signal control instruction.
2. The method according to claim 1, wherein the receiving the target configuration information sent by the dual inline memory module and performing a corresponding check operation on the target configuration information to obtain a check result includes:
receiving frame data which is sent by the dual in-line storage module and obtained by converting the target configuration information through a first preset format;
and carrying out corresponding checking operation on the frame data to obtain a checking result.
3. The storage module management and control method according to claim 2, wherein the performing a corresponding check operation on the frame data to obtain a check result includes:
reading the target configuration information in the frame data;
matching the target configuration information with information stored in a local preset white list;
when the information corresponding to the target configuration information is matched in the preset white list, the verification result is that the verification is passed;
and when the information corresponding to the target configuration information is not matched in the preset white list, the verification result is verification failure.
4. The storage module management and control method according to claim 3, wherein the sending of the corresponding signal control instruction to the power switching chip based on the verification result includes:
when the verification result is that the verification is passed, sending the signal control instruction for improving the target signal to the power supply switching chip;
and when the verification result is verification failure, sending the signal control instruction for reducing the target signal to the power supply switching chip.
5. The memory module management and control method according to claim 4, wherein the sending a corresponding signal control instruction to a power switching chip based on the verification result so that the power switching chip provides a corresponding voltage to the dual inline memory module based on the signal control instruction comprises:
sending the signal control instruction for improving the target signal to the power switching chip so that the power switching chip provides a preset voltage to the dual in-line memory module; the preset voltage is the voltage of the dual in-line type memory module during normal work;
and sending the signal control instruction for reducing the target signal to the power switching chip so that the power switching chip stops supplying voltage to the dual in-line memory module.
6. The method according to claim 4, wherein the sending a corresponding signal control command to a power switching chip based on the verification result, so that the power switching chip provides a corresponding voltage to the dual inline memory module based on the signal control command, further comprises:
converting the frame data passing the verification through a second preset format to obtain converted frame data;
and sending the converted frame data to a substrate management controller or a central processing unit through a wiring selector switch, so that when the signal control instruction for improving the target signal is sent to the power supply switching chip during verification, the substrate management controller or the central processing unit performs data interaction with the dual in-line storage module through an upgraded system management bus, and performs corresponding preset processing operation when monitoring that corresponding data changes.
7. The method according to any one of claims 1 to 6, wherein after sending the corresponding signal control instruction to the power switching chip based on the verification result, the method further includes:
and receiving feedback information corresponding to the signal control instruction, which is returned by the power supply switching chip after the signal control instruction is received.
8. The utility model provides a memory module management and control device which characterized in that is applied to complicated programmable logic device, includes:
the first instruction sending module is used for sending a configuration information acquisition instruction to the dual in-line storage module so that the dual in-line storage module can read target configuration information from a register after receiving the configuration information acquisition instruction;
the information receiving module is used for receiving the target configuration information sent by the dual in-line storage module;
the information checking module is used for carrying out corresponding checking operation on the target configuration information to obtain a checking result;
and the second instruction sending module is used for sending a corresponding signal control instruction to the power supply switching chip based on the verification result so that the power supply switching chip can provide corresponding voltage to the dual in-line storage module based on the signal control instruction.
9. An electronic device, comprising:
a memory for storing a computer program;
a processor for executing the computer program to implement the steps of the storage module management method according to any one of claims 1 to 7.
10. A computer-readable storage medium for storing a computer program; wherein the computer program, when executed by a processor, implements the storage module management method of any one of claims 1 to 7.
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