CN115032641B - ZYNQ-based satellite-borne high-repetition-frequency laser radar photon counting system - Google Patents

Abstract

A ZYNQ-based satellite-borne high-repetition-frequency laser radar photon counting system, wherein the ZYNQ chip comprises a programmable logic unit PL and a processor system PS; the programmable logic unit PL is used for collecting signals of the photon counting detector and finishing counting and storing; the programmable logic unit PL comprises a control module, a storage module, an output module and a counting module, wherein the storage module, the output module and the counting module are connected with corresponding pins of the control module; the counting module is used for carrying out sectional counting on the pulse signals output by the photon counting detector, the control module is used for controlling the counting module to carry out count value accumulation on the corresponding bin positions, and after the set accumulation times are reached, the counting result is transmitted to the processor unit PS; bin width corresponds to distance resolution. The invention realizes hardware accumulation in PL in ZYNQ slice, has fast operation speed, reduces bandwidth of data transmission between PL and PS, realizes control program related to data preprocessing and storage in PS in ZYNQ slice, and can work independently without industrial personal computer.

Description

ZYNQ-based satellite-borne high-repetition-frequency laser radar photon counting system

Technical Field

The invention relates to the technical field of data acquisition and processing, in particular to a ZYNQ-based satellite-borne high-repetition-frequency laser radar photon counting system.

Background

The laser radar uses laser as a carrier, and the laser interacts with particles or various gas molecules in the atmosphere to obtain a back scattering echo signal, and finally atmospheric parameters are obtained through data inversion and analysis. The method has the advantages of high space-time resolution, high detection precision and the like, and is widely used for detecting parameters such as atmospheric aerosol, water vapor, ozone or temperature and the like. The laser radar mainly comprises a laser transmitting unit, an optical receiving unit, an acquisition unit and a control unit, wherein the acquisition unit and the control unit are important components of the laser radar. The echo optical signals are converted into electric signals through photoelectric sensors (such as APDs/PMTs and the like), and the electric signals are collected and preprocessed (such as accumulated) through data and then sent to a control unit. Besides receiving and storing echo data, the control unit needs to monitor the running state of the laser in real time, set parameters of the acquisition card, configure gain and high voltage of the photoelectric detector, and the like, and is generally realized by using an industrial personal computer with strong universality, so that the laser radar works orderly according to set steps.

The lidar may be classified into ground-based, vehicle-based, airborne, and space-based lidars according to the platform. Various lidars have different requirements on acquisition control systems, such as relatively low requirements on foundation lidars, and in order to obtain higher spatial resolution, commercial data acquisition cards are usually used to cooperate with industrial personal computers (control units), and the acquisition and control systems are generally not dedicated, which makes the foundation lidar acquisition and control systems relatively large. The space-borne laser radar is much more complex than the ground-based laser radar in the environment, such as solar power supply in outer space and incapability of manual adjustment or maintenance in on-orbit operation, so that the electronic system is required to have lower power consumption and higher stability, and the electronic system with stable hardware structure and high device integration level is required. Because of the limitation of factors such as volume, power consumption, stability and the like, the software and hardware architecture of the data acquisition and control system is different from that of the ground-based laser radar, and no such equipment is available in the market.

The current space-borne lidars that are representative in terms of Cloud and aerosol detection are CALIOP (Cloud-Aerosol Lidar with Orthogonal Polarization) and CATS (Cloud Aerosol Transport System). CATS is a satellite-borne laser radar adopting a photon detection mode for the first time, compared with CAPIPSO, the laser monopulse energy is reduced to several mJ levels from the traditional hundred mJ, and meanwhile, the working frequency of kHz is adopted, so that the horizontal resolution of earth observation is greatly improved. CATS has two lasers with single pulse energy of 1mJ/2mJ and repetition rate of 5kHz/4kHz, respectively. The average transmitting power of the laser is improved by improving the pulse repetition frequency, in the detection mode, echo signals received by the radar are extremely weak and are only of photon magnitude, if the analog detection mode is used, the echo signals cannot be extracted from background noise due to extremely low signal-to-noise ratio, so that photon counting technology is needed, namely the number of photon pulses which occur randomly is counted, finally, the echo signal intensities of different distances are obtained through statistics, and higher requirements are put on a photon counting acquisition card.

Currently, commercial photon counting cards (Multichannel Scaler: MCS) are not more, such as MCS-PCI and EASY-MCS are boards adopting PCI and USB buses respectively, which are used for counting external pulses based on a programmable logic device, the counted value of each trigger is transmitted to a computer for software accumulation, and when the trigger frequency of a laser is very high (such as 1 MHz), data loss can be caused due to the limitation of the transmission rate. The Licel transient recorder is applied to the field of laser radars, an Ethernet interface is used for transmitting data, two acquisition modes of simulation and photon counting are supported, but the Licel transient recorder adopts a modularized structure, is flexible, has a large volume and is high in price. The acquisition equipment has only a data acquisition function, and the participation of an industrial personal computer is needed for data transmission, data storage and control of each unit of the laser radar, so that the structural complexity of the whole laser radar is increased.

Disclosure of Invention

In order to solve the technical problems, the invention provides a ZYNQ-based satellite-borne high-repetition-frequency laser radar photon counting system, which comprises the following specific technical scheme:

a ZYNQ-based satellite-borne high-repetition-frequency laser radar photon counting system, wherein the ZYNQ chip comprises a programmable logic unit PL and a processor system PS; the programmable logic unit PL is used for collecting signals of the photon counting detector and finishing counting and storing; the programmable logic unit PL comprises a control module, a storage module, an output module and a counting module, wherein the storage module, the output module and the counting module are connected with corresponding pins of the control module;

the counting module performs sectional counting on the pulse signals output by the photon counting detector, the control module controls the counting module to perform count value accumulation and accumulation times on the corresponding positions of the bin channels, and after the set accumulation times are reached, the counting result is transmitted to the processor unit PS; bin width corresponds to distance resolution.

In particular, the programmable logic unit PL also comprises an AXI protocol conversion module.

Specifically, the control module includes a rising edge detection circuit, the rising edge detection circuit includes a trigger DFF1, a trigger DFF2, a NOT gate NOT1, an AND gate AND1, AND a trigger DFF3 that are sequentially set, another input terminal of the AND gate is connected to an output terminal of the trigger DFF1, an input terminal of the trigger DFF1 inputs a trigger signal, two input terminals of a comparator CMP1 in the control module respectively input a bin width cnt_bin_width AND a bin width set_bin_width, two input terminals of the comparator CMP2 respectively input a bin number cnt_bin_num AND a bin number set_num, an output terminal of the two comparators is correspondingly connected to two input terminals of the AND gate AND2, an output terminal of the AND gate AND2 is connected to an input terminal of the trigger DFF5, the trigger DFF5 is used for outputting a count completion signal done AND is connected to a selector 1 selection terminal of the multiplexer, one input terminal of the multiplexer MUX1 is connected to an output terminal of the rising edge detection circuit, AND the other input terminal of the trigger MUX 4 is connected to an output terminal of the trigger DFF 4.

Specifically, the counting module comprises a counter selection unit, an initial signal processing unit, a first counting unit and a second counting unit;

the counter selection unit comprises a comparator CMP21, a multiplexer MUX21, an NOT21, a trigger DFF21, a subtracter SUB21 and a comparator CMP22, wherein two input ends of the comparator CMP21 are respectively input with cnt_bin_width and set_bin_width signals of an internal register, an output end is connected with a selection end of the multiplexer MUX21, an output end of the multiplexer MUX21 is connected with one input end through the NOT21 after passing through the trigger DFF21, and the other input end is directly connected with an output end of the trigger DFF21 and outputs js_en signals; the cnt_bin_width signal is input to an input end of the comparator CMP22, the set_bin_width signal is input to the other input end of the comparator CMP22 after passing through the subtracter SUB21, the other input end of the subtracter SUB21 is input with the signal 1, and the output end of the comparator CMP22 outputs the sig1 signal;

the initial signal processing unit comprises a NOT22 and a NOR gate NOR22, wherein two input ends of the NOR gate NOR22 are respectively a counting start run signal and a busy signal being counted, an output end of the NOR gate NOR22 is used for providing sig2 signals for the first counting unit and the second counting unit, and js_en signals are output after passing through the NOT gate NOT 22;

the first counting unit includes an AND gate AND21, a multiplexer MUX22, a flip-flop DFF22, a multiplexer MUX23, an adder ADD21, AND a flip-flop DFF23;

the two input ends of the AND gate AND21 are respectively input with js_en signal AND sig1 signal, the output end is connected with one end of a multiplexer MUX22, the other end of the multiplexer MUX22 is input with 1, the selection end is input with sig2 signal, the output end is connected with the input end of a trigger DFF22, the output end of the trigger DFF22 outputs rst_1 signal, the input end of a multiplexer MUX23 is respectively 0 AND1, AND the selection end is input with js_en signal; the output end is connected with one end of the adder ADD21, the output end of the adder ADD21 outputs a cnt1 signal after passing through the trigger DFF23, the cnt1 signal is fed back to the other input end of the adder ADD21, the reset end of the trigger DFF23 inputs an rst_1 signal, and the clock input end inputs a pulse signal;

the second counting unit includes an AND gate AND22, a multiplexer MUX24, a flip-flop DFF24, a multiplexer MUX25, an adder ADD22, AND a flip-flop DFF25;

the two input ends of the AND gate 22 are respectively input with a js_en signal AND a sig1 signal, the output end is connected with one end of a multiplexer MUX24, the other end of the multiplexer MUX24 is input with 1, the selection end is input with a sig2 signal, the output end is connected with the input end of a trigger DFF24, the output end of the trigger DFF24 is output with a rst_2 signal, the input ends of a multiplexer MUX25 are respectively 0 AND1, AND the selection end is input with a js_en signal; the output end is connected with one end of the adder ADD22, the output end of the adder ADD22 outputs a cnt2 signal after passing through the trigger DFF25, the cnt2 signal is fed back to the other input end of the adder ADD22, the reset end of the trigger DFF25 inputs the rst_2 signal, and the clock input end inputs the pulse signal.

Specifically, the comparators CMP31, CMP32, CMP33 in the output module are connected to the input terminal of the AND gate AND31, the bin width cnt_bin_width AND the bin width set value set_bin_width are respectively AND correspondingly input to the two input terminals of the comparator CMP31, the bin number cnt_bin_num AND the bin number set value set_bin_num are respectively AND correspondingly input to the two input terminals of the comparator CMP32, AND the accumulation times cnt_accum_num AND the accumulation times set value set_accum_num are respectively AND correspondingly input to the two input terminals of the comparator CMP 33;

the two ends of the subtracter SUB31 are respectively corresponding to input signals set_bin_num and1, the output end is connected with one input end of the comparator CMP34, the read-RAM address rd_ram_addr is used as the input end of the trigger DFF32, after the trigger DFF32, the trigger DFF33 and the trigger DFF34 are sequentially arranged, the output end of the trigger DFF34 is connected with the other input end of the comparator CMP34, the output end of the comparator CMP34 outputs a signal sig31 and is used as a gating signal of the multiplexer MUX31, and the output end of the trigger DFF33 outputs the signal sig32;

the comparator CMP35 has one end for inputting the signal sig32 AND the other end for inputting 1, the output end is connected with one input end of the adder AND32, the comparator CMP36 has one end for inputting the signal sig32 AND the other end for inputting the bin number setting value set_bin_num, the output end is connected with the other input end of the adder AND32, the third input end of the adder AND32 inputs the accumulation completion flag flag_out signal, the output end outputs the signal sig33, one end of the multiplexer MUX32 inputs the read RAM data rd_ram_data signal, the output end outputs the accumulation data data_accum signal after passing through the trigger DFF35, the accumulation data data_accum signal is fed back to the other input end of the multiplexer MUX32, AND the selection end of the multiplexer MUX32 inputs the accumulation completion flag flag_out signal;

the multiplexer MUX33 has an input terminal for inputting 0, an input terminal for inputting 4, and an output terminal for outputting an accumulated address_accum signal after passing through the adder ADD31 and the flip-flop DFF36, the accumulated address_accum signal being fed back to the other input terminal of the adder ADD31, and a selection terminal of the multiplexer MUX33 inputs the signal sig33.

Specifically, the model of the ZYNQ chip is ZYNQ-7020.

Specifically, the processor system PS includes two ARM Cortex-A9.

Specifically, the system also comprises

A laser for emitting laser light and outputting a trigger signal synchronized with the laser light;

the comparator is used for discriminating the trigger signal to obtain a starting signal serving as a sample;

and the photon counting detector is used for detecting the echo signals and outputting pulse signals with density proportional to light intensity.

The invention has the advantages that:

(1) The laser radar adopts the high-repetition frequency micropulse laser, the detection mode is photon counting, and the laser radar is suitable for remote sensing monitoring of dust haze pollution in areas.

(2) Due to the presence of shot noise and electron thermal noise, PMTs still have a small number of random pulse outputs, i.e. "dark counts" caused by "dark noise", in the absence of external light illumination. Moreover, sky backlight can also cause the detector to output electronic pulses, so that the observation precision of the laser radar is greatly influenced.

(3) Firstly, realizing sectional counting on a programmable logic unit PL in a ZYNQ slice, adopting two counters to alternately count, and eliminating the influence of dead time; hardware accumulation (accumulation operation is realized through a logic circuit) is realized in the programmable logic unit PL, the operation speed is high, the data throughput of transmission between the PL and the PS is reduced, and meanwhile, a high-speed AXI bus is adopted to transmit data to the PS, so that the triggering of a high-repetition frequency laser is supported; aiming at the needs of a satellite-borne special environment, the control program related to data preprocessing and storage is realized in PS in the ZYNQ chip, and the control program can independently work under the condition of no industrial personal computer. The system adopts a software and hardware collaborative design method, all acquisition and control functions are completed in the ZYNQ, internal data transmission is interconnected by an internal high-speed AXI bus, external interference is effectively reduced, and stability and reliability are improved.

(4) When the micropulse laser radar is applied to the field of atmospheric detection, the echo signal is extremely weak and is only in photon magnitude (10) ^-14 W), only the detection mode of photon counting can be adopted to obtain effective echo signals. However, the number of echo photons after one shot is very small, and the atmospheric background noise and shot noise in electronics are always present, so that the signal-to-noise ratio of the echo after one shot is very low (much smaller than 1), and therefore, the echo can not be directly used for inversion of atmospheric parameters. The signal to noise ratio can be greatly improved by adopting an accumulation mode, and the improvement degree of the signal to noise ratio is in direct proportion to the square root of accumulation times. In practical application, the method can be accumulated by both software and hardware. The working principle of software accumulation is as follows: and when triggering each time, the result of PL counting is sent to the DSP/ARM/computer through a bus, and then accumulated in a serial working mode in the processor, so that the speed is low. The method has high requirement on bus bandwidth, when the signal with high repetition frequency is triggered (such as 1 MHz), the triggering interval is only 1 mu s, so the data volume is large, the data is lost when the data is not timely transmitted to the receiving end, and the FIFO is in a full state for a long time even if the FIFO is used for caching, and communication congestion is caused when the FIFO is continuously collected; the working principle of hardware accumulation is as follows: the count value after the PL is triggered for many times is directly accumulated in an internal logic circuit in a parallel working mode, and only the final accumulated result is output to the DSP/ARM/computer to further finish data processing. And when hardware accumulation is adopted, the one-shot result of PL is directThe count value and the last count value are accumulated by the adder, the result is transmitted by the bus only after the whole accumulation process is finished, and the frequency of data transmission is reduced, so that the data transmission is not jammed. In summary, the PL-based hardware accumulation approach and the high speed AXI bus together guarantee the support of the system to the high repetition frequency laser.

(5) The AXI bus has the advantages of high bandwidth and low delay, and can timely and efficiently transmit data when triggered by high repetition frequency. The invention adopts the ZYNQ heterogeneous chip, the AXI bus is connected with PL and PS in the chip, and the reliability and the effectiveness of data transmission are high. The traditional double-chip scheme (such as FPGA+ARM/DSP) lacks an efficient communication bus, bus connection such as SPI/FSMC/EMIF is generally adopted, transmission efficiency is low, and the bus is arranged on a PCB circuit board and is more easily interfered by external electromagnetic signals. In conclusion, the data acquisition and control system based on the ZYNQ heterogeneous chip has the advantages of good stability, high data transmission rate, small volume and the like, and the advantages are required by the satellite-borne high-repetition-frequency laser radar data acquisition and control system.

(6) ZYNQ has PL (Aritx-7 FPGA) and PS (ARM Cortex-A9 dual core and other peripherals). In the invention, the external pulse signals are repeatedly counted by utilizing the advantages of PL (pulse line) high-speed parallel processing, the counted results are accumulated and then transmitted to PS (PS for preprocessing, background noise removal and the like), meanwhile, the system receives the control instruction of the ground console at any time, in order to prevent interference in the data preprocessing process (when the wireless module receives the instruction, the wireless module preferentially enters an interrupt service routine, the main routine stops running and returns to the main routine for continuous running after the interrupt routine is finished), and the two ARM cores in the interior are utilized for division work cooperation, namely ARM 1 core circulation is utilized for executing fault detection, data preprocessing and data storage, and the three are normal working states of the system, so the stability is important. The ARM 2 core is responsible for communicating with a ground console, and the working time is random, for example, after receiving a ground control instruction (such as reading collected data for a period of time), the ARM 2 core reads the data from a nonvolatile memory (IDE hard disk) and wirelessly transmits the data, and the data is serially transmitted to the wireless module at the moment, so that the time is required for transmission. An internal message transmission mechanism is adopted between the ARM 1 core and the ARM 2 core, so that data conflict caused by reading and writing DDR3 SDRAM or a hard disk simultaneously is avoided. In conclusion, the dual-core advantage of PS is fully utilized, the probability of data loss can be greatly reduced, and the robustness of a control program is improved.

Drawings

Fig. 1 is an overall configuration diagram of a system.

Fig. 2 is a circuit diagram of a control module.

Fig. 3 is a circuit diagram of the counting module.

Fig. 4 is a circuit diagram of the output module.

Fig. 5 is a diagram of the overall echo signal acquisition process.

Fig. 6 is a timing diagram of a system obtaining photon counts.

Detailed Description

A ZYNQ-based satellite-borne high-repetition frequency laser radar photon counting system comprises

A laser for emitting laser light and outputting a trigger signal synchronized with the laser light;

the comparator is used for discriminating the trigger signal to obtain a starting signal serving as a sample;

the photon counting detector is a PMT (photomultiplier tube) or a SPAD (single photon avalanche diode) and is used for detecting echo signals and outputting pulse signals with density being in direct proportion to light intensity;

and the acquisition and control system is used for obtaining the pulse signals output by the photon counting detector. In the scheme, a ZYNQ chip (heterogeneous multi-core chip) is adopted as an acquisition system, and the specific model is ZYNQ-7020.

As shown in fig. 1, the ZYNQ chip includes a programmable logic unit PL and a processor system PS.

The programmable logic unit PL is used for collecting signals of the photon counting detector and finishing counting and storing; the programmable logic unit PL comprises a control module, a storage module connected with corresponding pins of the control module, an output module and a counting module.

The counting module performs segment counting on the pulse signals output by the photon counting detector, the control module controls the counting module to accumulate the count value of the corresponding position of the bin channel, and after the set accumulated times are reached, the counting result is transmitted to the processor unit PS. The bin width corresponds to a distance resolution, such as 50ns, and the corresponding distance resolution is 7.5m. The output module reads data from the storage module.

The programmable logic unit PL further comprises an AXI protocol conversion module for providing conditions for providing validity of data communication, preventing congestion of data caused by high frequency triggering. The protocol conversion module encapsulates the data in an AXI4 protocol, transmits the data to a DDR3 SDRAM connected with a processor system PS through a high-speed AXI-Full bus, and after the data transmission is completed, the programmable logic unit PL informs the processor system PS through an interrupt inr to remind the processor system PS to timely read and process the data from the DDR3 SDRAM. Because DDR3 SDRAM memory is mounted on processor system PS, data can be read out fast and preprocessed, and timeliness is increased. In addition, the processor system PS may also transmit three parameters of the bin channel width (set_bin_width) required for acquisition, the bin channel number (set_bin_num) and the accumulation number (set_accum_num) to the control module of the programmable logic unit PL through the axi_lite bus, so as to implement dynamic configuration of the photon counting system. The AXI_Lite bus is a simplified AXI bus, occupies less logic resources, and is realized in Vivado through a custom IP core.

The processor system PS includes two ARM Cortex-A9, and in order to improve the system operation efficiency, fault detection, data preprocessing and data storage programs are executed in the ARM core 1, and finally data is stored in the hard disk. The ARM kernel 2 detects whether the wireless transmission module receives the instruction in real time, and executes corresponding actions or transmits data to the ground console through the wireless transmission module when receiving the instruction. Through dual-core cooperative work, the ARM core 2 does not influence the program running in the ARM core 1 when in wireless communication with a ground console, so that the data integrity is maintained.

The circuits of the control module, the counting module and the output module are described in detail below.

Control module

As shown in fig. 2, the control module includes a rising edge detection circuit, where the rising edge detection circuit includes a trigger DFF1, a trigger DFF2, a NOT1, an AND gate AND1, AND a trigger DFF3 that are sequentially set, the other input of the AND gate is connected to the output of the trigger DFF1, the input of the trigger DFF1 is input with a trigger signal, the two inputs of a comparator CMP1 in the control module are respectively input with a bin width cnt_bin_width AND a bin width set value set_bin_width, the two inputs of the comparator CMP2 are respectively input with a bin number cnt_bin_num AND a bin number set value set_bin_num, the output of the two comparators is correspondingly connected to the two inputs of the AND gate AND2, the output of the AND gate AND2 is connected to the input of the trigger DFF5, the trigger DFF5 is used for outputting a count completion signal done AND is connected to a selector 1, the one input of the multiplexer MUX1 is connected to the rising edge detection circuit, AND the other input of the trigger DFF4 is connected to the output of the trigger DFF 4.

The working principle is as follows: the module mainly completes real-time control of the counting module, the storage module and the output module by generating run, busy and done signals. The rising edge of the trigger signal trigger outputted by the laser means that the laser has been emitted, so that the trigger signal is detected by a rising edge detection circuit composed of the trigger DFF1, the trigger DFF2, the NOT gate NOT1, the AND gate AND3, AND the trigger DFF3, AND a run signal is outputted. When the rising edge of trigger arrives, run is pulled high, indicating that the acquisition system starts to work by counting a single round. The current counting state is output through the multiplexer MUX1 and the trigger DFF4, when run is high, and the counting is not finished (done is low), busy is pulled high to indicate that the counting is currently performed, and the acquisition system single-round counting work is indicated to be performed. The comparators CMP1, CMP2, AND gate AND2 AND the flip-flop DFF5 are used to output the count completion signal done, i.e. done is pulled high when the values cnt_bin_width AND cnt_bin_num of the internal counter are simultaneously equal to the set parameters (output by PS) set_bin_width AND set_bin_num, respectively, at which time the acquisition system single-round counting operation ends.

Counting module

As shown in fig. 3, the apparatus includes a counter selection unit, an initial signal processing unit, a first counting unit, and a second counting unit; the specific description is as follows:

the counter selection unit comprises a comparator CMP21, a multiplexer MUX21, an NOT21, a trigger DFF21, a subtracter SUB21 and a comparator CMP22, wherein two input ends of the comparator CMP21 are respectively input with cnt_bin_width and set_bin_width signals of an internal register, an output end is connected with a selection end of the multiplexer MUX21, an output end of the multiplexer MUX21 is connected with one input end through the NOT21 after passing through the trigger DFF21, and the other input end is directly connected with an output end of the trigger DFF21 and outputs js_en signals; the cnt_bin_width signal is input to an input terminal of the comparator CMP22, the set_bin_width signal is input to the other input terminal of the comparator CMP22 after passing through the subtractor SUB21, the other input terminal of the subtractor SUB21 inputs the signal 1, and the output terminal of the comparator CMP22 outputs the sig1 signal.

The initial signal processing unit comprises a NOT22 and a NOR gate NOR22, wherein two input ends of the NOR gate NOR22 are respectively a counting start run signal and a busy signal being counted, an output end of the NOR gate NOR22 is used for providing sig2 signals for the first counting unit and the second counting unit, and js_en signals are output after passing through the NOT gate NOT 22.

The first counting unit includes an AND gate AND21, a multiplexer MUX22, a flip-flop DFF22, a multiplexer MUX23, an adder ADD21, AND a flip-flop DFF23;

the two input ends of the AND gate AND21 are respectively input with js_en signal AND sig1 signal, the output end is connected with one end of a multiplexer MUX22, the other end of the multiplexer MUX22 is input with 1, the selection end is input with sig2 signal, the output end is connected with the input end of a trigger DFF22, the output end of the trigger DFF22 outputs rst_1 signal, the input end of a multiplexer MUX23 is respectively 0 AND1, AND the selection end is input with js_en signal; the output end is connected with one end of the adder ADD21, the output end of the adder ADD21 outputs a cnt1 signal after passing through the trigger DFF23, the cnt1 signal is fed back to the other input end of the adder ADD21, the reset end of the trigger DFF23 inputs an rst_1 signal, and the clock input end inputs a pulse signal.

The second counting unit includes an AND gate AND22, a multiplexer MUX24, a flip-flop DFF24, a multiplexer MUX25, an adder ADD22, AND a flip-flop DFF25;

the two input ends of the AND gate 22 are respectively input with a js_en signal AND a sig1 signal, the output end is connected with one end of a multiplexer MUX24, the other end of the multiplexer MUX24 is input with 1, the selection end is input with a sig2 signal, the output end is connected with the input end of a trigger DFF24, the output end of the trigger DFF24 is output with a rst_2 signal, the input ends of a multiplexer MUX25 are respectively 0 AND1, AND the selection end is input with a js_en signal; the output end is connected with one end of the adder ADD22, the output end of the adder ADD22 outputs a cnt2 signal after passing through the trigger DFF25, the cnt2 signal is fed back to the other input end of the adder ADD22, the reset end of the trigger DFF25 inputs the rst_2 signal, and the clock input end inputs the pulse signal.

The count start run signal and the count busy signal are connected to the NOR gate NOR21, and when the single-round trigger is ended, run and busy are both low, and at this time, the output signal sig2 of the NOR21 is high, and the multiplexer MUX22 of the first counting unit and the multiplexer MUX24 of the second counting unit are output high, so that the counter can be cleared (the flip-flop DFF22 and the flip-flop DFF25 output high, and the clear signals rst_1 and rst_2 are both 1).

During the counting (at least one of the count start signal run or the count signal busy is high) sig2 is low, AND inputs of the multiplexer MUX22 AND the multiplexer MUX24 are respectively connected to the AND gate AND21 AND the AND gate AND22.

The comparator CMP21 compares the bin width cnt_bin_width with the bin width set value set_bin_width. When they are equal, the js_en signal toggles (js_en becomes js_en and vice versa), the toggling function is implemented by the multiplexer MUX21, the NOT gate NOT21 and the flip-flop DFF 21. js_en AND its inverse signal js_en (generated by the NOT gate NOT 22) are respectively connected to the AND gate AND21 AND the AND gate AND22.

Meanwhile, the subtractor SUB21 and the comparator CMP22 compare the bin width value cnt_bin_width with the bin width set value set_bin_width-1 value. When they are equal, sig1 is high, indicating that the set channel time has arrived, allowing the counters 1 AND2 to be cleared, sig1 signal is passed into AND gate AND21 AND gate AND22.js_en (or js_en) and sig1 signals alternately clear the counter, and the clear operation is synchronous with the bin width set value set_bin_width (if set_bin_width corresponds to 50ns, the clear period is 50 ns).

When js_en signal is high, the counter's multiplexer MUX22 outputs 1, and when the external pulse rising edge arrives, the count value of the second counting unit is incremented by 1 (implemented by the flip-flop DFF25 and the adder ADD 22). Similarly, when the js_en signal is at low level, the multiplexer MUX25 of the counter outputs 1, and when the rising edge of the external pulse arrives, the count value of the second counting unit is incremented by 1 (realized by the flip-flop DFF25 and the adder ADD 22).

Output module

As shown in fig. 4, the comparators CMP31, CMP32, CMP33 in the output module are connected to the input terminals of the AND gate AND31, AND the bin width cnt_bin_width AND the bin width setting value set_bin_width are respectively input to the two input terminals of the comparator CMP 31. The bin number cnt_bin_num and the bin number set value set_bin_num are respectively input to two input ends of the comparator CMP32 correspondingly. The count cnt_accum_num of the accumulated times and the set value set_accum_num of the accumulated times are respectively input to two input terminals of the comparator CMP 33. That is, when the bin width value cnt_bin_width, the bin number cnt_bin_num, AND the count value cnt_accum_num of the accumulation times are respectively equal to the PS output parameters (set_bin_width, set_bin_num, AND set_accum_num), the output signal of the AND31 is pulled high, indicating that the one accumulation process is ended.

The output terminal of the AND gate AND31 is connected to the input terminal of the multiplexer MUX31, the other input terminal is input with 0, AND the output terminal outputs the accumulation completion flag_out signal after passing through the flip-flop DFF 31.

The two ends of the subtracter SUB31 are respectively corresponding to input signals set_bin_num and1, the output end is connected with one input end of the comparator CMP34, the read RAM address rd_ram_addr is used as the input end of the trigger DFF32, the trigger DFF33 and the trigger DFF34 are sequentially arranged, the output end of the trigger DFF34 is connected with the other input end of the comparator CMP34, the output end of the comparator CMP34 outputs a signal sig31, and the output end of the trigger DFF33 outputs a signal sig32 as a gating signal of the multiplexer MUX 31. The sig31 signal is used to reset the accumulation flag signal flag_out, i.e., sig31 is high when the read address signal is the same value as set_bins_num-1 (indicating that the read is complete). At this time, the input of the multiplexer MUX31 is 0, and the output of the flip-flop DFF31 is 0, i.e., the accumulation completion flag signal flag_out is cleared, so that the next accumulation flag signal is conveniently generated. The flip-flop DFF32, the flip-flop DFF33, and the flip-flop DFF34 constitute a delay unit that delays the RAM read address signal rd_ram_addr by three clock cycles to prevent premature reset of the flag_out.

The comparator CMP35 has one end for inputting the signal sig32 AND the other end for inputting 1, the output end is connected with one input end of the adder AND32, the comparator CMP36 has one end for inputting the signal sig32 AND the other end for inputting the bin number setting value set_bin_num, the output end is connected with the other input end of the adder AND32, the third input end of the adder AND32 inputs the accumulation completion flag flag_out signal, the output end outputs the signal sig33, one end of the multiplexer MUX32 inputs the read RAM data rd_ram_data signal, the output end outputs the accumulation data data_accum signal after passing through the trigger DFF35, the accumulation data data_accum signal is fed back to the other input end of the multiplexer MUX32, AND the selection end of the multiplexer MUX32 inputs the accumulation completion flag flag_out signal; the multiplexer MUX32 and the flip-flop DFF35 are used to control the value of the accumulated data data_accum. When the accumulation is finished (flag_out is high), the value of data is equal to the data rd_ram_data in the RAM of the memory module, and the accumulated data continues to store the original value under the other conditions. The multiplexer MUX33 has an input terminal for inputting 0, an input terminal for inputting 4, and an output terminal for outputting an accumulated address_accum signal after passing through the adder ADD31 and the flip-flop DFF36, the accumulated address_accum signal being fed back to the other input terminal of the adder ADD31, and a selection terminal of the multiplexer MUX33 inputs the signal sig33. The comparator CMP35, the comparator CMP36, the AND gate AND32, the multiplexer MUX33, AND the adder ADD31 generate the accumulated address signal address_accum. When accumulation is completed (flag_out is at high level), and the value sig2 signal (DFF 3 output) after rd_ram_addr delay satisfies 1.ltoreq.sig2.gtoreq.set_bin_num (i.e. data has not been transmitted yet), the accumulated address signal address_accum is self-incremented by 1, at this time, the data in the RAM are read out in turn, and the accumulated address is 0 in the rest cases. When the flag_out is pulled high, the data data_accum accumulated in the RAM memory module is sequentially transferred to the AXI protocol converter (the flag_out remains high during the transfer until the transfer is finished), and finally output to the DDR3 SDRAM connected to the PS.

According to the system, the whole echo signal acquisition process is shown in fig. 5, the laser emits laser light and simultaneously outputs a trigger signal synchronous with the laser light, and after the trigger signal is screened by the high-speed comparator, the trigger signal is output and used as an initial signal of the photon counting system. The PMT photon detector detects the echo signal pulse and inputs the echo signal pulse to the photon counting system. In order to obtain the distribution characteristics of aerosol concentrations at different heights, the echo photon signals are counted by adopting a segment counting method, namely, the count value of the bin width (such as 50ns, which can be set) represents the number of echo photons in a section of height interval (according to the propagation speed of light, 50ns corresponds to 7.5 m), and the bin number corresponds to the total detection distance, for example, when the bin channel time is 50ns and the bin channel number is 5000, the total detection distance is 37.5km (bin width is equal to bin number). Studies have shown that the improvement in snr is proportional to the square root of the number of summations, and thus the number of echo photons in the same altitude interval (e.g., the first bin of each trigger, the dark gray filled region of the figure) is correspondingly summated (e.g., 10 ⁴ Second, settable). After the accumulation is finished, the intensity distribution of the echo signals can be recovered by the acquired data, and the intensity distribution of the echo signals represents aerosol concentrations at different heights.

According to the acquisition procedure described above, the timing of obtaining photon counts is shown in fig. 6, where the master clock signal clk of the acquisition system is generated by a sum crystal and Phase Locked Loop (PLL). After an external trigger signal trigger is input into an acquisition system, a rising edge detection circuit outputs a run signal (trig_r and trig_rr are signals with 1 and2 periods delayed by the trigger respectively), run= -trig_rr & trig_r is a counting start signal, and after the trigger signal trigger is valid, the busy signal is pulled high to indicate that a counter is working.

To reduce the effect of dead time of counting (the time it takes for a counter to store data during which it cannot count), it works in a "ping-pong" manner, i.e. when one of the counters counts, the other counter is stored, and vice versa. cnt1 and cnt2 are two independent counters that are alternately selected by cnt_en to prevent a miss count event from occurring due to the data storage process, with a single count period, i.e., bin width (here 50 ns), being adjustable. pulse is the output signal of the single photon detector, the signal appears randomly, and adjacent pulses can be closely separated, and an asynchronous logic design method is adopted, so that the probability of counting leakage is effectively reduced.

When counting is completed, done outputs a high level signal of one period, which indicates that sampling caused by one-shot is finished (a dotted rectangle box in the figure is a one-shot process). After all accumulation processes are completed, the flag_out outputs a high level signal, which indicates that the accumulation process is completed, and the data in the RAM storage module are sequentially output to the PS through the AXI protocol converter.

The above embodiments are merely preferred embodiments of the present invention and are not intended to limit the present invention, and any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the scope of the present invention.

Claims (7)

1. The ZYNQ-based satellite-borne high-repetition-frequency laser radar photon counting system is characterized in that the ZYNQ chip comprises a programmable logic unit PL and a processor system PS; the programmable logic unit PL is used for collecting signals of the photon counting detector and finishing counting and storing; the programmable logic unit PL comprises a control module, a storage module, an output module and a counting module, wherein the storage module, the output module and the counting module are connected with corresponding pins of the control module;

the counting module performs sectional counting on the pulse signals output by the photon counting detector, the control module controls the counting module to perform count value accumulation and accumulation times on the corresponding positions of the bin channels, and after the set accumulation times are reached, the counting result is transmitted to the processor unit PS; bin width corresponds to distance resolution;

the counting module comprises a counter selection unit, an initial signal processing unit, a first counting unit and a second counting unit;

the counter selection unit comprises a comparator CMP21, a multiplexer MUX21, an NOT21, a trigger DFF21, a subtracter SUB21 and a comparator CMP22, wherein two input ends of the comparator CMP21 are respectively input with cnt_bin_width and set_bin_width signals of an internal register, an output end is connected with a selection end of the multiplexer MUX21, an output end of the multiplexer MUX21 is connected with one input end through the NOT21 after passing through the trigger DFF21, and the other input end is directly connected with an output end of the trigger DFF21 and outputs js_en signals; the cnt_bin_width signal is input to an input end of the comparator CMP22, the set_bin_width signal is input to the other input end of the comparator CMP22 after passing through the subtracter SUB21, the other input end of the subtracter SUB21 is input with the signal 1, and the output end of the comparator CMP22 outputs the sig1 signal;

the initial signal processing unit comprises a NOT22 and a NOR gate NOR22, wherein two input ends of the NOR gate NOR22 are respectively a counting start run signal and a busy signal being counted, an output end of the NOR gate NOR22 is used for providing sig2 signals for the first counting unit and the second counting unit, and js_en signals are output after passing through the NOT gate NOT 22;

the first counting unit includes an AND gate AND21, a multiplexer MUX22, a flip-flop DFF22, a multiplexer MUX23, an adder ADD21, AND a flip-flop DFF23;

the two input ends of the AND gate AND21 are respectively input with js_en signal AND sig1 signal, the output end is connected with one end of a multiplexer MUX22, the other end of the multiplexer MUX22 is input with 1, the selection end is input with sig2 signal, the output end is connected with the input end of a trigger DFF22, the output end of the trigger DFF22 outputs rst_1 signal, the input end of a multiplexer MUX23 is respectively 0 AND1, AND the selection end is input with js_en signal; the output end is connected with one end of the adder ADD21, the output end of the adder ADD21 outputs a cnt1 signal after passing through the trigger DFF23, the cnt1 signal is fed back to the other input end of the adder ADD21, the reset end of the trigger DFF23 inputs an rst_1 signal, and the clock input end inputs a pulse signal;

the second counting unit includes an AND gate AND22, a multiplexer MUX24, a flip-flop DFF24, a multiplexer MUX25, an adder ADD22, AND a flip-flop DFF25;

the two input ends of the AND gate 22 are respectively input with a js_en signal AND a sig1 signal, the output end is connected with one end of a multiplexer MUX24, the other end of the multiplexer MUX24 is input with 1, the selection end is input with a sig2 signal, the output end is connected with the input end of a trigger DFF24, the output end of the trigger DFF24 is output with a rst_2 signal, the input ends of a multiplexer MUX25 are respectively 0 AND1, AND the selection end is input with a js_en signal; the output end is connected with one end of the adder ADD22, the output end of the adder ADD22 outputs a cnt2 signal after passing through the trigger DFF25, the cnt2 signal is fed back to the other input end of the adder ADD22, the reset end of the trigger DFF25 inputs the rst_2 signal, and the clock input end inputs the pulse signal.

2. The ZYNQ-based satellite-borne high-frequency lidar photon counting system of claim 1, wherein the programmable logic unit PL further comprises an AXI protocol conversion module.

3. The ZYNQ-based satellite-borne high-repetition-frequency lidar photon counting system according to claim 1, wherein the control module comprises a rising edge detection circuit, AND the rising edge detection circuit comprises a trigger DFF1, a trigger DFF2, a NOT1, an AND gate AND1 AND a trigger DFF3 which are sequentially arranged; the other input end of the AND gate is connected with the output end of the trigger DFF1, the input end of the trigger DFF1 is input with a trigger signal, two input ends of the comparator CMP1 in the control module are respectively input with a bin width cnt_bin_width AND a bin width set value set_bin_width, two input ends of the comparator CMP2 are respectively input with a bin number cnt_bin_num AND a bin number set value set_bin_num, the output ends of the two comparators are correspondingly connected with the two input ends of the AND gate AND2, the output end of the AND gate AND2 is connected with the input end of the trigger DFF5, the trigger DFF5 is used for outputting a counting completion signal done AND connecting to the selection end of the multiplexer MUX1, one input end of the multiplexer MUX1 is connected with the output end of the rising edge detection circuit, the other input end of the multiplexer MUX1 is connected with the input end of the trigger DFF4, AND the trigger DFF4 outputs a counting busy signal.

4. The ZYNQ-based satellite-borne high-repetition frequency laser radar photon counting system according to claim 1, wherein a comparator CMP31, a comparator CMP32 AND a comparator CMP33 in the output module are connected to the input terminal of the AND gate AND31, a bin width cnt_bin_width AND a bin width set value set_bin_width are respectively AND correspondingly input to the two input terminals of the comparator CMP31, a bin number cnt_bin_num AND a bin number set value set_bin_num are respectively AND correspondingly input to the two input terminals of the comparator CMP32, AND a cumulative number cnt_accum_num AND a cumulative number set_accum_num are respectively AND correspondingly input to the two input terminals of the comparator CMP 33;

the two ends of the subtracter SUB31 are respectively corresponding to input signals set_bin_num and1, the output end is connected with one input end of the comparator CMP34, the read-RAM address rd_ram_addr is used as the input end of the trigger DFF32, after the trigger DFF32, the trigger DFF33 and the trigger DFF34 are sequentially arranged, the output end of the trigger DFF34 is connected with the other input end of the comparator CMP34, the output end of the comparator CMP34 outputs a signal sig31 and is used as a gating signal of the multiplexer MUX31, and the output end of the trigger DFF33 outputs the signal sig32;

the comparator CMP35 has one end for inputting the signal sig32 AND the other end for inputting 1, the output end is connected with one input end of the adder AND32, the comparator CMP36 has one end for inputting the signal sig32 AND the other end for inputting the bin number setting value set_bin_num, the output end is connected with the other input end of the adder AND32, the third input end of the adder AND32 inputs the accumulation completion flag flag_out signal, the output end outputs the signal sig33, one end of the multiplexer MUX32 inputs the read RAM data rd_ram_data signal, the output end outputs the accumulation data data_accum signal after passing through the trigger DFF35, the accumulation data data_accum signal is fed back to the other input end of the multiplexer MUX32, AND the selection end of the multiplexer MUX32 inputs the accumulation completion flag flag_out signal;

the multiplexer MUX33 has an input terminal for inputting 0 and an input terminal for inputting 1, and an output terminal for outputting an accumulated address_accum signal after passing through the adder ADD31 and the flip-flop DFF36, and the accumulated address_accum signal is fed back to the other input terminal of the adder ADD31, and the selection terminal of the multiplexer MUX33 inputs the signal sig33.

5. The ZYNQ-based satellite-borne high-repetition frequency lidar photon counting system of claim 1, wherein the model of the ZYNQ chip is ZYNQ-7020.

6. The ZYNQ-based satellite-borne high-repetition frequency lidar photon counting system of claim 1, wherein the processor system PS comprises two ARM Cortex-A9.

7. The ZYNQ-based satellite-borne high-repetition frequency lidar photon counting system of claim 1, further comprising

A laser for emitting laser light and outputting a trigger signal synchronized with the laser light;

the comparator is used for discriminating the trigger signal to obtain a starting signal serving as a sample;

and the photon counting detector is used for detecting the echo signals and outputting pulse signals with density proportional to light intensity.

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