CN115016848A - Instruction processing method, device, chip, board, device and medium - Google Patents

Abstract

The present disclosure provides an instruction processing method, device, chip, board, device and medium, wherein the method includes: acquiring a first calculation instruction to be executed at the current moment; after determining that the first calculation instruction is to be merged In the case of an instruction, the cached computing instruction is searched in the cache space; when it is determined that the found cached computing instruction and the first computing instruction satisfy the instruction merging condition, the first computing instruction and the first computing instruction are combined. The cached computing instructions are merged.

Description

Instruction processing method, device, chip, board, device and medium

technical field

The present disclosure relates to the field of computer technology, and in particular, to an instruction processing method, device, chip, board, device, and medium.

Background technique

In the process of processing instructions, the processor usually executes the received instructions in a certain order. The process of executing the instruction mainly includes the process of accessing the storage space in the processor and the process of calculating the data. The computing process of data needs to call the processing hardware computing device, and the execution process of the corresponding computing process in each instruction in this process needs to occupy one clock cycle of the hardware computing device. If the number of instructions to be processed is large, the existing instruction processing process will affect the processor's processing efficiency of instructions, thereby reducing the processing performance of the processor.

SUMMARY OF THE INVENTION

Embodiments of the present disclosure at least provide an instruction processing method, apparatus, chip, board, device, and medium.

In a first aspect, an embodiment of the present disclosure provides an instruction processing apparatus, the instruction processing apparatus includes: an instruction receiving unit and an instruction merging unit: the instruction receiving unit is configured to obtain a first calculation instruction to be executed at the current moment; The instruction merging unit is configured to search for a cached calculation instruction in the cache space when it is determined that the first calculation instruction is an instruction to be merged; and when it is determined that the found cached calculation instruction and all When the first calculation instruction satisfies the instruction merging condition, the first calculation instruction and the cached calculation instruction are merged.

In an optional implementation manner, the instruction merging unit is further configured to: determine an instruction identification of the first calculation instruction, wherein the instruction identification is used to indicate whether the first calculation instruction is to be Merge instruction; in the case that the identification content of the instruction identification identifier is determined as the target content, determine that the first calculation instruction is the instruction to be merged.

In an optional implementation manner, the instruction merging unit is further configured to: determine, based on a preset merging strategy, whether the cached computing instruction and the first computing instruction satisfy the instruction merging condition; wherein the The instruction merging condition is a condition associated with the instruction merging strategy.

In an optional implementation manner, the instruction merging unit is further configured to: in the case that the merging strategy is the first strategy, obtain the instruction attribute information of the cached computing instruction, obtain the first information, and Obtain the instruction attribute information of the first calculation instruction, and obtain the second information; wherein, the first strategy is used to instruct the combination of calculation instructions based on the instruction attribute information; determine the first information and the second information. The information matching degree between them is determined; if the information matching degree satisfies the preset matching degree requirement, it is determined that the cached computing instruction and the first computing instruction satisfy the instruction merging condition.

In an optional implementation manner, the first information includes a plurality of first sub-information, and the second information includes a plurality of second sub-information; the instruction merging unit is further configured to: respectively determine corresponding attribute information The sub-matching degree values of the first sub-information and the second sub-information are obtained, and a plurality of sub-matching degree values are obtained; the information matching degree between the first information and the second information is determined based on the plurality of sub-matching degree values; The attribute information includes: the number of instruction channels, the instruction calculation type, and the instruction data type.

In an optional implementation manner, the instruction merging unit is further configured to: in the case that the merging strategy is the second strategy, determine the remaining cache space of the cache space; wherein, the second strategy uses Instructing to combine calculation instructions based on the size of the remaining space in the cache space; in the case that it is determined that the remaining cache space does not meet the cache requirements of the first calculation instruction, determine that the cached calculation instruction and the first calculation instruction The instruction satisfies the instruction merging condition.

In an optional implementation manner, the instruction merging unit is further configured to: when the merging strategy is the third strategy, obtain the instruction quantity of the cached computing instructions in the cache space; wherein, the The third strategy is used to instruct the combination of computing instructions based on the preset number of instructions; if it is determined that the information on the number of instructions satisfies the requirement of the number of instructions, it is determined that the cached computing instruction and the first computing instruction satisfy the instruction merging condition .

In an optional implementation manner, the instruction processing apparatus further includes: an instruction scheduling unit; and the instruction merging unit, configured to merge the cached computing instruction and the first computing instruction to obtain a target computing instruction ; the instruction scheduling unit is configured to receive the target computing instruction sent by the instruction merging unit, and send the target computing instruction to a computing device for computing processing.

In an optional implementation manner, the instruction merging unit is further configured to: determine the instruction calculation type of the first calculation instruction and/or the cached calculation instruction; When the instruction merging mode of the first calculation instruction and the cached calculation instruction is the first merge mode, the cached calculation instruction and the first calculation instruction are merged to obtain the target calculation instruction.

In an optional implementation manner, the instruction merging unit is further configured to: determine, based on the instruction calculation type, that the instruction merging mode of the first calculation instruction and the cached calculation instruction is the second merge mode. In this case, send a target control instruction to the instruction scheduling unit; the instruction scheduling unit is configured to, after receiving the target control instruction, send the first calculation instruction and the The cache calculation instruction is sent to the calculation device for calculation processing.

In an optional implementation manner, the instruction processing apparatus further includes: an instruction scheduling unit; the instruction scheduling unit is further configured to find that the cached computing instruction and the first computing instruction are not satisfied In the case of the instruction merging condition, the cached computing instruction is sent to the computing device for processing, and the first computing instruction is cached in the cache space.

In a second aspect, an embodiment of the present disclosure further provides an instruction processing method, including: acquiring a first calculation instruction to be executed at the current moment; and in the case of determining that the first calculation instruction is an instruction to be merged, in a cache space Find the cached computing instruction; in the case that it is determined that the found cached computing instruction and the first computing instruction satisfy the instruction merging condition, combine the first computing instruction and the cached computing instruction .

In a third aspect, an embodiment of the present disclosure further provides a chip, including: an instruction distribution apparatus, an instruction processing apparatus, and a computing apparatus; the instruction distribution apparatus is configured to distribute to the instruction processing apparatus a first calculation to be executed at the current moment instruction; the instruction processing device is used to obtain the first calculation instruction to be executed at the current moment; when it is determined that the first calculation instruction is the instruction to be merged, the cached calculation instruction is searched in the cache space; Under the condition that the found cached calculation instruction and the first calculation instruction satisfy the instruction merging condition, the first calculation instruction and the cached calculation instruction are merged to obtain a target calculation instruction; the A computing device, configured to obtain operands for executing the target computing instruction, and execute the target computing instruction based on the operands.

In a fourth aspect, an embodiment of the present disclosure further provides a board, which is characterized by comprising: a package structure encapsulating at least one chip according to the third aspect.

In a fifth aspect, an embodiment of the present disclosure further provides a computer device, including the chip as described in the third aspect, or the board as described in the fourth aspect.

In a sixth aspect, an embodiment of the present disclosure further provides a computer-readable storage medium, where a computer program is stored on the computer-readable storage medium, and the computer program is executed by a processor to execute the first aspect, or any one of the first aspect. steps in one possible implementation.

In order to make the above-mentioned objects, features and advantages of the present disclosure more obvious and easy to understand, the preferred embodiments are exemplified below, and are described in detail as follows in conjunction with the accompanying drawings.

Description of drawings

In order to explain the technical solutions of the embodiments of the present disclosure more clearly, the following briefly introduces the accompanying drawings required in the embodiments, which are incorporated into the specification and constitute a part of the specification. The drawings illustrate embodiments consistent with the present disclosure, and together with the description serve to explain the technical solutions of the present disclosure. It should be understood that the following drawings only show some embodiments of the present disclosure, and therefore should not be regarded as limiting the scope. Other related figures are obtained from these figures.

FIG. 1 shows a flowchart of an instruction processing method provided by an embodiment of the present disclosure;

FIG. 2 shows a schematic diagram of an instruction processing apparatus provided by an embodiment of the present disclosure;

FIG. 3 shows a schematic structural diagram of a chip provided by an embodiment of the present disclosure;

FIG. 4 shows a schematic diagram of an instruction processing apparatus provided by an embodiment of the present disclosure;

FIG. 5 shows a schematic diagram of a chip provided by an embodiment of the present disclosure;

FIG. 6 shows a schematic diagram of a board provided by an embodiment of the present disclosure.

Detailed ways

In order to make the purposes, technical solutions and advantages of the embodiments of the present disclosure more clear, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only These are some, but not all, embodiments of the present disclosure. The components of the disclosed embodiments generally described and illustrated in the drawings herein may be arranged and designed in a variety of different configurations. Therefore, the following detailed description of the embodiments of the disclosure provided in the accompanying drawings is not intended to limit the scope of the disclosure as claimed, but is merely representative of selected embodiments of the disclosure. Based on the embodiments of the present disclosure, all other embodiments obtained by those skilled in the art without creative work fall within the protection scope of the present disclosure.

It should be noted that like numerals and letters refer to like items in the following figures, so once an item is defined in one figure, it does not require further definition and explanation in subsequent figures.

The term "and/or" in this paper only describes an association relationship, which means that there can be three kinds of relationships, for example, A and/or B, which can mean: the existence of A alone, the existence of A and B at the same time, the existence of B alone. a situation. In addition, the term "at least one" herein refers to any combination of any one of the plurality or at least two of the plurality, for example, including at least one of A, B, and C, and may mean including from A, B, and C. Any one or more elements selected from the set of B and C.

Through research, it is found that in the related art, the calculation process of data needs to call a hardware computing device for processing, and the execution process of the corresponding calculation process in each instruction in this process needs to occupy one clock cycle of the hardware computing device. If the number of instructions to be processed is large, the existing instruction processing process will affect the processor's processing efficiency of instructions, thereby reducing the processing performance of the processor. Based on this, the inventor found that some of the instructions in all the instructions can be combined for processing, so as to improve the throughput rate of the computing device for data, thereby improving the performance of the processor. Here, combining and processing part of the instructions can be understood as processing the part of the instructions by occupying the same clock cycle, thereby improving the processing efficiency and processing performance of the processor, thereby shortening the processing time of the processor for the instructions.

The inventor found that in the process of merging the instructions, the instructions to be merged can be set in the program by the programmer, and the instructions to be merged can be merged through the pre-written program. However, the inventor found that this instruction merging method has certain limitations. For example, if there are too many merging conditions, the program written by the programmer will be too complicated, which increases the probability of loopholes or defects in the program, thus leading to instruction merging. The accuracy of the results is not ideal.

Based on the above research, the present disclosure provides an instruction processing method, device, chip, board, device and medium. In the embodiment of the present disclosure, first, the first calculation instruction to be executed at the current moment may be obtained, and after it is determined that the first calculation instruction is the calculation instruction to be merged, the cached calculation instruction may be searched in the cache space, and stored in the cache space. When it is determined that the cached calculation instruction and the first calculation instruction satisfy the instruction merging condition, the first calculation instruction and the cached calculation instruction are merged, and the merged instruction is processed. Through the above processing method, the calculation instructions satisfying the instruction combining condition can be automatically combined, so that the combined instructions can be processed by the processor, so that the processing efficiency of the processor can be improved, and the processing speed of the instructions by the processor can be accelerated.

In order to facilitate the understanding of this embodiment, an instruction processing method disclosed in the embodiment of the present disclosure is first introduced in detail. The device includes, for example, a terminal device or a server or other processing device, and the instruction processing method can be implemented by the processor calling computer-readable instructions stored in the memory.

Referring to FIG. 1 , which is a flowchart of an instruction processing method provided by an embodiment of the present disclosure, the method includes steps S101 to S105 , and the processes described in the steps S101 to S105 may be applied to an instruction processing apparatus, wherein the The instruction processing device is a device in a processor of a chip, and the chip is a chip in the above-mentioned computer equipment, specifically:

S101: Acquire a first calculation instruction to be executed at the current moment.

In the embodiment of the present disclosure, the instruction processing apparatus of the processor may receive the instruction to be executed (ie, the above-mentioned first calculation instruction) distributed by the instruction distribution apparatus in the processor. Here, the first calculation instruction may be any calculation instruction, for example, may be a macc instruction, that is, a multiply-accumulate instruction. For example, the macc instruction may be: macc1(a0,b0), where a0 and b0 are register identifiers. Wherein, the register identifier can be understood as a register for storing the operand for executing the first calculation instruction macc1.

S103: In a case where it is determined that the first calculation instruction is an instruction to be merged, search for a cached calculation instruction in the cache space. Here, the cached calculation instruction is a calculation instruction to be merged that is cached in the cache space before the first calculation instruction is received.

In the embodiment of the present disclosure, after the above-mentioned first calculation instruction is obtained, the instruction attribute information of the first calculation instruction may be obtained, so as to determine whether the first calculation instruction is mergeable based on the instruction attribute information of the first calculation instruction instruction, and when it is determined that the first calculation instruction is an instruction that can be combined, the first calculation instruction is determined as an instruction to be combined.

Here, the instruction attribute information may be used to indicate at least one of the following: the instruction calculation type, the number of instruction sending channels occupied by the instruction, and the data type of the operand corresponding to the instruction.

For example, data types may contain binary data, octal data, decimal data, hexadecimal data, and the like. The instruction calculation type can be used to represent the operation strategy of the first calculation instruction, such as dot product calculation, addition, subtraction, multiplication and division. The number of instruction sending channels occupied by an instruction may be understood as the number of instruction sending channels occupied by the first computing instruction in the process of sending the first computing instruction to the computing device by the instruction processing apparatus. Here, the computing device may be understood as a unit in the processor that executes the first computing instruction.

Taking the instruction attribute information as the number of instruction sending channels occupied by the instruction as an example, after the instruction processing device obtains the first calculation instruction, it can send the instruction to the instruction sending channel preset between the instruction processing device and the computing device. A computing device, so that the computing device performs data processing on the acquired first computing instruction. If the instruction processing apparatus sends the first calculation instruction to the computing apparatus, the number of channels of the instruction sending channel occupied is less than the number of channels of the above preset instruction sending channel. At this time, if the first calculation instruction is selected to be sent to the computing device for processing in one clock cycle, a large amount of resources will be wasted.

Assuming that the above preset number of command sending channels is 8 channels, and the number of command sending channels occupied by the first calculation command is 4 channels, at this time, the command sending channel occupied by the first calculation command can be determined The number is less than the preset number of command sending channels. At this time, in order to save the resources of the processor, the first calculation instruction may be combined with other calculation instructions before being sent to the computing device. At this time, it may be determined that the first calculation instruction is an instruction to be combined.

Take the instruction attribute information as the instruction calculation type as an example. It is assumed that the command calculation type of the preset commands that can be combined is dot product calculation. After the instruction receiving unit receives the first calculation instruction, it can obtain the instruction calculation type of the first calculation instruction. If the instruction calculation type is dot product calculation, then the first calculation instruction is an instruction that can be combined. It is determined that the first calculation instruction is an instruction to be combined.

Take the instruction attribute information as the data type as an example. It is assumed that the data type of the pre-set mergeable instructions is binary data. After the instruction receiving unit receives the first calculation instruction, it can obtain the data type of the first calculation instruction. If the data type is binary data, then the first calculation instruction is an instruction that can be combined. At this time, the first calculation instruction can be determined. A calculation instruction is an instruction to be combined.

After it is determined that the first computing instruction is the instruction to be merged, the cached computing instruction may be searched in the cache space of the processor. Here, the number of the found cached computing instructions may be one or more.

S105: If it is determined that the found cached calculation instruction and the first calculation instruction satisfy an instruction merging condition, perform a merge process on the first calculation instruction and the cached calculation instruction.

When a cached calculation instruction is found in the cache space, it can be determined whether the cached calculation instruction and the first calculation instruction satisfy the instruction merging condition.

Here, a merging strategy of the cached computing instruction and the first computing instruction may be determined, and based on the merging strategy, it is determined whether the cached computing instruction and the first computing instruction satisfy the instruction merging condition; wherein, the instruction merging condition is a condition associated with the instruction merging strategy.

Wherein, the merging strategy may be used to instruct to merge the cached computing instruction and the first computing instruction based on the instruction attribute information; or, to instruct to merge the cached computing instruction and the first computing instruction based on the size of the remaining space in the cache space; Or, it is used to instruct to combine the cached computing instruction and the first computing instruction based on a preset number of instructions. It can be understood that the command merging conditions corresponding to different merging strategies are different.

If the merging policy is used to instruct to merge the cached computing instruction and the first computing instruction based on the instruction attribute information, then it may be determined based on the instruction attribute information of the cached computing instruction and the instruction attribute information of the first computing instruction that the cached computing instruction is the same as the first computing instruction. Whether the first calculation instruction satisfies the instruction merging condition.

Continuing the above example, in the case where the number of channels of the above preset command sending channel is 8 channels, the cached computing instruction and the first computing instruction can be determined based on the instruction attribute information of the cached computing instruction and the first computing instruction respectively. Calculate whether the channel number of the command sending channel occupied by the command and whether it is less than or equal to the preset channel number of the command sending channel. If yes, it may be determined that the cached computing instruction and the first computing instruction satisfy the instruction merging condition.

Specifically, it is assumed that when the instruction processing apparatus sends the cached calculation instruction to the computing apparatus, the number of channels occupied by the instruction sending channel is 4, and when the instruction processing apparatus sends the first calculation instruction to the computing apparatus, the occupied instruction sending channel The number of channels of the channel is 4, then, the sum of the number of channels occupied by the cached calculation instruction and the first calculation instruction is 8 channels. At this time, it can be determined that the cached computing instruction and the first computing instruction satisfy the instruction merging condition. Next, the first calculation instruction and the cached calculation instruction may be merged.

If the merging policy is used to instruct to merge the cached computing instruction and the first computing instruction based on the size of the remaining space in the cache space, it may be determined whether the cached computing instruction and the first computing instruction satisfy the instruction merging condition based on the size of the remaining space.

If the merging policy is used to instruct the merging of computing instructions based on the preset number of instructions, then it may be determined whether the cached computing instruction and the first computing instruction satisfy instruction merging based on the number of instructions of the cached computing instruction and the number of instructions of the first computing instruction condition.

It can be seen from the above description that the calculation instructions satisfying the instruction merging condition can be automatically merged, so that the combined instructions can be processed by the processor, thereby improving the processing efficiency of the processor and speeding up the processing speed of the processor on the instructions.

In an optional implementation manner, in the above step S103, it is determined that the first calculation instruction is an instruction to be combined, which specifically includes the following process:

S1031: Determine an instruction identification identifier of the first calculation instruction, where the instruction identification identifier is used to indicate whether the first calculation instruction is an instruction to be combined.

S1032: In the case that the identification content of the instruction identification identifier is determined to be the target content, determine that the first calculation instruction is the instruction to be merged.

In the embodiment of the present disclosure, a pre-combination condition and a post-combination condition may be preset, wherein the pre-combination condition is used to determine whether the first calculation instruction is an instruction to be combined, and the post-combination condition is used to determine the first calculation instruction and the post-combination condition. Whether the found cached computing instructions can be combined, that is, the above-mentioned instruction combining condition may be the above-mentioned post-combining condition.

Here, an instruction identification identifier of the first calculation instruction may be determined, and whether the first calculation instruction satisfies the prerequisite merging condition is determined according to the instruction identification identifier. In the case where it is determined that the first calculation instruction satisfies the prerequisite merging condition, the first calculation instruction may be determined as the instruction to be merged.

Here, the instruction identification identifier of the first computing instruction may be determined in the following manner.

The instruction identification identifier is determined in the instruction content of the first calculation instruction.

Here, the instruction content of the first calculation instruction is acquired, and then the instruction identification identifier is searched in the instruction content. After finding the identification content of the instruction identification mark of the first calculation instruction, the identification content can be matched with the target content, and if the identification content is the same as the target content, the first calculation instruction is determined to be merged instruction.

For example, if the first calculation instruction is macc, then the instruction content of the first calculation instruction may be: macc(a0, b0, c), where a0 and b0 are register identifiers. Wherein, the register identifier can be understood as a register for storing the operand for executing the first calculation instruction macc1, and c can be understood as the above-mentioned instruction identifier.

It can be seen from the above description that, in the embodiment of the present disclosure, the identification content of the instruction identification identifier can be used to indicate whether the instruction processing apparatus outputs the first calculation instruction to the computing apparatus immediately after receiving the first calculation instruction. In the case that the identified content is the target content, it can be determined that the first calculation instruction does not need to be output immediately, that is, the first calculation instruction satisfies the prerequisite merging condition, and the first calculation instruction is determined as the instruction to be merged.

In the above-mentioned embodiment, after the instruction content of the first calculation instruction is acquired, the instruction identification mark in the instruction content can be determined, and when the identification content of the instruction identification mark is the target content, the first calculation instruction is determined. The prerequisite merging condition is satisfied, so that the first calculation instruction is determined as the instruction to be merged. Through this processing method, the flexibility of setting the instructions to be merged can be improved to meet various merging requirements of users.

In the embodiment of the present disclosure, following the above method, the instruction identification identifier of each first computing instruction can be determined.

The instruction identification identifier may be set in the instruction content of each first calculation instruction. After acquiring each first calculation instruction, the instruction processing device may search for the instruction identification mark in the instruction content of each first calculation instruction, so as to determine whether the first calculation instruction is pending according to the identification content of the instruction identification mark. Merge instructions.

Here, in addition to indicating whether the first calculation instruction satisfies the prerequisite merging condition, the identification content of the instruction identification mark can also be used to determine whether the first calculation instruction satisfies the prerequisite merging condition through the identification content of the instruction identification mark. , an instruction that can be combined with the first computing instruction among the cached computing instructions contained in the cache space. For example, different identification contents may be set for different types of instructions to be merged, so that instructions to be merged of the same type are merged through the identification contents.

In an optional implementation manner, in the above step S105, it is determined that the cached computing instruction and the first computing instruction are found to satisfy the instruction merging condition, which specifically includes the following process:

(1), in the case where the merging strategy is the first strategy, obtain the instruction attribute information of the cached calculation instruction, obtain the first information, and obtain the instruction attribute information of the first calculation instruction, and obtain the second information; wherein, the first strategy is used to instruct the merging of computing instructions based on instruction attribute information;

(2), determining the degree of information matching between the first information and the second information;

(3) In the case that the information matching degree satisfies the preset matching degree requirement, determine that the cached computing instruction and the first computing instruction satisfy the instruction merging condition.

In the case where the merging strategy is the first strategy, the instruction attribute information of the cached computing instruction and the first computing instruction can be obtained respectively, so as to obtain the first information corresponding to the cached computing instruction (equivalent to the cached computing instruction corresponding to the The attribute value of the attribute information of the instruction) and the second information corresponding to the first calculation instruction (equivalent to the attribute value of the attribute information corresponding to the first calculation instruction).

Here, the instruction attribute information may be used to indicate at least one of the following: the instruction calculation type, the number of instruction sending channels occupied by the instruction, and the data type of the operand corresponding to the instruction.

For example, data types may contain binary data, octal data, decimal data, hexadecimal data, and the like. The instruction calculation type can be used to indicate the operation mode of the first calculation instruction, such as dot product calculation, addition, subtraction, multiplication and division. The number of instruction sending channels occupied by an instruction can be understood as the number of instruction sending channels occupied by the instruction in the process of sending the corresponding instruction to the computing device by the instruction processing apparatus. Here, a computing device may be understood as a unit in a processor that executes the above-mentioned instructions.

It can be seen from the above description that the first information includes a plurality of first sub-information, wherein the plurality of first sub-information includes the attribute values of the following instruction attribute information of the cached calculation instruction: instruction calculation type, instruction transmission channel occupied by the instruction The number, the data type of the operand corresponding to the instruction; the second information includes multiple second sub-information, wherein the multiple second sub-information includes the attribute values of the following instruction attribute information of the first calculation instruction: instruction calculation type, The number of instruction sending channels occupied by the instruction (hereinafter referred to as the number of channels), and the data type of the operand corresponding to the instruction.

In this case, the instruction merging unit is further configured to: respectively determine the sub-matching degree values of the first sub-information and the second sub-information corresponding to the attribute information, to obtain multiple sub-matching degree values; and based on the multiple sub-matching degree values A degree of information matching between the first information and the second information is determined.

Here, the number of channels in the first sub-information and the number of channels in the second sub-information may be attribute values of the channel number attribute, and the data type in the first sub-information and the data type in the second sub-information may be attribute values of the data type attribute .

Next, the sub-matching degree values of the first sub-information and the second sub-information in each of the information groups may be determined to obtain a plurality of sub-matching degree values.

In the process of determining the sub-matching degree value between the first sub-information and the second sub-information in each information group, different matches may be set for different contents contained in the first sub-information and the second sub-information. Standards, including the following situations:

Case 1: The first sub-information is the data type of the cached calculation instruction, and the second sub-information is the data type of the first calculation instruction. At this time, it may be determined whether the data types of the first calculation instruction and the cached calculation instruction match.

In the embodiment of the present disclosure, the first data type of the operand corresponding to the first calculation instruction may be determined based on the foregoing second sub-information, and the second data type of the operand corresponding to the cached calculation instruction may be determined based on the foregoing first sub-information data type, and determine whether the first data type matches the second data type. In the case where the first data type matches the second data type, it is determined that the data type matches between the first computation instruction and the cached computation instruction. For example, in the case where the number systems indicated by the first data type and the second data type are both binary, it may be determined that the data types between the first computing instruction and the cached computing instruction match. At this time, it may be determined that the sub-matching degree value of the first sub-information and the second sub-information is a preset value (for example, 1/3).

Case 2: The first sub-information is the instruction calculation type of the cached calculation instruction, and the second sub-information is the instruction calculation type of the first calculation instruction. At this time, it may be determined whether the instruction calculation types match between the first calculation instruction and the cached calculation instruction.

In this embodiment of the present disclosure, the operation modes of the first calculation instruction and the cached calculation instruction may be determined based on the first sub-information and the second sub-information, respectively, and the operation modes of the first calculation instruction and the cached calculation instruction In the same case, it is determined that the instruction calculation type of the first calculation instruction and the cached calculation instruction match. For example, if it is determined that the operation modes of the first calculation instruction and the cached calculation instruction are both dot product operations, it may be determined that the instruction calculation types of the first calculation instruction and the cached calculation instruction match. At this time, it may be determined that the sub-matching degree value of the first sub-information and the second sub-information is a preset value (for example, 1/3).

Case 3: The first sub-information is the number of channels of the cached computing instruction, and the second sub-information is the number of channels of the first computing instruction. At this time, it may be determined whether the number of instruction sending channels occupied by the first calculation instruction matches the number of instruction sending channels occupied by the cached calculation instruction.

In this embodiment of the present disclosure, the number of instruction sending channels occupied by the first computing instruction, that is, the information on the number of first channels, may be determined based on the second sub-information, and the occupied by the cached computing instruction may be determined based on the first sub-information Indicates the number of channels sent by the command, that is, the second channel number information. Then, it can be determined whether the sum of the first channel number information and the second channel number information matches the above command sending channel, and the sum of the first channel number information and the second channel number information and the above preset command can be determined. In the case where the channel numbers of the sending channels match, it is determined that the channel number information between the first calculation instruction and the cached calculation instruction matches. At this time, it may be determined that the sub-matching degree value of the first sub-information and the second sub-information is a preset value (for example, 1/3).

Here, when the sum of the first channel number information and the second channel number information is less than or equal to the number of channels of the preset command sending channel, the channel between the first calculation command and the cached calculation command may be determined matching information.

For example, in the case where the total number of channels of the above-mentioned command sending channel is 8 channels, if the first channel number information corresponding to the above-mentioned first calculation command is 4 channels, the second channel corresponding to the calculation command has been cached. If the information is 4 channels, then it can be determined that the channel number information between the first calculation instruction and the cached calculation instruction matches.

After the multiple sub-matching degree values are obtained, a sum operation may be performed on the multiple sub-matching degree values to obtain the information matching degree between the first information and the second information. Therefore, the above-mentioned information matching degree may be the proportion of the matching content in the instruction attribute information. If there is a match, then the proportion of the matching content in the instruction attribute information is 2/3. In this case, the information matching degree between the first calculation instruction and the cached calculation instruction may be rounded to 67%.

In the case that the above-mentioned information matching degree satisfies the preset matching degree requirement, it may be determined that the cached calculation instruction and the first calculation instruction satisfy the post-merging condition. For example, if the information matching degree between the above-mentioned first calculation instruction and the cached calculation instruction is 100%, and the preset matching degree requirement is 80%, it can be determined that the cached calculation instruction and the first calculation instruction satisfy the post-combination requirement. Condition, that is, the command merge condition is satisfied.

In this embodiment of the present disclosure, when a cached computing instruction is included in the cache space, the information between the cached computing instruction and the first computing instruction may be determined based on the instruction attribute information of the cached computing instruction and the first computing instruction Whether the matching degree satisfies the preset matching degree requirement is judged whether the first computing instruction and the cached computing instruction meet the instruction merging condition, which provides a technical basis for combining the first computing instruction and the cached computing instruction.

In an optional implementation manner, in the above step S105, it is determined that the cached computing instruction and the first computing instruction are found to satisfy the instruction merging condition, which specifically further includes the following process:

(1), in the case that the merging strategy is a third strategy, obtain the instruction quantity information of the cached computing instructions in the cache space; wherein, the third strategy is used to instruct the calculation instruction based on the preset number of instructions. the merger;

(2) In a case where it is determined that the instruction quantity information satisfies the instruction quantity requirement, determine that the cached computing instruction and the first computing instruction satisfy an instruction merging condition.

When the merging strategy is the third strategy, if it is determined that the first computing instruction is an instruction to be merged, the instruction quantity of the cached computing instruction in the cache space can be obtained, and it is determined whether the instruction quantity information meets the instruction quantity requirement.

Here, after the programmer writes the program code, the instruction processing apparatus may determine the instruction for instructing the computer device to run based on the program code. Therefore, in the process of writing the program code, the programmer can also write the instruction merging condition in the program code. For example, the instruction merging condition can be the instruction quantity requirement, and the instruction quantity requirement can be used to indicate that the instruction merging process is performed The number of combined instructions (ie, the above-mentioned preset number of instructions).

During specific implementation, in the case where the preset number of instructions is n, if the instruction number information of the cached computing instruction in the cache space is n-1, it can be determined that the instruction number information meets the instruction number requirement, and the cached computing instruction can be determined. and the first calculation instruction to satisfy the instruction merging condition. It should be understood that the number of instructions requires n to be an integer greater than 2, such as 3, 4, 5, 6, and so on.

If the instruction number information of the cached computing instructions in the cache space is n, the n-1 cached computing instructions that are first cached in the cache space can be selected from the cached computing instructions according to the cache order of the cached computing instructions in the cache space. , and merge the n-1 cached computing instructions that are first cached in the cache space with the first computing instruction.

In the embodiment of the present disclosure, the instruction quantity requirement may be set, and if the instruction quantity information of the cached computation instruction in the cache space meets the instruction quantity requirement, it is determined that the cached computation instruction and the first computation instruction satisfy the instruction merging condition, Therefore, the process of command merging is improved, and the accuracy of command merging processing is improved.

In an optional implementation manner, in the above step S105, it is determined that the cached computing instruction and the first computing instruction are found to satisfy the instruction merging condition, which specifically further includes the following process:

(1), in the case where the merging strategy is the second strategy, determine the remaining cache space of the cache space; wherein, the second strategy is used to indicate that the calculation instruction is merged based on the size of the remaining space in the cache space;

(2) In a case where it is determined that the remaining cache space does not meet the cache requirement of the first computing instruction, determine that the cached computing instruction and the first computing instruction satisfy an instruction merging condition.

When the merging strategy is the second strategy, before storing the first computing instruction in the cache space, it may also be determined whether the remaining cache space in the cache space satisfies the cache requirement of the first computing instruction.

In the case that the remaining cache space does not meet the cache requirement of the first computing instruction, it may be determined that the cached computing instruction and the first computing instruction satisfy the instruction merging condition, and the cached computing instruction and the first computing instruction satisfy the instruction Merge processing.

In the case that the remaining cache space satisfies the cache requirement of the first computing instruction, the first computing instruction may be cached in the cache space until the remaining cache space does not meet the cache requirement, and will receive a message when the cache requirement is not met. The first computation instruction of the , and the cached computation instruction in the cache space are merged.

For example, a maximum number of caches y may be set for the above-mentioned cache space, and the maximum number of caches y may be used to indicate an upper limit of the number of cached computing instructions that can be stored in the cache space. When the remaining cache space of the cache space cannot completely cache the first computing instruction, it may be determined that the remaining cache space does not meet the cache requirement of the first computing instruction.

In the process of determining the remaining cache space of the cache space, the cache space occupied by the cached computing instructions in the cache space can be obtained, and the difference y-x between the maximum cache space y of the cache space and the occupied cache space x can be calculated , and the result of the difference y-x is determined as the remaining buffer space. If the difference y-x is smaller than the instruction size of the first calculation instruction, it is determined that the remaining cache space does not meet the cache requirement of the first calculation instruction, that is, it is determined that the cached calculation instruction and the first calculation instruction satisfy the instruction merging condition.

In the embodiment of the present disclosure, before storing the above-mentioned first calculation instruction in the cache space, it may also be determined whether the remaining cache space in the cache space satisfies the cache requirement of the first calculation instruction, and if the cache requirement does not meet the cache requirement In this case, it is determined that the cached calculation instruction and the first calculation instruction satisfy the instruction merging condition, so that the cached calculation instruction and the first calculation instruction are merged, which further improves the instruction merging process and improves the performance of the instruction merging process. accuracy.

In an optional implementation manner, in the above step S105, the first calculation instruction and the cached calculation instruction are combined and processed, which specifically includes the following process:

S1051: Combine the cached computing instruction and the first computing instruction to obtain a target computing instruction;

S1052: Send the target calculation instruction to a computing device for calculation processing.

In this embodiment of the present disclosure, after the above-mentioned cached computing instruction and the first computing instruction are combined, a target computing instruction can be obtained, and then the target computing instruction can be sent to a computing device, so that the computing device can be based on The target calculation instruction performs calculation processing on the data to be processed to obtain a calculation result.

In the specific implementation, taking the dot product operation in the convolution operation as an example, the process of the above-mentioned merging processing is shown:

For example, the instruction received by the processor is to calculate the dot product a·b of matrix a and matrix b. Here,

Then, the above a·b=a ₀ b ₀ +a ₁ b ₁ +...+a ₈ b ₈ . Therefore, based on the obtained instructions a·b, the following calculation instructions 0-calculation instructions 8 can be obtained respectively:

Calculation instruction 0: macc(a0, b0);

Calculation instruction 1: macc(a1, b1);

Calculation instruction 2: macc(a2, b2);

Calculation instruction 3: macc(a3, b3);

Calculation instruction 4: macc(a4, b4);

Calculation instruction 5: macc(a5, b5);

Calculation instruction 6: macc(a6, b6);

Calculation instruction 7: macc(a7, b7);

Calculation instruction 8: macc(a8, b8).

Here, the merging strategies for merging the above calculation instructions 0 to 8 are the above first strategy and the third strategy, that is, the calculation instructions 0 to 8 are merged based on the instruction attribute information and the instruction quantity requirement. If the above-mentioned number of instructions requires n=2, then the process of combining the above-mentioned calculation instructions 0-calculation instructions 8 is as follows:

Acquire calculation instruction 0, and determine the acquired calculation instruction 0: macc(a0, b0) as the first calculation instruction, and determine whether the calculation instruction 0 satisfies the prerequisite merging condition, and in the case that the calculation instruction 0 satisfies the prerequisite merging condition Next, the calculation instruction 0 is stored in the cache space as a cached calculation instruction.

Acquire calculation instruction 1, and determine the acquired calculation instruction 1: macc(a1, b1) as the first calculation instruction. Next, obtain the instruction calculation type of the first calculation instruction and the cached calculation instruction in the cache space respectively. . Since the instruction quantity information of the cached calculation instruction in the cache space is 1, the instruction quantity requirement n-1≤1 is satisfied. Therefore, if the instruction calculation type of calculation instruction 1 is the same as the instruction calculation type of calculation instruction 0, the calculation instruction 1 and calculation instruction 0 satisfy the instruction merging condition. At this time, the calculation instruction 1 and the calculation instruction 0 can be combined to obtain the target calculation instruction macc(a0, b0, a1, b1), and the target calculation instruction macc(a0, b0, a1, b1) is sent to the Calculation processing is performed in the computing device.

Acquire calculation instruction 2, and determine the acquired calculation instruction 2: macc(a2, b2) as the first calculation instruction, and determine whether the calculation instruction 2 satisfies the prerequisite merging condition, and in the case that the calculation instruction 2 satisfies the prerequisite merging condition Next, the calculation instruction 2 is stored in the cache space as a cached calculation instruction.

Acquire calculation instruction 3, and determine the acquired calculation instruction 3: macc(a3, b3) as the first calculation instruction. Next, obtain the instruction calculation type of the first calculation instruction and the cached calculation instruction in the cache space respectively . Since the instruction quantity information of the cached calculation instructions in the cache space is 1, the instruction quantity requirement n-1≤1 is satisfied. Therefore, if the instruction calculation type of calculation instruction 2 is the same as the instruction calculation type of calculation instruction 3, it can be determined that the Calculation instruction 3 and calculation instruction 2 satisfy the instruction merging condition. At this time, the calculation instruction 2 and the calculation instruction 3 can be combined to obtain the target calculation instruction macc(a2, b2, a3, b3), and the target calculation instruction macc(a2, b2, a3, b3) can be sent to Calculation processing is performed in the computing device.

Here, the merging process of the above calculation instructions 4-7 is as described above, and details are not repeated here.

Next, since the calculation instruction 8 is the last calculation instruction in the instructions for calculating a·b, therefore, different from the instruction type that does not require immediate output, the instruction type indicated by the instruction identification identifier of the calculation instruction 8 is different from the above instruction type. Can be an instruction type that needs immediate output. Therefore, the calculation instruction 8 does not satisfy the above-mentioned pre-combination condition, and in this case, the calculation instruction 8 can be directly sent to the computing device for calculation processing.

In this embodiment of the present disclosure, the cached computing instruction and the first computing instruction may be combined to obtain a target computing instruction, and the target computing instruction may be sent to a computing device for computing processing, so that the computing device can perform computing based on the target computing instruction. The instruction performs calculation processing on the data to be processed, and obtains the calculation result.

In an optional implementation manner, in the above step S1051, the cached calculation instruction and the first calculation instruction are combined to obtain the target calculation instruction, which specifically includes the following process:

(1), determine the instruction calculation type of the first calculation instruction and the cached calculation instruction;

(2) In the case that the instruction merge mode of the first calculation instruction and the cached calculation instruction is determined to be the first merge mode based on the instruction calculation type, merge the cached calculation instruction with the first merge mode. The calculation instructions are combined to obtain the target calculation instructions;

(3) In the case that the instruction merge mode of the first calculation instruction and the cached calculation instruction is determined to be the second merge mode based on the instruction calculation type, in the same instruction issuing cycle The computing instructions and the cached computing instructions are sent to the computing device for computing processing.

In the embodiment of the present disclosure, when combining the first computing instruction and the cached computing instruction, different instruction combining modes may be adopted, wherein the adopted instruction combining mode may be based on the first computing instruction and the cached computing instruction. The instruction calculation type of the calculation instruction is determined.

For example, the above-mentioned command merging mode can be divided into a first merging mode and a second merging mode. In the case that the instruction calculation type of the first calculation instruction and the cached calculation instruction are the same, the first merge mode may be adopted, and if the instruction calculation type of the first calculation instruction and the cached calculation instruction are different, the Second merge mode.

In the embodiment of the present disclosure, when the instruction merging mode is the above-mentioned first merging mode, firstly, the above-mentioned instruction calculation types corresponding to the above-mentioned first calculation instruction and the cached calculation instructions may be obtained respectively, and based on the above-mentioned instruction calculation type Indicated calculation mode, the elements in the first calculation instruction and the cached calculation instruction are combined. For example, in the case where the calculation method indicated by the instruction calculation type of the first calculation instruction and the cached calculation instruction is a dot product operation, the elements in the first calculation instruction and the cached calculation instruction may be combined to obtain target calculation instruction.

Here, an element may be used to indicate an operand for executing a corresponding calculation instruction, or may be used to indicate identification information of a register storing the operand.

Specifically, taking the above calculation instruction 0macc(a0, b0) and calculation instruction 1macc(a1, b1) as an example, after combining the calculation instruction 1macc(a1, b1) and the calculation instruction 0macc(a0, b0), you can The target calculation instruction macc(a0, b0, a1, b1) is obtained.

In addition, the merging mode indicated by the second merging mode may be parallel merging, that is, the first computing instruction and the cached computing instruction are sent to the computing device in the same instruction issuing cycle. For example, the cached computing instruction is the above-mentioned macc instruction, If the first calculation instruction is the initialization instruction minit, then the instruction merge mode corresponding to the first calculation instruction and the cached calculation instruction may be the second merge mode.

In the embodiment of the present disclosure, the instruction merging mode of the first computing instruction and the cached computing instruction can be determined based on the instruction computing type, so that the present disclosure can be applied to computing instructions of different instruction computing types, and the scope of application of the present disclosure is increased.

In an optional embodiment, the above method further includes the following process:

In the case where it is determined that the cached computing instruction and the first computing instruction do not meet the instruction merging condition, the cached computing instruction is sent to a computing device for processing, and the first computing instruction is sent to the computing device for processing. Instructions are cached into the cache space.

It can be seen from the above description that the merging strategy between the cached computing instruction and the first computing instruction includes at least one of the following: a first strategy, a second strategy and a third strategy, wherein each merging strategy corresponds to a sub-merging condition, which is respectively Sub-merge condition 1, sub-merge condition 2, and sub-merge condition 3.

Here, in the case where the instruction merging condition includes multiple sub-merging conditions, if the cached computing instruction and the first computing instruction do not satisfy the sub-merging condition corresponding to the first policy, the cached computing instruction may be sent to the computing device for processing , and cache the first computing instruction to the cache space.

Take the merging strategy as the first strategy and the third strategy as an example to introduce.

In the case that the cache space includes cached computing instructions, the instruction attribute information of the cached computing instructions can be obtained to obtain the first information, and the instruction attribute information of the first computing instructions can be obtained to obtain the second information. Then, it can be determined whether the information matching degree between the first information and the second information meets the preset matching degree requirement. At this time, it can be determined that the cached calculation instruction and the first calculation instruction do not meet the sub-merging condition 1. At this time, Regardless of whether the instruction quantity of the cached computing instructions satisfies the sub-merge condition 3, the cached computing instruction may be sent to the computing device for processing, and the first computing instruction is cached in the cache space.

In another embodiment, when the instruction merging condition includes multiple sub-merging conditions, if the cached computing instruction and the first computing instruction do not satisfy the sub-merging condition corresponding to the first policy, the first computing instruction may also be sent Go to the computing device for processing, and continue to identify the next acquired computing instruction to determine whether the next computing instruction can be combined with the cached computing instruction.

In the embodiment of the present disclosure, when it is determined that the cached computing instruction and the first computing instruction do not meet the instruction merging condition, the cached computing instruction can be sent to the computing device for processing, and the first computing instruction is cached into the cache space, thereby reducing the instruction processing delay caused by waiting for the merging when the computing instructions that can be merged are far apart.

Referring to FIG. 2, it is a schematic diagram of an instruction processing apparatus according to an embodiment of the present disclosure. Referring to FIG. 3 , a schematic diagram of a chip provided by an embodiment of the present disclosure is shown.

As shown in FIG. 3 , the chip includes an instruction distribution device 31 , an instruction processing device 32 , a scheduling unit 33 and a computing device 34 .

As shown in FIG. 3 , the instruction distribution apparatus is used to distribute the first calculation instruction to the instruction processing apparatus; the instruction processing apparatus is used to process the first calculation instruction based on the instruction processing apparatus provided by the embodiment of the present disclosure; the instruction scheduling unit uses The combined calculation instruction is sent to the corresponding computing device for processing.

In the embodiment of the present disclosure, the instruction processing apparatus 32 includes: an instruction receiving unit 10 and an instruction combining unit 20 .

The instruction receiving unit 10 is configured to acquire the first calculation instruction to be executed at the current moment.

In the embodiment of the present disclosure, the instruction processing apparatus of the chip may receive the instruction to be executed (ie, the above-mentioned first calculation instruction) distributed by the instruction distribution apparatus in the chip. Here, the first calculation instruction may be any calculation instruction, for example, may be a macc instruction, that is, a multiply-accumulate instruction. For example, the macc instruction may be: macc1(a0,b0), where a0 and b0 are register identifiers. Wherein, the register identifier can be understood as a register for storing the operand for executing the first calculation instruction macc1.

The instruction merging unit 20 is configured to search for a cached calculation instruction in the cache space when it is determined that the first calculation instruction is an instruction to be merged; wherein, the cached calculation instruction is received after the The first calculation instruction is cached into the to-be-combined calculation instruction in the cache space.

In the embodiment of the present disclosure, after the above-mentioned first calculation instruction is obtained, the instruction attribute information of the first calculation instruction may be obtained, so as to determine whether the first calculation instruction is mergeable based on the instruction attribute information of the first calculation instruction instruction, and when it is determined that the first calculation instruction is an instruction that can be combined, the first calculation instruction is determined as the instruction to be combined.

When a cached calculation instruction is found in the cache space, it can be determined whether the cached calculation instruction and the first calculation instruction satisfy the instruction merging condition. Specifically, it may be determined whether the cached computing instruction and the first computing instruction satisfy the instruction merging condition based on a preset merging policy; wherein the instruction merging condition is a condition associated with the instruction merging policy . On the condition that it is determined that the cached calculation instruction and the first calculation instruction satisfy the instruction merging condition, the first calculation instruction and the cached calculation instruction may be merged.

As can be seen from the above description, it is possible to realize automatic merging of computing instructions that satisfy the instruction merging conditions, so that the processing efficiency of the processor in the chip can be improved by processing the merged instructions, and the processing speed of the instructions by the processor can be accelerated; The programming workload of the programmer can also be reduced.

In an optional implementation manner, the instruction merging unit 20 is further configured to:

(1), determine the instruction identification mark of the first calculation instruction, wherein, the instruction identification mark is used to indicate whether the first calculation instruction is an instruction to be merged;

(2) In the case that the identification content of the instruction identification identifier is determined to be the target content, determine that the first calculation instruction is the instruction to be merged.

In the embodiment of the present disclosure, a pre-combination condition and a post-combination condition may be preset, wherein the pre-combination condition is used to determine whether the first calculation instruction is an instruction to be combined, and the post-combination condition is used to determine the first calculation instruction and the post-combination condition. Whether the found cached computing instructions can be combined, that is, the above-mentioned instruction combining condition may be the above-mentioned post-combining condition.

Here, an instruction identification identifier of the first calculation instruction may be determined, and whether the first calculation instruction satisfies the prerequisite merging condition is determined according to the instruction identification identifier. In the case where it is determined that the first calculation instruction satisfies the prerequisite merging condition, the first calculation instruction may be determined as the instruction to be merged. The specific process of judging whether the first calculation instruction satisfies the pre-combination condition is as described in the embodiment corresponding to step S1031 in the instruction processing method corresponding to FIG. 1 above, and will not be repeated here.

In the embodiment of the present disclosure, after the instruction content of the first calculation instruction is acquired, the instruction identification mark in the instruction content may be determined, and if the identification content of the instruction identification mark is the target content, the first calculation instruction is determined. The calculation instruction satisfies the pre-combination condition, so that the first calculation instruction is determined as the instruction to be merged. The specific process of determining whether the identification content of the instruction identification identifier is the target content is as described in step S1032 in the instruction processing method corresponding to FIG. 1 , which will not be repeated here.

In an optional implementation manner, the above-mentioned instruction merging unit is further used for:

(1), in the case where the merging strategy is the first strategy, obtain the instruction attribute information of the cached calculation instruction, obtain the first information, and obtain the instruction attribute information of the first calculation instruction, and obtain the second information; Wherein, the first strategy is used for instructing to combine calculation instructions based on instruction attribute information;

(2), determining the degree of information matching between the first information and the second information;

(3) In the case that the information matching degree satisfies the preset matching degree requirement, determine that the cached computing instruction and the first computing instruction satisfy the instruction merging condition.

When the merging strategy is the first strategy, the instruction attribute information of the cached computing instruction and the first computing instruction can be obtained respectively, so as to obtain the first information corresponding to the cached computing instruction and the second computing instruction corresponding to the first computing instruction. information.

In addition, in the embodiment of the present disclosure, the process of determining whether the information matching degree between the first information and the second information meets the preset matching degree requirement by the instruction merging unit is as described in the instruction processing method corresponding to FIG. 1 above. The implementation manner corresponding to step S105 is described, and details are not repeated here.

In this embodiment of the present disclosure, when a cached computing instruction is included in the cache space, the information between the cached computing instruction and the first computing instruction may be determined based on the instruction attribute information of the cached computing instruction and the first computing instruction Whether the matching degree satisfies the preset matching degree requirement is judged whether the first computing instruction and the cached computing instruction meet the instruction merging condition, which provides a technical basis for combining the first computing instruction and the cached computing instruction.

In an optional implementation manner, when the first information includes multiple first sub-information, and the second information includes multiple second sub-information, the above-mentioned instruction merging unit is further configured to:

Determine the sub-matching degree values of the first sub-information and the second sub-information corresponding to the attribute information, respectively, to obtain a plurality of sub-matching degree values; determine the difference between the first information and the second information based on the plurality of sub-matching degree values. The information matching degree; the attribute information includes: the number of instruction channels, the instruction calculation type and the instruction data type.

The specific implementation process is as described in the first to third situations in the foregoing embodiment, and details are not repeated here.

In an optional implementation manner, the above-mentioned instruction merging unit is further used for:

(1), in the case where the merging strategy is the second strategy, determine the remaining cache space of the cache space; wherein, the second strategy is used to indicate that the calculation instruction is merged based on the size of the remaining space in the cache space;

(2) In a case where it is determined that the remaining cache space does not meet the cache requirement of the first computing instruction, determine that the cached computing instruction and the first computing instruction satisfy an instruction merging condition.

When the merging strategy is the second strategy, the process of determining whether the remaining cache space meets the cache requirement of the first computing instruction is as described in the embodiment corresponding to step S105 in the instruction processing method corresponding to FIG. 1 above. No longer.

In the embodiment of the present disclosure, before storing the above-mentioned first calculation instruction in the cache space, it may also be determined whether the remaining cache space in the cache space satisfies the cache requirement of the first calculation instruction, and if the cache requirement does not meet the cache requirement In this case, it is determined that the cached calculation instruction and the first calculation instruction satisfy the instruction merging condition, so that the cached calculation instruction and the first calculation instruction are merged, which further improves the instruction merging process and improves the performance of the instruction merging process. accuracy.

In an optional implementation manner, the above-mentioned instruction merging unit is further used for:

(1), in the case that the merging strategy is a third strategy, obtain the instruction quantity of the cached computing instructions in the cache space; wherein, the third strategy is used to indicate the calculation instruction based on the preset number of instructions. merge;

(2) In a case where it is determined that the instruction quantity information satisfies the instruction quantity requirement, determine that the cached computing instruction and the first computing instruction satisfy an instruction merging condition.

When the merging strategy is the third strategy, the process of determining whether the number of instructions of the cached computing instructions in the cache space meets the requirement of the number of instructions is as described in the embodiment corresponding to step S105 in the instruction processing method corresponding to FIG. 1 above. , and will not be repeated here.

In the embodiment of the present disclosure, the instruction quantity requirement may be set, and if the instruction quantity information of the cached computation instruction in the cache space meets the instruction quantity requirement, it is determined that the cached computation instruction and the first computation instruction satisfy the instruction merging condition, Therefore, the process of command merging is improved, and the accuracy of command merging processing is improved.

In an optional implementation manner, the above-mentioned instruction processing apparatus further includes: an instruction scheduling unit.

the instruction combining unit, configured to combine the cached computing instruction and the first computing instruction to obtain a target computing instruction;

The instruction scheduling unit is configured to receive the target computing instruction sent by the instruction merging unit, and send the target computing instruction to a computing device for computing processing.

In the embodiment of the present disclosure, the process of combining the cached computing instruction and the first computing instruction to obtain the target computing instruction, and sending the target computing instruction to the computing device is as described in the instruction processing method corresponding to FIG. 1 above. The implementation manner corresponding to step S105 is described, and details are not repeated here.

In this embodiment of the present disclosure, the cached computing instruction and the first computing instruction may be combined to obtain a target computing instruction, and the target computing instruction may be sent to a computing device for computing processing, so that the computing device can perform computing based on the target computing instruction. The instruction performs calculation processing on the data to be processed, and obtains the calculation result.

In an optional implementation manner, the above-mentioned instruction merging unit is further used for:

(1), determine the instruction calculation type of the first calculation instruction and the cached calculation instruction;

(2) In the case that the instruction merge mode of the first calculation instruction and the cached calculation instruction is determined to be the first merge mode based on the instruction calculation type, merge the cached calculation instruction with the first merge mode. The calculation instructions are combined to obtain the target calculation instructions.

In the embodiment of the present disclosure, the process of determining the instruction merging mode of the first computing instruction and the cached computing instruction, and merging the cached computing instruction and the first computing instruction based on the instruction merging mode is as shown in the instruction corresponding to FIG. 1 above. The embodiment corresponding to step S1051 in the processing method is described, and details are not repeated here.

In the embodiment of the present disclosure, the instruction merging mode of the first computing instruction and the cached computing instruction can be determined based on the instruction computing type, so that the present disclosure can be applied to computing instructions of different instruction computing types, and the scope of application of the present disclosure is increased.

In an optional implementation manner, the instruction merging unit is further configured to: determine, based on the instruction calculation type, that the instruction merging mode of the first calculation instruction and the cached calculation instruction is the second merge mode In this case, send a target control instruction to the instruction scheduling unit;

The instruction scheduling unit is configured to, after receiving the target control instruction, send the first calculation instruction and the cached calculation instruction to a computing device for calculation processing within the same instruction sending cycle.

Here, the merging mode indicated by the second merging mode may be parallel merging, that is, the first computing instruction and the cached computing instruction are sent to the computing device in the same instruction issuing cycle. If the calculation instruction is an initialization instruction minit, then the instruction merge mode corresponding to the first calculation instruction and the cached calculation instruction may be the second merge mode.

In an optional implementation manner, the above-mentioned instruction processing apparatus further includes: an instruction scheduling unit;

The instruction scheduling unit is further configured to send the cached computing instruction to a computing device for processing when it is determined that the cached computing instruction and the first computing instruction are found not to satisfy the instruction merging condition. processing, and cache the first computing instruction to the cache space.

In the embodiment of the present disclosure, when the cache space includes a cached calculation instruction, the instruction attribute information of the cached calculation instruction can be obtained to obtain the first information, and the instruction attribute information of the first calculation instruction can be obtained to obtain the first information. 2. Information. Then, it may be determined whether the information matching degree between the first information and the second information satisfies the preset matching degree requirement, and if the preset matching degree requirement is not met, it is determined that the cached calculation instruction and the first calculation instruction do not meet the preset matching degree requirement. The instruction merging condition is satisfied, wherein the process of determining the information matching degree between the first information and the second information is as described in the embodiment corresponding to the foregoing step S105, and details are not repeated here.

After it is determined that the cached computing instruction and the first computing instruction do not meet the instruction merging condition, the following two implementations may be included:

method one:

In the embodiment of the present disclosure, the first calculation instruction is sent to the computing device for processing, and the next acquired calculation instruction is continued to be identified to determine whether the next calculation instruction can be combined with the cached calculation instruction.

Method two:

In the embodiment of the present disclosure, the cached computing instructions may be combined, and the computing instructions obtained after the combined processing are sent to the computing device for processing, and the first computing instructions are cached in the cache space at the same time.

In the embodiment of the present disclosure, when it is determined that the cached computing instruction and the first computing instruction do not meet the instruction merging condition, the cached computing instruction can be sent to the computing device for processing, and the first computing instruction is cached into the cache space, thereby reducing the instruction processing delay caused by waiting for the merging when the computing instructions that can be merged are far apart.

In addition, in the embodiment of the present disclosure, FIG. 3 is a schematic diagram of a chip. As shown in FIG. 3 , the chip includes an instruction distribution device 31, an instruction processing device 32 and a computing device 33, specifically:

an instruction distribution device, configured to distribute the first computing instruction to be executed at the current moment to the instruction processing device;

The instruction processing device is used to obtain the first calculation instruction to be executed at the current moment; when it is determined that the first calculation instruction is the instruction to be merged, the cached calculation instruction is searched in the cache space; Under the condition that the cached computing instruction and the first computing instruction satisfy the instruction merging condition, combine the first computing instruction and the cached computing instruction to obtain a target computing instruction;

A computing device, configured to obtain an operand corresponding to the target computing instruction, and execute the target computing instruction based on the operand.

Here, the instruction processing apparatus includes an instruction receiving unit, an instruction merging unit, and an instruction scheduling unit, and the computing apparatus includes a plurality of computing cores.

In this embodiment of the present disclosure, the processing flow of the instruction distribution apparatus 31, the instruction processing apparatus 32, and the computing apparatus 33 may be the flow described in the following steps S301-S308, wherein:

S301: The instruction distribution apparatus may send the acquired calculation instruction to the instruction processing apparatus for processing.

S302: After determining the received calculation instruction as the first calculation instruction, the instruction receiving unit of the instruction processing apparatus may determine whether the first calculation instruction is the calculation instruction to be combined.

Wherein, if the first calculation instruction is not the calculation instruction to be combined, execute S303, and then jump to execute S308. In the case that the first calculation instruction is the calculation instruction to be combined, then jump to execute S304 to S308.

S303: The instruction receiving unit sends the to-be-combined calculation instruction to the instruction scheduling unit. Wherein, after executing S303, jump to executing S308 until the calculation instruction to be combined is sent to the computing device for processing.

S304: The instruction receiving unit in the instruction processing apparatus sends the instruction to be combined to the instruction combining unit.

After executing S303, execute S305-S308 in sequence until the calculation instruction to be combined is sent to the computing device for processing.

S305: The instruction receiving unit can determine whether the above-mentioned calculation instruction to be merged and the cached calculation instruction in the cache space satisfy the instruction merging condition. Then execute S307.

S306: The instruction receiving unit combines the first calculation instruction and the cached calculation instruction to obtain a target calculation instruction, and sends the target calculation instruction to the instruction transmitter.

S307: The instruction receiving unit stores the to-be-combined calculation instruction into the cache space.

S308: The instruction scheduling unit sends the acquired computing instruction (which may include the first computing instruction and the target computing instruction) to the computing device, so that multiple computing cores in the computing device can perform computing processing based on the acquired computing instruction.

To sum up, in the embodiment of the present disclosure, after it is determined that the acquired first calculation instruction to be executed at the current moment is the calculation instruction to be merged, the cached calculation instruction can be searched in the cache space, and the cached calculation instruction that is found can be searched. When the calculation instruction and the first calculation instruction satisfy the instruction merging condition, the first calculation instruction and the cached calculation instruction are merged, so as to realize the dynamic merge of the calculation instructions, reduce the programming workload of the programmer, and further improve the The programmer's programming efficiency.

Those skilled in the art can understand that in the above method of the specific implementation, the writing order of each step does not mean a strict execution order but constitutes any limitation on the implementation process, and the specific execution order of each step should be based on its function and possible Internal logic is determined.

Based on the same inventive concept, the embodiment of the present disclosure also provides an instruction processing apparatus corresponding to the instruction processing method. Reference may be made to the implementation of the method, and repeated descriptions will not be repeated.

Referring to FIG. 4 , which is a schematic diagram of an instruction processing apparatus provided by an embodiment of the present disclosure, the apparatus includes: an obtaining unit 41 , a determining unit 42 , and a merging unit 43 ; wherein,

an obtaining unit 41, for obtaining the first calculation instruction to be executed at the current moment;

A determination unit 42, configured to search for a cached calculation instruction in the cache space when it is determined that the first calculation instruction is an instruction to be merged;

The merging unit 43 is configured to perform merging processing on the first computing instruction and the cached computing instruction when it is determined that the found cached computing instruction and the first computing instruction satisfy the instruction merging condition .

In the embodiment of the present disclosure, after it is determined that the acquired first calculation instruction to be executed at the current moment is the calculation instruction to be merged, the cached calculation instruction may be searched in the cache space, and the cached calculation instruction and When the first calculation instruction satisfies the instruction merging condition, the first calculation instruction and the cached calculation instruction are merged, so as to realize dynamic merging of the calculation instructions.

For the description of the processing flow of each unit in the apparatus and the interaction flow between the various units, reference may be made to the relevant descriptions in the foregoing method embodiments, which will not be described in detail here.

Corresponding to the instruction processing method in FIG. 1 , an embodiment of the present disclosure further provides a chip 500 . As shown in FIG. 5 , a schematic structural diagram of the chip 500 provided by an embodiment of the present disclosure includes:

The chip 51, the memory 52, and the bus 53; the memory 52 is used to store execution instructions, and the chip 51 and the memory 52 communicate through the bus 53, so that the chip 51 executes the following instructions:

Obtain the first calculation instruction to be executed at the current moment;

When it is determined that the first calculation instruction is an instruction to be merged, look up the cached calculation instruction in the cache space;

When it is determined that the found cached calculation instruction and the first calculation instruction satisfy the instruction merging condition, the first calculation instruction and the cached calculation instruction are merged.

The present disclosure also provides a board, which includes a package structure packaged with at least one of the above-mentioned chips. Referring to FIG. 6 , an exemplary board card is provided. The above board card includes the above chip 500 , and may also include other components, including but not limited to: a storage device 604 and an interface device 606 .

The storage device is connected to the chip in the chip package structure through a bus, and is used for storing data. The storage device may include multiple groups of storage units 608, such as: DDR SDRAM (English: Double Data Rate SDRAM, double-rate synchronous dynamic random access memory) and the like. Each group of the memory cells is connected to the chip through a bus.

The interface device is electrically connected to the chip in the chip package structure. The interface device is used to realize data transmission between the chip and an external device 610 (for example, a terminal, a server, a camera, etc.). In one embodiment, the interface device may include a PCIE interface, and may also be a network interface, or other interfaces, which are not limited in the present disclosure.

Embodiments of the present disclosure further provide a computer-readable storage medium, where a computer program is stored on the computer-readable storage medium, and the computer program executes the steps of the instruction processing method described in the above method embodiments when the computer program is run by the chip. Wherein, the storage medium may be a volatile or non-volatile computer-readable storage medium.

Embodiments of the present disclosure further provide a computer program product, where the computer program product carries program codes, and the instructions included in the program codes can be used to execute the steps of the instruction processing methods described in the foregoing method embodiments. For details, please refer to the foregoing methods. The embodiments are not repeated here.

Wherein, the above-mentioned computer program product can be specifically implemented by means of hardware, software or a combination thereof. In an optional embodiment, the computer program product is embodied as a computer storage medium, and in another optional embodiment, the computer program product is embodied as a software product, such as a software development kit (Software Development Kit, SDK), etc. Wait.

Those skilled in the art can clearly understand that, for the convenience and brevity of description, for the specific working process of the system and device described above, reference may be made to the corresponding process in the foregoing method embodiments, which will not be repeated here. In the several embodiments provided in the present disclosure, it should be understood that the disclosed system and method may be implemented in other manners. The apparatus embodiments described above are only illustrative. For example, the division of the units is only a logical function division. In actual implementation, there may be other division methods. For example, multiple units or components may be combined or Can be integrated into another system, or some features can be ignored, or not implemented. On the other hand, the shown or discussed mutual coupling or direct coupling or communication connection may be through some communication interfaces, indirect coupling or communication connection of devices or units, which may be in electrical, mechanical or other forms.

The units described as separate components may or may not be physically separated, and components displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed to multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution in this embodiment.

In addition, each functional unit in each embodiment of the present disclosure may be integrated into one processing unit, or each unit may exist physically alone, or two or more units may be integrated into one unit.

If the functions are implemented in the form of software functional units and sold or used as independent products, they may be stored in a chip-executable non-volatile computer-readable storage medium. Based on such understanding, the technical solutions of the present disclosure can be embodied in the form of software products in essence, or the parts that contribute to the prior art or the parts of the technical solutions. The computer software products are stored in a storage medium, including Several instructions are used to cause a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in various embodiments of the present disclosure. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (Read-Only Memory, ROM), random access memory (Random Access Memory, RAM), magnetic disk or optical disk and other media that can store program codes.

Finally, it should be noted that the above-mentioned embodiments are only specific implementations of the present disclosure, and are used to illustrate the technical solutions of the present disclosure rather than limit them. The protection scope of the present disclosure is not limited thereto, although referring to the foregoing The embodiments describe the present disclosure in detail. Those of ordinary skill in the art should understand that: any person skilled in the art can still modify the technical solutions described in the foregoing embodiments within the technical scope disclosed by the present disclosure. Changes can be easily thought of, or equivalent replacements are made to some of the technical features; and these modifications, changes or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present disclosure, and should be covered in the present disclosure. within the scope of protection. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims (16)

1. An instruction processing device, characterized in that the instruction processing device comprises: an instruction receiving unit and an instruction merging unit: The instruction receiving unit is used to obtain the first calculation instruction to be executed at the current moment; The instruction merging unit is configured to search for a cached calculation instruction in the cache space when it is determined that the first calculation instruction is an instruction to be merged; and when it is determined that the found cached calculation instruction and all When the first calculation instruction satisfies the instruction merging condition, the first calculation instruction and the cached calculation instruction are merged. 2. The instruction processing apparatus according to claim 1, wherein the instruction merging unit is further configured to: determining an instruction identification of the first calculation instruction, wherein the instruction identification is used to indicate whether the first calculation instruction is an instruction to be merged; When it is determined that the identification content of the instruction identification identifier is the target content, it is determined that the first calculation instruction is the instruction to be combined. 3. The instruction processing apparatus according to claim 1 or 2, wherein the instruction merging unit is further configured to: Whether the cached computing instruction and the first computing instruction satisfy the instruction merging condition is determined based on a preset merging policy; wherein the instruction merging condition is a condition associated with the instruction merging policy. 4. The instruction processing apparatus according to claim 3, wherein the instruction merging unit is further configured to: In the case where the merging strategy is the first strategy, obtain the instruction attribute information of the cached calculation instruction to obtain the first information, and obtain the instruction attribute information of the first calculation instruction to obtain the second information; wherein, The first strategy is used to instruct the merging of computing instructions based on instruction attribute information; determining the degree of information matching between the first information and the second information; In the case that the information matching degree satisfies the preset matching degree requirement, it is determined that the cached computing instruction and the first computing instruction satisfy the instruction merging condition. 5 . The instruction processing apparatus according to claim 4 , wherein the first information includes a plurality of first sub-information, and the second information includes a plurality of second sub-information; the instruction merging unit further comprises: 6 . Used for: respectively determining the sub-matching degree values of the first sub-information and the second sub-information corresponding to the attribute information, to obtain a plurality of sub-matching degree values; determining an information matching degree between the first information and the second information based on the plurality of sub-matching degree values; The attribute information includes: the number of instruction channels, the instruction calculation type, and the instruction data type. 6. The instruction processing apparatus according to claims 3 to 5, wherein the instruction merging unit is further configured to: In the case that the merging strategy is the second strategy, determining the remaining cache space of the cache space; wherein the second strategy is used to instruct the merging of computing instructions based on the size of the remaining space in the cache space; In a case where it is determined that the remaining cache space does not meet the cache requirement of the first computing instruction, it is determined that the cached computing instruction and the first computing instruction satisfy an instruction merging condition. 7. The instruction processing apparatus according to any one of claims 3 to 6, wherein the instruction merging unit is further configured to: In the case that the merging strategy is a third strategy, obtain the instruction quantity of the cached computing instructions in the cache space; wherein the third strategy is used to instruct the merging of computing instructions based on a preset number of instructions; When it is determined that the instruction quantity meets the instruction quantity requirement, it is determined that the cached computation instruction and the first computation instruction satisfy an instruction merging condition. 8. The instruction processing apparatus according to any one of claims 1 to 7, wherein the instruction processing apparatus further comprises: an instruction scheduling unit; the instruction merging unit, configured to merge the cached computing instruction and the first computing instruction to obtain a target computing instruction; The instruction scheduling unit is configured to receive the target computing instruction sent by the instruction merging unit, and send the target computing instruction to a computing device for computing processing. 9. The instruction processing apparatus according to claim 8, wherein the instruction merging unit is further configured to: determining the instruction computation type of the first computation instruction and/or the cached computation instruction; If it is determined based on the instruction calculation type that the instruction merge mode of the first calculation instruction and the cached calculation instruction is the first merge mode, the cached calculation instruction and the first calculation instruction are merged to obtain the target calculation instruction. 10. The instruction processing apparatus according to claim 9, characterized in that: The instruction merging unit is further configured to: in the case that the instruction merging mode of the first computing instruction and the cached computing instruction is determined to be the second merging mode based on the instruction calculation type, send the instruction to the instruction scheduling unit Send target control instructions; The instruction scheduling unit is configured to, after receiving the target control instruction, send the first calculation instruction and the cached calculation instruction to a computing device for calculation processing within the same instruction sending cycle. 11. The instruction processing apparatus according to any one of claims 1 to 10, wherein the instruction processing apparatus further comprises: an instruction scheduling unit; The instruction scheduling unit is further configured to send the cached computing instruction to a computing device for processing when it is determined that the cached computing instruction and the first computing instruction are found not to satisfy the instruction merging condition. processing, and cache the first computing instruction to the cache space. 12. An instruction processing method, comprising: Obtain the first calculation instruction to be executed at the current moment; When it is determined that the first calculation instruction is an instruction to be merged, look up the cached calculation instruction in the cache space; When it is determined that the found cached calculation instruction and the first calculation instruction satisfy the instruction merging condition, the first calculation instruction and the cached calculation instruction are merged. 13. A chip, comprising: an instruction distribution device, an instruction processing device, and a computing device; the instruction distribution device, configured to distribute the first computing instruction to be executed at the current moment to the instruction processing device; The instruction processing device is used to obtain the first calculation instruction to be executed at the current moment; when it is determined that the first calculation instruction is an instruction to be merged, the cached calculation instruction is searched in the cache space; Under the condition that the received cached computing instruction and the first computing instruction satisfy the instruction merging condition, combine the first computing instruction and the cached computing instruction to obtain a target computing instruction; The computing device is configured to obtain operands for executing the target computing instruction, and execute the target computing instruction based on the operands. 14. A board, comprising: a package structure encapsulating at least one chip according to claim 13. 15 . A computer device, characterized in that it comprises the instruction processing device according to any one of claims 1 to 11 , or the chip according to claim 13 , or the board according to claim 14 . 16. A computer-readable storage medium, wherein a computer program is stored on the computer-readable storage medium, and the computer program executes the steps of the instruction processing method according to claim 12 when the computer program is run by a processor.

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