CN115002383B

CN115002383B - SDI video signal processing system and method and signal isolation system

Info

Publication number: CN115002383B
Application number: CN202210939433.8A
Authority: CN
Inventors: 邬东升; 谭文安; 梁江荣; 伍思樾; 李明; 任均宇; 吴春波
Original assignee: Guangdong Optomedic Technology Co Ltd
Current assignee: Guangdong Oupu Mandi Technology Co ltd
Priority date: 2022-08-05
Filing date: 2022-08-05
Publication date: 2022-10-28
Anticipated expiration: 2042-08-05
Also published as: CN115002383A

Abstract

The application provides a SDI video signal processing system, a method and a signal isolation system, which relate to the technical field of video data processing and comprise the following steps: the selecto module receives the LVDS signals and the LVDS time sequence, converts the LVDS signals into parallel signals and converts the LVDS time sequence into a working clock; the decoding module is used for decoding the parallel signals to obtain YC signals, SAV signals, EAV signals and LN signals; the identification module acquires a video format according to the YC signal and the working clock; the synchronous module generates a DE signal, an Hblank signal and a Vblank signal according to the SAV signal, the EAV signal and the LN signal, and generates a VS signal and an HS signal according to a video format; and the video processing module receives the YC signal, the DE signal, the Hblank signal, the Vblank signal, the VS signal and the HS signal for video processing. Has the advantage of reducing the use of hardware products.

Description

SDI video signal processing system and method and signal isolation system

Technical Field

The application relates to the technical field of video data processing, in particular to a SDI video signal processing system and method and a signal isolation system.

Background

The anti-interference items comprise static interference, pulse group interference, surge and other test items which are difficult to pass. Interference signals generated when the camera carries out EMC test are usually directly transmitted to a camera host through a cable, and the interference signals can cause the host to be black and flash; to solve this, all signals of the camera are usually isolated.

The SDI video signal with higher speed in the camera usually needs to be converted into LVDS parallel signal with lower speed to be transmitted in the isolation chip, after the SDI video signal passes through the digital isolation chip, the current conventional method is to convert the LVDS signal output by the isolation chip into the SDI video signal by using a parallel-serial conversion chip, and the SDI video signal is converted into YCbCr422 format by a conversion chip such as ADV7601 and then transmitted to a later FPGA for processing. The prior art has the disadvantages of high hardware cost and complex circuit structure.

In view of the above problems, improvements are needed.

Disclosure of Invention

The invention aims to provide an SDI video signal processing system, an SDI video signal processing method and a signal isolation system, which have the advantages of reducing the use of hardware products, reducing the cost and simplifying the circuit structure.

In a first aspect, the present application provides an SDI video signal processing system, which has the following technical scheme:

the method comprises the following steps:

the selecto module is used for receiving the LVDS signals and the LVDS time sequence after the SDI video signals are subjected to signal isolation, converting the LVDS signals into parallel signals and converting the LVDS time sequence into a working clock;

the decoding module is used for decoding the parallel signals to obtain YC signals, SAV signals, EAV signals and LN signals;

the identification module is used for acquiring video format information contained in the SDI video signal according to the YC signal and the working clock;

the synchronization module correspondingly generates a DE signal, an Hblank signal and a Vblank signal according to the SAV signal, the EAV signal and the LN signal, and generates a VS signal and an HS signal according to the video format information;

and the video processing module is used for receiving the YC signal, the DE signal, the Hblank signal, the Vblank signal, the VS signal and the HS signal respectively so as to perform video processing.

The LVDS after signal isolation is converted into parallel signals by using a selecto module, the parallel signals are directly decoded by a decoding module to obtain YC signals, SAV signals, EAV signals and LN signals, video format information is obtained by an identification module according to the YC signals and a working clock, DE signals, hblank signals and Vblank signals are correspondingly generated by a synchronization module according to the SAV signals, the EAV signals and the LN signals, VS signals and HS signals are generated according to the video format information, and finally the YC signals, the DE signals, the Hblank signals, the Vblank signals, the VS signals and the HS signals are input into a video processing module for video processing.

Further, in the present application, the selecto module includes:

the first buffer unit receives the LVDS signals;

the second buffer unit receives the LVDS timing sequence and converts the LVDS timing sequence into a single-ended signal;

the third buffer unit is used for carrying out frequency division on the LVDS time sequence converted into the single-ended signal to obtain the working clock;

and the parallel unit is used for receiving the working clock and converting the LVDS signals into the parallel signals according to a preset proportion.

Further, in the present application, the selecto module further includes:

the delay unit is used for receiving the working clock and delaying the LVDS signals;

and the control unit receives the reference data and the working clock and controls the delay unit to delay the LVDS signals according to the reference data.

Further, in the present application, the identification module includes:

the frequency identification unit receives the working clock and an additional input sequence with known frequency so as to identify the clock frequency of the working clock;

a first detection unit that detects and identifies a Y signal or a C signal in the YC signals;

a counting unit, extracting two consecutive SAV signals or two consecutive EAV signals in the Y signal or the C signal in the first detection unit, and calculating to obtain a video width of a line and a clock number between the SAV signal and the EAV signal;

and the comparison unit is used for obtaining the video format information according to the clock frequency of the working clock, the video width of the line and the clock number between the SAV signal and the EAV signal, wherein the video format information at least comprises a frame rate and a resolution ratio.

Further, in the present application, the synchronization module includes:

a generating unit for receiving the SAV signal, the EAV signal and the LN signal to correspondingly generate a DE signal, an Hblank signal and a Vblank signal, and receiving the video format information to generate a VS signal and an HS signal;

and the second detection unit is used for detecting and identifying a Y signal and a C signal in the YC signal and sending the SAV signal, the EAV signal and the LN signal in the Y signal or the C signal to the generation unit.

In a second aspect, the present application further provides a method for processing an SDI video signal, including:

receiving an LVDS (low voltage differential signaling) signal and an LVDS time sequence of an SDI (Serial digital interface) video signal after signal isolation, converting the LVDS signal into a parallel signal, and converting the LVDS time sequence into a working clock;

decoding the parallel signals to obtain YC signals, SAV signals, EAV signals and LN signals;

acquiring video format information contained in the SDI video signal according to the YC signal and the working clock;

correspondingly generating a DE signal, an Hblank signal and a Vblank signal according to the SAV signal, the EAV signal and the LN signal, and generating a VS signal and an HS signal according to the video format information;

the YC signal, DE signal, hblank signal, vblank signal, VS signal, and HS signal are received for video processing, respectively.

Further, in this application, the step of receiving the LVDS signal of the SDI video signal after signal isolation and the LVDS timing, converting the LVDS signal into a parallel signal, and converting the LVDS timing into the working clock includes:

receiving the LVDS signals;

receiving the LVDS time sequence and converting the LVDS time sequence into a single-ended signal;

carrying out frequency division on the LVDS time sequence converted into a single-ended signal to obtain the working clock;

and receiving the working clock and converting the LVDS signals into the parallel signals according to a preset proportion.

Further, in the present application, the method further includes:

receiving the working clock and delaying the LVDS signals;

and receiving reference data and the working clock, and delaying the LVDS signals according to the reference data.

Further, in the present application, the step of acquiring video format information included in the SDI video signal according to the YC signal and the operating clock includes:

receiving the operating clock and an additional input timing of known frequency to identify a clock frequency of the operating clock;

detecting and identifying a Y signal or a C signal in the YC signals;

extracting two continuous SAV signals or two continuous EAV signals in the Y signal or the C signal, and calculating to obtain the video width of one line and the clock number between the SAV signal and the EAV signal;

and obtaining the video format information according to the clock frequency of the working clock, the video width of the line and the clock number between the SAV signal and the EAV signal, wherein the video format information at least comprises a frame rate and a resolution.

In a third aspect, the present application further provides a signal isolation system, including:

the serial-parallel conversion module receives an SDI video signal and converts the SDI video signal into a plurality of paths of first LVDS signals;

the digital isolation module receives a plurality of channels of the first LVDS signals and correspondingly generates a plurality of channels of the second LVDS signals and corresponding second LVDS time sequences;

the selecto module is used for receiving the second LVDS signals and the corresponding second LVDS time sequence, converting the second LVDS signals into parallel signals and converting the second LVDS time sequence into a working clock;

As can be seen from the above, according to the SDI video signal processing system, the SDI video signal processing method and the signal isolation system provided by the present application, the selectio module is used to convert the LVDS signal subjected to signal isolation into the parallel signal, the decoding module directly decodes the parallel signal to obtain the YC signal, the SAV signal, the EAV signal and the LN signal, the identification module obtains the video format information according to the YC signal and the operating clock, the synchronization module correspondingly generates the DE signal, the Hblank signal and the Vblank signal according to the SAV signal, the synchronization module generates the VS signal and the HS signal according to the video format information, and finally inputs the YC signal, the DE signal, the Hblank signal, the Vblank signal, the VS signal and the HS signal to the video processing module for video processing, so that the use of the string conversion chip, the ADV conversion chip and other conversion chips can be reduced by the scheme of the present application, thereby avoiding the need of converting the isolated LVDS signal into the SDI video signal, and reducing the use of hardware products, and simplifying the cost of the LVDS circuit structure.

Drawings

Fig. 1 is a schematic structural diagram of an SDI video signal processing system according to the present application.

Fig. 2 is a schematic structural diagram of a selecto module provided in the present application.

Fig. 3 is a schematic structural diagram of an identification module provided in the present application.

Fig. 4 is a schematic structural diagram of a synchronization module provided in the present application.

Fig. 5 is a flowchart of an SDI video signal processing method provided in the present application.

Fig. 6 is a schematic structural diagram of a signal isolation system provided in the present application.

Fig. 7 is a schematic diagram of a signal isolation system in the conventional prior art.

In the figure: 100. a selecto module; 200. a decoding module; 300. an identification module; 400. a synchronization module; 500. a video processing module; 600. a serial-to-parallel conversion module; 700. a digital isolation module; 110. a first buffer unit; 120. a second buffer unit; 130. a third buffer unit; 140. a parallel unit; 150. a delay unit; 160. a control unit; 310. a frequency identification unit; 320. a first detection unit; 330. a counting unit; 340. a comparison unit; 410. a second detection unit; 420. and a generating unit.

Detailed Description

The technical solutions in the present application will be described clearly and completely with reference to the drawings in the present application, and it should be understood that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. The components of the present application, as generally described and illustrated in the figures herein, may be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present application, presented in the accompanying drawings, is not intended to limit the scope of the claimed application, but is merely representative of selected embodiments of the application. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the present application without making any creative effort, shall fall within the protection scope of the present application.

It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures. Meanwhile, in the description of the present application, the terms "first", "second", and the like are used only for distinguishing the description, and are not to be construed as indicating or implying relative importance.

In the field of video data transmission, an SDI video signal is a high-speed video signal, generally speaking, parallel-to-serial conversion is not required for processing the SDI video signal, and a high-speed SDI video signal can be directly received by a corresponding hardware device, however, in the field of medical instruments, particularly for surgical devices, a strict anti-interference test is required to reduce interference between the devices, and simultaneously, current generated accidentally is prevented from flowing to a user, which is directly related to the safety of surgery, for this reason, in order to improve the anti-interference performance of the medical devices, digital isolation is required to be performed on the SDI video signal, while the SDI video signal belongs to a high-speed video signal, a general digital isolation chip cannot perform digital isolation on the high-speed SDI video signal, and therefore, as shown in fig. 7 in the prior art, a high-speed SDI video signal needs to be converted into a multi-path LVDS signal with a lower speed by a serial-to-parallel conversion module 600, then the multi-path LVDS signal is input into a digital isolation module 700 for digital isolation, after the digital isolation, the multi-path LVDS signal is generated from the digital isolation module 700, and then the multi-path of the SDI video signal is recovered by an FPGA 7601 string-to a multi-path conversion, and the conventional scheme needs to be converted into a multi-path video signal processing scheme, and then the multi-path of an adc video signal processing method, which is recovered by a multi-path of a multi-path adc, and then, and a multi-path adc, which is recovered video signal processing method.

To this end, referring to fig. 1, the present application provides an SDI video signal processing system, which is developed based on an FPGA, and the selectio module 100, the decoding module 200, the identification module 300, and the synchronization module 400 are programmed on the PFGA to replace a parallel-to-serial conversion chip and an ADV7601 chip in the existing scheme, so as to achieve the purpose of simplifying a circuit structure and reducing hardware cost, and the technical scheme specifically includes:

the selectio module 100 receives the LVDS signal of the SDI video signal after signal isolation and the LVDS timing, converts the LVDS signal into a parallel signal, and converts the LVDS timing into a working clock;

the LVDS timing refers to a clock signal of the LVDS;

a decoding module 200 for decoding the parallel signal to obtain a YC signal, an SAV signal, an EAV signal, and an LN signal;

the decoding module 200 is mainly used to find out the video-related signal from the parallel signals;

the identification module 300 is used for acquiring video format information contained in the SDI video signal according to the YC signal and the working clock;

a synchronization module 400, which generates a DE signal, an Hblank signal, and a Vblank signal according to the SAV signal, the EAV signal, and the LN signal, and generates a VS signal and an HS signal according to the video format information;

the video processing module 500 receives the YC signal, the DE signal, the Hblank signal, the Vblank signal, the VS signal, and the HS signal, respectively, to perform video processing.

The selecto module 100 described above refers to a module including an I/O interface and I/O logic;

the LVDS signal refers to a Low-Voltage Differential Signaling (Low-Voltage Differential Signaling);

the YCbCr422 format signals refer to three signals of a YCbCr color space, namely, Y, cb, cr, and the YC signals are abbreviated as YCbCr422 format signals;

the SAV signal refers to a start of active video signal (start of active video);

the EAV signal refers to an end of active video signal (end of active video);

SDI video signal refers to a Serial Digital Interface video signal (Serial Digital Interface);

the LN signal contains LN0 and LN1 and is the code of the line number in a frame of video;

the DE signal refers to a data valid signal;

the Hblank signal refers to a horizontal blanking signal;

the Vblank signal refers to a vertical blanking signal;

the VS signal refers to a vertical synchronization signal;

the HS signal refers to a horizontal synchronization signal.

Through the technical scheme, the LVDS signals subjected to signal isolation are converted into parallel signals by the selectio module 100, the parallel signals are directly decoded by the decoding module 200 to obtain YC signals, SAV signals, EAV signals and LN signals, the video format information is obtained by the identification module 300 according to the YC signals and the working clock, DE signals, hblank signals and Vblank signals are correspondingly generated by the synchronization module 400 according to the SAV signals, EAV signals and LN signals, VS signals and HS signals are generated according to the video format information, and finally the YC signals, the DE signals, the Hblank signals, the Vblank signals, the VS signals and the HS signals are input into the video processing module 500 for video processing.

Further, referring to fig. 2, in some embodiments, the selecto module 100 includes:

a first buffer unit 110 receiving LVDS signals;

a second buffer unit 120, receiving the LVDS timing and converting the LVDS timing into a single-ended signal;

a third buffer unit 130, which divides the LVDS timing converted into the single-ended signal to obtain a working clock;

the first Buffer unit 110 and the second Buffer unit 120 may both be IBUFDS, that is, a Dedicated Differential Signaling Input Buffer with Selectable I/O Interface (Dedicated Differential Signaling Input Buffer I/O Interface), and the first Buffer unit 110 receives LVDS signals and converts them into single-ended signals;

the third buffer unit 130 may be a BUFGCE _ DIV, i.e., a clock buffer, and the clock buffer has a frequency division function;

during the process of converting the SDI video signal into the LVDS signal, the LVDS signal contains some codes originally added to the SDI video signal to ensure transmission reliability, and normal data in the SDI video signal can be identified only by decoding, so that an LVDS time sequence needs to be converted into a working clock;

in addition, because the LVDS signals subjected to signal isolation are processed, the original SDI video signals are high in speed and cannot be effectively isolated, a single-channel SDI video signal needs to be converted into multiple channels of LVDS signals, the upper edge and the lower edge of each LVDS clock signal both contain data, and the working principle of the FPGA determines that the clock signal cannot process the data of the upper edge and the lower edge at the same time, so that the multiple channels of LVDS signals need to be converted into a single-ended signal, specifically, a 5-bit LVDS signal can be converted into a 20-bit video signal single-ended signal, and at this time, a 2-frequency division can be performed on the originally input LVDS timing sequence to obtain a working clock;

for example, if the clock frequency of the LVDS clock signal is 100M, the LVDS signal rate in this embodiment is 100m × 2 × 5=1000m, and according to this rate, the corresponding operating clock frequency is 1000M/20=50m by converting into the parallel signal of 20 bits, that is, two-division frequency;

the parallel unit 140 receives the operating clock and converts the LVDS signal into a parallel signal according to a preset ratio.

Among them, the parallel unit 140 may be ISERDES3, i.e., an input serializer/deserializer;

through the above technical solution, the parallel unit 140 converts the LVDS signals into the parallel signals according to the preset ratio according to the working clock, so that the decoding module 200 can decode the LVDS signals, because the speed of the LVDS signals is still higher for the PFGA, and a general FPGA cannot process the LVDS signals, the LVDS signals need to be converted into the parallel signals, and after the conversion, the parallel signals corresponding to each working clock include data of one pixel, while before the conversion, the LVDS signals corresponding to the clocks of the LVDS clocks include data of one pixel, so that the LVDS signals can be processed conveniently after being converted into the parallel signals, and the LVDS signals can be compatible with a general video standard after being converted into the parallel signals.

Further, in some embodiments, the selecto module 100 further comprises:

a delay unit 150 for receiving the working clock and delaying the LVDS signal;

the control unit 160 receives the reference data and the operation clock, and controls the delay unit 150 to delay the LVDS signal according to the reference data.

The delay unit 150 may be ideelaye 3, i.e., an input delay.

Through the above technical solution, the control unit 160 is utilized to receive the reference data, and the delay unit 150 is controlled to delay the LVDS signal according to the reference data and the working clock, so as to find the center position of the eye diagram and determine the delay time.

Specifically, the reference data may be data prepared in advance, the reference data is delayed by the delay unit 150 to find the center position of the eye pattern, and determine the delay time corresponding to the center position of the eye pattern, and then the LVDS signal is delayed by the delay time to ensure the sampling quality.

The delayed LVDS signals are transmitted to the parallel unit 140, and the parallel unit 140 converts the LVDS signals into parallel signals according to a preset ratio by a working clock.

Further, referring to fig. 3, in some embodiments, the identification module 300 comprises:

a frequency identification unit 310 for receiving the working clock and an additional input sequence with known frequency to identify the clock frequency of the working clock;

a first detection unit 320 detecting and recognizing a Y signal or a C signal among the YC signals;

a counting unit 330 for extracting two consecutive SAV signals or two consecutive EAV signals from the Y signal or the C signal in the first detecting unit 320, and calculating a video width of one line and a clock number between the SAV signal and the EAV signal;

the comparing unit 340 obtains video format information according to the clock frequency of the operating clock, the video width of one line, and the clock number between the SAV signal and the EAV signal, where the video format information at least includes a frame rate and a resolution.

By the above technical solution, the frequency identifying unit 310 receives two time sequences, one is an operating clock, and the other is an additional input time sequence, wherein the clock frequency of the additional input time sequence is known, and the clock frequency of the operating clock is obtained by comparing the additional input time sequence with the operating clock, the first detecting unit 320 identifies the Y signal and the C signal in the YC signal, because the Y signal and the C signal both include the SAV signal, the EAV signal and the LN signal, so that the SAV signal, the EAV signal and the LN signal can be extracted only by any one pixel number in the Y signal and the C signal, after the Y signal and the C signal are identified, two consecutive SAV signals or two consecutive EAV signals in the Y signal or the C signal are extracted by the counting unit 330, in order to count the number of clocks between the two consecutive signals, so that the video width of one line, the effective clock number of one line of video can be obtained according to the clock number between the SAV signal and the EAV signal, and the effective clock number of one line of video width of the video lines can be obtained by comparing the effective clock number 340 and the video frequency of the last line according to the video format.

For example, recognizing that the clock frequency of the operating clock is 148.5MHZ, the video width of one line is 2640, and the number of effective pixels is 1920, the video format is 1080p @50hz;

specifically, there are 7 types of videos having a width of 2640, 2048x1080@100Hz, 2048x1080@50Hz,2048x1080@25Hz,1920x1440@75Hz,1920x1080@100Hz,1920x1080@50Hz, and 1920x1080@25Hz. Wherein the working frequency is 148.5MHZ, 2048x1080@50Hz, 1920x1080@50Hz; 2048x1080@50hz and 1920x1080@50Hz can be distinguished by calculating the clock number between the SAV signal and the EAV signal.

Similarly, for example, if the clock frequency of the operating clock is 148.35MHZ, the video width of one line is 2200, and the effective pixel number is 1920, the video format is 1080p@59.94HZ.

Further, referring to fig. 4, in some embodiments, the synchronization module 400 includes:

generating section 420 for receiving the SAV signal, EAV signal, and LN signal, generating the DE signal, hblank signal, and Vblank signal, and receiving the video format information, generating the VS signal and HS signal;

the second detecting unit 410 detects and identifies a Y signal and a C signal in the YC signal, and transmits an SAV signal, an EAV signal, and an LN signal in the Y signal or the C signal to the generating unit 420.

According to the above technical solution, since the YC signal includes the Y signal and the C signal, and both of the Y signal and the C signal include the SAV signal, the EAV signal, and the LN signal, the second detecting unit 410 is used to identify and select one of the Y signal and the C signal, and send the corresponding SAV signal, EAV signal, and LN signal to the generating unit 420, the generating unit 420 generates the DE signal, hblank signal, and Vblank signal according to the SAV signal, EAV signal, and LN signal, generates the VS signal and HS signal according to the video format information, and finally sends the YC signal and the generated DE signal, hblank signal, vblank signal, VS signal, and HS signal to the video processing module 500, and the video processing module 500 performs video processing.

In a second aspect, referring to fig. 5, the present application further provides an SDI video signal processing method, including:

s110, receiving an LVDS signal and an LVDS time sequence of the SDI video signal after signal isolation, converting the LVDS signal into a parallel signal, and converting the LVDS time sequence into a working clock;

s120, decoding the parallel signals to obtain YC signals, SAV signals, EAV signals and LN signals;

s130, acquiring video format information contained in the SDI video signal according to the YC signal and the working clock;

s140, correspondingly generating a DE signal, an Hblank signal and a Vblank signal according to the SAV signal, the EAV signal and the LN signal, and generating a VS signal and an HS signal according to the video format information;

and S150, respectively receiving the YC signal, the DE signal, the Hblank signal, the Vblank signal, the VS signal and the HS signal for video processing.

Through the technical scheme, the LVDS signals subjected to signal isolation are converted into parallel signals, then the parallel signals are directly decoded to obtain YC signals, SAV signals, EAV signals and LN signals, video format information is obtained according to the YC signals and the working clock, DE signals, hblank signals and Vblank signals are correspondingly generated according to the SAV signals, EAV signals and LN signals, VS signals and HS signals are generated according to the video format information, and finally video processing is carried out according to the YC signals, DE signals, hblank signals, vblank signals, VS signals and HS signals.

Further, in some embodiments, the receiving the SDI video signal after signal isolation and the LVDS timing, and converting the LVDS signal into a parallel signal, and the step of converting the LVDS timing into the working clock includes:

receiving an LVDS signal;

receiving an LVDS time sequence and converting the LVDS time sequence into a single-ended signal;

carrying out frequency division on the LVDS time sequence converted into the single-ended signal to obtain a working clock;

and receiving the working clock and converting the LVDS signals into parallel signals according to a preset proportion.

Through the technical scheme, the LVDS signals are converted into parallel signals according to the preset proportion according to the working clock so as to be decoded.

Further, in some of the embodiments, the method further comprises:

receiving a working clock and delaying the LVDS signals;

and receiving the reference data and the working clock, and delaying the LVDS signals according to the reference data.

Through the technical scheme, the LVDS signals are delayed according to the reference data and the working clock by receiving the reference data, and the method and the device aim at finding the center position of the eye pattern and determining the delayed time.

Specifically, the reference data may be data prepared in advance, the center position of the eye pattern is found by delaying the reference data, a delay time corresponding to the center position of the eye pattern is determined, and then the LVDS signal is delayed by the delay time to ensure the sampling quality.

Further, in some embodiments, the step of acquiring the video format information contained in the SDI video signal according to the YC signal and the operating clock comprises:

receiving a working clock and an additional input time sequence with known frequency so as to identify the clock frequency of the working clock;

detecting and identifying a Y signal or a C signal in the YC signal;

and obtaining video format information according to the clock frequency of the working clock, the video width of one line and the clock number between the SAV signal and the EAV signal, wherein the video format information at least comprises a frame rate and a resolution ratio.

According to the technical scheme, two time sequences are received, one time sequence is an operating clock, the other time sequence is an additional input time sequence, the clock frequency of the additional input time sequence is known, the clock frequency of the operating clock is obtained by comparing the additional input time sequence with the known frequency with the operating clock, the Y signal and the C signal in the YC signal are identified, because the Y signal and the C signal comprise the SAV signal, the EAV signal and the LN signal, the SAV signal, the EAV signal and the LN signal can be extracted only through any one of the Y signal and the C signal, after the Y signal and the C signal are identified, two consecutive SAV signals or two consecutive EAV signals in the Y signal or the C signal are extracted, the purpose is to calculate the clock number between the two consecutive signals, and therefore the video format information of one line can be obtained finally according to the clock frequency of the operating clock and the video format information of one line.

For example, recognizing that the clock frequency of the operating clock is 148.5MHZ and the video width of one line is 2640, the video format is 1080p @50hz.

For example, identifying that the clock frequency of the operating clock is 148.35MHZ and the video width of one row is 2200, a video format of 1080p@59.94HZ can be obtained.

In a third aspect, referring to fig. 6, the present application further provides a signal isolation system, including:

the serial-to-parallel conversion module 600 receives the SDI video signal and converts the SDI video signal into a plurality of paths of first LVDS signals;

the digital isolation module 700 receives the multiple first LVDS signals and generates multiple second LVDS signals and corresponding second LVDS timing sequences;

the selectio module 100 receives the second LVDS signal and the corresponding second LVDS timing, converts the second LVDS signal into a parallel signal, and converts the second LVDS timing into a working clock;

a decoding module 200, which decodes the parallel signal to obtain a YC signal, an SAV signal, an EAV signal, and an LN signal;

Specifically, in some embodiments, a high-speed SDI video signal is sent to the serial-to-parallel conversion module 600, the serial-to-parallel conversion module 600 converts the high-speed SDI video signal into 5 channels of first LVDS signals and outputs a corresponding first LVDS timing sequence, the 5 channels of first LVDS signals and the first LVDS timing sequence are input to the digital isolation module 700, and after being isolated by the digital isolation module 700, corresponding second LVDS signals and a second LVDS timing sequence are generated and input to the selectio module 100 constructed based on the PPGA;

the second buffering unit 120 in the selectio module 100 receives the second LVDS timing and converts the second LVDS timing into a single-ended signal, and the third buffering unit 130 divides the frequency of the second LVDS timing converted into the single-ended signal to obtain a working clock;

the first buffer unit 110 in the selectio module 100 receives five paths of second LVDS signals and sends the second LVDS signals to the delay unit, the control unit 160 performs delay by receiving reference data prepared in advance to find a corresponding delay time when the second LVDS signal is located at the center of an eye diagram, then performs picosecond-level delay on the second LVDS signal by the delay time, and sends the delayed second LVDS signal to the parallel unit 140, and the parallel unit 140 may convert the delayed second LVDS signal according to a preset ratio, specifically, 1: the second LVDS signals are converted and output at a ratio of 4, and at this time, the 5-path second LVDS signals are converted into 20-path parallel signals.

The 20 paths of parallel signals are input into a decoding module 200 for decoding, the decoding module 200 decodes the 20 paths of parallel signals, and after decoding, the 20 paths of parallel signals comprise 10bit Y signals and 10bit C signals, wherein the Y signals refer to data of a Y channel, the C signals refer to data of a C channel, and the data of the two channels simultaneously comprise SAV signals, EAV signals, LN signals and the like;

since the data of two channels simultaneously include the SAV signal, EAV signal, LN signal, and the like, in the present application, the data of one channel is used to extract the video identification signals such as SAV (FF 0000 XYZ), EAV (FF 0000 XYZ), LN, and the like;

wherein, FF0000 XYZ is the code in the channel, SAV signal/EAV signal is extracted according to the different XYZ code correspondences.

Therefore, the recognition module 300 includes the first detection unit 320, the first detection unit 320 can detect the Y signal, and after detecting that the Y signal is detected, the corresponding two consecutive SAV signals or two consecutive EAV signals are sent to the counting unit 330, and the counting unit 330 calculates the number of clocks according to the two consecutive signals to obtain the video width of one line;

a frequency identification unit 310 in the identification module 300, configured to receive the working clock and an additional input timing with a known frequency to identify a clock frequency of the working clock, and obtain the clock frequency of the working clock through comparison;

then the comparing unit 340 obtains the video format information according to the clock frequency of the working clock and the video width of one line;

after obtaining the video format information, sending the video format information to a generating unit 420 of the synchronization module 400 to obtain a VS signal and an HS signal, wherein the synchronization module 400 further includes a second detecting unit 410, the second detecting unit 410 can be used to detect the Y signal, and after identifying the Y signal, sending an SAV signal, an EAV signal, and an LN signal in the Y signal to the generating unit 420, and the generating unit 420 correspondingly generates and outputs a DE signal, an Hblank signal, and a Vblank signal, so that the VS signal, the HS signal, the DE signal, the Hblank signal, and the Vblank signal are output from the synchronization module 400 together;

the VS signal, the HS signal, the DE signal, the Hblank signal, and the Vblank signal output from the synchronization block 400 are finally input to the video processing block 500 for video processing.

In summary, the present application is developed based on an FPGA chip, and a selectio module 100, a decoding module 200, an identification module 300, and a synchronization module 400 are set by programming on a PFGA to replace a parallel-to-serial conversion chip and an ADV7601 chip in the existing scheme, so as to achieve the purposes of simplifying a circuit structure and reducing hardware cost.

The above description is only an example of the present application and is not intended to limit the scope of the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. An SDI video signal processing system comprising:

2. The SDI video signal processing system of claim 1 wherein the selecto module comprises:

the first buffer unit receives the LVDS signals;

the second buffer unit receives the LVDS time sequence and converts the LVDS time sequence into a single-ended signal;

3. The SDI video signal processing system of claim 2 wherein the selecto module further comprises:

4. The SDI video signal processing system of claim 1 wherein the identification module comprises:

5. The SDI video signal processing system of claim 1 wherein the synchronization module comprises:

6. An SDI video signal processing method comprising:

7. The SDI video signal processing method of claim 6 wherein the step of receiving the SDI video signal with the LVDS signal subjected to signal isolation and the LVDS timing, converting the LVDS signal into a parallel signal, and converting the LVDS timing into the operating clock comprises:

receiving the LVDS signals;

the LVDS time sequence converted into the single-ended signal is subjected to frequency division to obtain the working clock;

8. The SDI video signal processing method of claim 7 further comprising:

receiving the working clock and delaying the LVDS signals;

9. The SDI video signal processing method of claim 6 wherein the step of obtaining video format information contained in the SDI video signal from the YC signal and the operation clock comprises:

detecting and identifying a Y signal or a C signal in the YC signals;

and obtaining the video format information according to the clock frequency of the working clock, the video width of the line and the clock number between the SAV signal and the EAV signal, wherein the video format information at least comprises a frame rate and a resolution ratio.

10. A signal isolation system, comprising:

the digital isolation module receives a plurality of channels of first LVDS signals and correspondingly generates a plurality of channels of second LVDS signals and corresponding second LVDS time sequences;