CN114999396B - Display panel, driving method thereof and display device - Google Patents

Abstract

The application discloses a display panel, which comprises pixels and a driving circuit for driving the pixels; the driving circuit comprises a driving transistor, and the grid electrode of the driving transistor is a first node; the scanning lines and the data lines are arranged in a crossing manner; the scanning line and the data line are both connected with the driving circuit; the first parasitic capacitance is included between the data line and the first node; the anti-flicker module is used for providing a coupling signal for the data line in a holding stage in a first display mode; the first display mode includes a refresh phase and the hold phase between adjacent refresh phases. The application can reduce leakage current and prevent the display panel from flashing under low-frequency driving.

Description

Display panel, driving method thereof and display device

The application provides a divisional application with the name of a display panel, a driving method thereof and a display device, wherein the application is 28 days of the year 2020 and the application number 202010887320.9.

Technical Field

The present disclosure relates generally to the field of display technologies, and in particular, to a display panel and a driving method thereof.

Background

With the development of display technology, wearable devices increasingly employ Organic Light Emitting (OLED) display panels. Wearable devices, such as watches, do not have high demands on the display effect, but have a need for low power consumption. However, the organic light emitting display panel is driven by a current, and the driving current of the pixel driving circuit generating the driving circuit is determined by the voltage difference between the source and the gate of the driving transistor. The source of the driving transistor receives the power supply voltage, and the gate of the driving transistor receives the data signal voltage and stores the data signal voltage in the storage capacitor. The channel leakage current and the film leakage current cause the voltage change of the data signal stored in the grid electrode of the driving transistor, so that the brightness jump is caused, and the flicker phenomenon occurs.

Disclosure of Invention

In view of the foregoing drawbacks and shortcomings of the prior art, it is desirable to provide a display panel and a display device, so as to solve the technical problems in the prior art.

In one aspect, the application discloses a display panel, a pixel, and a driving circuit for driving the pixel; the driving circuit comprises a driving transistor, and the grid electrode of the driving transistor is a first node;

The scanning lines and the data lines are arranged in a crossing manner; the scanning line and the data line are both connected with the driving circuit; a first parasitic capacitance is included between the data line and the first node;

the anti-flicker module is used for providing a coupling signal for the data line in a holding stage in a first display mode; the first display mode includes a refresh phase and the hold phase between adjacent ones of the refresh phases.

In another aspect, the present application discloses a driving method of a display panel, the display panel including: a pixel, and a driving circuit driving the pixel; the driving circuit comprises a driving transistor, and the grid electrode of the driving transistor is a first node;

The scanning lines and the data lines are arranged in a crossing manner; the scanning line and the data line are both connected with the driving circuit; a first parasitic capacitance is included between the data line and the first node;

The driving method includes: a first display drive mode and a second display drive mode, the display refresh rate of the first display drive mode being less than the display refresh rate of the second display drive mode;

In a first display mode, comprising a refresh phase and a hold phase, the hold phase being located between adjacent refresh phases; in the hold phase, a coupling signal is provided to the data line.

In another aspect, the present application provides a display device comprising a display panel as described above.

According to the display panel and the display device provided by the application, leakage current can be reduced, and the phenomenon that the display panel flickers under low-frequency driving is prevented.

Drawings

Other features, objects and advantages of the present application will become more apparent upon reading of the detailed description of non-limiting embodiments, made with reference to the accompanying drawings in which:

FIG. 1 is a schematic diagram showing the change of the gate potential of a driving transistor in the prior art;

FIG. 2 shows a schematic diagram of a display panel in one embodiment of the application;

Fig. 3 shows an equivalent circuit schematic diagram of the driving circuit at X in fig. 2;

FIG. 4 is a schematic diagram showing the layout of the driving circuit at X in FIG. 2 as viewed from the light exit surface;

FIG. 5 is a schematic diagram of the layout of the driving circuit at X in FIG. 2 as viewed from a non-light emitting surface;

FIG. 6 shows a cross-sectional view of a display panel according to an embodiment of the present application;

FIG. 7 shows a 60Hz timing diagram of a display panel in accordance with an embodiment of the present application;

FIG. 8 shows a 15Hz timing diagram of a display panel in accordance with an embodiment of the present application;

fig. 9 shows a timing chart of 15Hz of a display panel according to another embodiment of the present application;

FIG. 10 is a timing diagram of a display panel according to another embodiment of the present application;

Fig. 11 shows a schematic diagram of a display device in an embodiment of the application.

Detailed Description

The application is described in further detail below with reference to the drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the application and are not limiting of the application. It should be noted that, for convenience of description, only the portions related to the application are shown in the drawings.

It should be noted that, without conflict, the embodiments of the present application and features of the embodiments may be combined with each other. The application will be described in detail below with reference to the drawings in connection with embodiments.

Wearable devices, such as watches, do not have high demands on the display effect, but have a need for low power consumption. Therefore, in order to reduce power consumption, products such as watches generally use a low frequency driving method to reduce power consumption, but unlike the low frequency driving of the liquid crystal display panel, the low frequency driving of the OLED display panel has a flicker problem. As a result of the analysis by the inventors, it was found that, since the organic light emitting display panel is driven by a current, the driving current of the pixel driving circuit generating the driving circuit is determined by the voltage difference (Vgs) between the source and gate of the driving transistor. The source of the driving transistor receives the power supply voltage, and the gate of the driving transistor receives the data signal voltage and stores the data signal voltage in the storage capacitor. The power supply voltage is an active signal, and the data signal voltage is stored in the storage capacitor. But the voltage of the data signal stored in the gate of the driving transistor is changed due to the channel leakage current and the film leakage current. The point position Vg of the grid electrode of the driving transistor is changed, so that Vgs is changed, brightness jump is caused, and a flicker phenomenon occurs. At a normal driving frequency, for example, in a 60Hz mode, the time of one frame is 16.67ms, the potential of the gate (N1) of the driving transistor changes as shown in fig. 1, the potential of the N1 node drops less at 60Hz, and the brightness changes less, which is not easily recognized by human eyes. However, by 30Hz, the time of one frame becomes 33.33ms, and the drop value of the n1 node potential is relatively large while the frequency is reduced, so that flickering can be observed by the human eye. Further, the drop value of the n1 node potential becomes larger at the time of the next frame of 15Hz to become 66.67ms, while the frequency is reduced more, so that flickering can be clearly observed by the human eye. Resulting in the unavailability of low frequency driving, limiting the power consumption reduction of the OLED display panel.

In one embodiment of the present application, please refer to fig. 2-8, fig. 2 shows a schematic diagram of a display panel in one embodiment of the present application; fig. 3 shows an equivalent circuit schematic diagram of the driving circuit at X in fig. 2; FIG. 4 is a schematic diagram showing the layout of the driving circuit at X in FIG. 2 as viewed from the light exit surface; FIG. 5 is a schematic diagram of the layout of the driving circuit at X in FIG. 2 as viewed from a non-light emitting surface; FIG. 6 shows a cross-sectional view of a display panel according to an embodiment of the present application;

FIG. 7 shows a 60Hz timing diagram of a display panel in accordance with an embodiment of the present application; FIG. 8 shows a 15Hz timing diagram of a display panel in accordance with an embodiment of the present application;

The display panel of the present application includes: a pixel P, and a driving circuit PC that drives the pixel P; the driving circuit PC includes a driving transistor M3, and a gate of the driving transistor M3 is a first node N1; a scan line 100 and a data line 200 disposed to cross each other; the scan line 100 and the data line 200 are both connected to the driving circuit PC;

The driving circuit of fig. 3 will be described as an example. The present embodiment further includes a first light emitting control transistor M1 in addition to the driving transistor M3, the first light emitting control transistor M1 being controlled by a light emitting control signal Emit to provide a first power supply voltage signal PVDD to the driving transistor M3; and the second light-emitting control transistor is connected in series between the driving transistor M3 and the light-emitting element and is controlled by a light-emitting control signal Emit to control whether the driving current passes through the light-emitting element. A data writing transistor M2, wherein the data writing transistor M2 is controlled by a second scanning signal S2 to transmit a data signal Vdata to the driving transistor M3; the compensation transistor M4 is controlled by the second scan signal S2 for detecting and self-compensating the deviation of the threshold voltage of the driving transistor M3; the first initializing transistor M5 is controlled by the first scanning signal S1 to provide an initializing signal for the grid electrode of the driving transistor; the second initialization transistor M7 is controlled by the first scan signal S1 or the second scan signal S2 to provide an initialization signal to the organic light emitting element. The scan line 100 supplies the first scan signal S1, the second scan signal S2, and the emission control signal Emit to the driving circuit. The data line 200 supplies a data signal voltage Vdata to the pixel circuit.

In the initialization phase: the first scan signal S1 provides an active level, and the second scan signal and the light emission control signal provide a cut-off level; the first initialization transistor M5 is turned on, the initialization signal Vref is transmitted to the gate of the driving transistor M3, and initialization is performed on the driving transistor M3, where the potential of the node N1 of the gate of the driving transistor M3 is Vref;

In the compensation phase: the first scanning signal S1 provides a cut-off level, the second scanning signal provides an active level, and the light-emitting control signal provides a cut-off level; the data writing transistor M2 and the compensating transistor M4 are turned on, the data signal voltage Vdata is transmitted from the data writing transistor to the first pole of the driving transistor M3, at this time, the driving transistor M3 meets the condition of being turned on, so that the driving transistor M3 is turned on, the data signal voltage is transmitted to the N1 node through the driving transistor M3 and the compensating transistor M4, the potential of the N1 node is raised, until the potential difference between the gate of the driving transistor and the first pole is the threshold voltage Vth of the driving transistor M3, the driving transistor M3 is turned off, the potential of the N1 node cannot be raised continuously, and at this time, the potential of the N1 node is Vdata- |vth|.

In the light-emitting stage: the first scan signal S1 and the second scan signal S2 provide a cut-off level, and the light emission control signal provides an active level; the first light emission control transistor M1 and the second light emission control transistor M2 are turned on, the first light emission control transistor M1 transmits the first power supply voltage PVDD to the source of the driving transistor, and the light emission current is ids=k (Vgs-Vth)/(2=k (PVDD-Vdata)/(2). Accordingly, the light emission current is independent of the threshold voltage, so that the driving transistor compensates for the deviation of the threshold voltage.

Referring to the layout of fig. 4 and 5 and the film structure diagram of fig. 6, the initialization signal line 110 transmits the initialization signal Vref, the first scan signal line 101 transmits the scan signal S1, and the second scan signal line 102 transmits the second scan signal S2; the light emission signal line 103 supplies a light emission control signal Emit; the power signal line 210 transmits a power signal PVDD, and the lateral power signal line 120 is connected to the power signal line 210 through a via hole, transmits the power signal PVDD, and serves as one pole of a storage capacitor. Referring to fig. 6, the semiconductor layer in the pixel driving circuit is made of poly, and the first scanning signal line 101, the second scanning signal line 102, and the light emitting signal line 103 are located on the gate metal layer M1 as gates of transistors. The initialization signal line 110, the lateral power signal line 120 is located in the capacitor metal layer Mc, and the power signal line 210 and the data line 200 are located in the source drain metal layer M2. Meanwhile, the pixel P includes a light emitting element including an anode 500, a cathode 700, and an organic light emitting material 600 between the cathode and the anode, and the anode 500 is connected to the drain electrode M2 of the transistor through a via.

In the low frequency driving, the potential of the N1 node of the gate electrode of the driving transistor M3 needs to be maintained for a long time, and the leakage current causes the N1 node potential to continuously vary, for example: the M5 transistor leaks electricity, so that the potential of the N1 node is continuously pulled down by Vref, and therefore the luminous current Ids is continuously increased, and brightness improvement occurs. Or the potential of the N1 node is pulled down by the electric leakage between the film layers. And the brightness is rapidly reduced until the next frame of writing the data signal voltage, so that the human eye observes the flicker phenomenon.

The application is arranged in the layout of the driving circuit PC, and a first parasitic capacitance Ca is arranged between the data line 200 and the first node N1; referring to fig. 4, 5 and 6, a portion C1 of the data line 200 and a portion C2 of the node N1 are close to each other, resulting in parasitic capacitance therebetween. Therefore, in the present application, an anti-flicker module 30 is disposed on the display panel, and in the first display mode, the anti-flicker module 30 is configured to provide a coupling signal to the data line in the hold phase; the coupling signal on the data line is transmitted to the gate first node N1 of the driving transistor through the parasitic capacitance Ca, and the potential variation of the N1 node is canceled, thereby improving or even eliminating the flicker phenomenon. The coupling signal of the present application refers to a difference from a signal at a previous time. For example: the signal on the data line at the previous time is 1v, the coupling signal is 2v, and a signal of 3v needs to be provided on the data line.

The first display mode includes a refresh phase and the hold phase between adjacent ones of the refresh phases; the display panel also comprises a second display mode, and the display refresh rate of the second display mode is larger than that of the first display mode; the display refresh rate of the first display mode is less than or equal to 30Hz. Referring to fig. 7 and 8, fig. 7 is a second display mode (normal driving mode), and fig. 8 is a first display mode (low frequency driving mode). In the first display mode, although the time per frame is increased, the time to refresh data is not increased in the present application. For example: when the second display mode is 60Hz and the first display mode is 15Hz, the time of one frame of the second display mode is 16.67ms, and the time of the refreshing stage is 16.67ms; the first display mode has a frame time of 66.67ms, wherein the refresh period has a time of 16.67ms, and three hold periods of the hold period between two adjacent refresh periods each have a time of 16.67ms. In the first display mode, the anti-flicker module 30 provides a coupling signal to the data line in the hold phase; the coupling signal on the data line is transmitted to the gate first node N1 of the driving transistor through the parasitic capacitance Ca, and the potential variation of the N1 node is canceled, thereby improving or even eliminating the flicker phenomenon.

The application also provides a driving method of the display panel, which is used for driving the display panel. The display panel includes pixels P, and a driving circuit PC driving the pixels P; the driving circuit comprises a driving transistor M3, and the grid electrode of the driving transistor M3 is a first node N1; a scan line 100 and a data line 200 disposed to cross each other; the scan line 100 and the data line 200 are both connected to the driving circuit PC; the data line 200 includes a first parasitic capacitance Ca between the first node N1; the driving method comprises the following steps: a first display drive mode and a second display drive mode, the first display drive mode having a display refresh rate less than a display refresh rate of the second display drive mode;

In a first display mode, including a refresh phase and a hold phase, the hold phase being located between adjacent refresh phases; in the hold phase, a coupling signal is provided to the data line 200. The coupling signal on the data line is transmitted to the gate first node N1 of the driving transistor through the parasitic capacitance Ca, and the potential variation of the N1 node is canceled, thereby improving or even eliminating the flicker phenomenon.

Further, the anti-flicker module 30 further comprises a multiplexer 40, the multiplexer 40 comprising a plurality of multiplexer units 41, each multiplexer unit comprising 1 input 411 and N outputs 412 and N controls; each output end 412 is correspondingly connected with the data line 200; n is an integer not less than 2; taking n=2 as an example in fig. 2, each multiplexer unit 41 includes 1 each input terminal 411 and 2 each output terminal 412 and two control terminals CKH1 and CKH2, when CKH1 is at an active level, a data signal is transmitted to a data line corresponding to CKH1 through the input terminal 411, and when CKH2 is at an active level, a data signal is transmitted to a data line corresponding to CKH2 through the input terminal 411.

In the first display mode, the N control end turns on, and the input end 411 outputs data signals to the output end 412 in turn; referring to fig. 7, CKH1 and CKH2 are alternately turned on before the active pulse of SCAN1, and data signals are written to the data lines 200 of the odd columns and the even columns, respectively, and the data signals are stored in parasitic capacitances of the data lines, respectively. When SCAN1 outputs an active level, a data signal is written to the gate of the driving transistor M3. After the valid pulse of SCAN1, CKH1 and CKH2 are again turned on in turn before the valid pulse of SCAN2, and data signals are again written to the data lines 200 of the odd columns and the even columns, respectively, and the data signals are stored in parasitic capacitances of the data lines, respectively. When SCAN2 outputs an active level, a data signal is written to the gate of the driving transistor M3. And so on. Note that SCAN1 represents the second SCAN signal S2 of the first row, SCAN2 represents the second SCAN signal S2 of the second row, and so on. EMIT1 represents the emission control signal EMIT of the first row. Here, fig. 7 shows only the light emission control signals of the first row.

In one embodiment of the present application, referring to fig. 8, in the second display mode, N controlled end wheel flows are turned on during the refresh phase, and an input end wheel flows to the output end to output a data signal; in the holding stage, each control end is started at least once, and the output end transmits a coupling signal to the data line. Specifically, in the refresh stage, CKH1 and CKH2 are alternately turned on before the active pulse of SCAN1, and data signals are written to the data lines 200 of the odd columns and the even columns, respectively, and the data signals are stored in parasitic capacitances of the data lines, respectively. When SCAN1 outputs an active level, a data signal is written to the gate of the driving transistor M3. After the valid pulse of SCAN1, CKH1 and CKH2 are again turned on in turn before the valid pulse of SCAN2, and data signals are again written to the data lines 200 of the odd columns and the even columns, respectively, and the data signals are stored in parasitic capacitances of the data lines, respectively. When SCAN2 outputs an active level, a data signal is written to the gate of the driving transistor M3. In the hold phase, CKH1 and CKH2 are turned on at least once, a coupling signal is supplied to the data line 200 through the input terminal 411, and a voltage difference of the data line is coupled to the gate N1 of the driving transistor to compensate for the leakage of N1, thereby preventing flicker.

Further, referring to fig. 8, CKH1 and CKH2 are alternately turned on, the output terminal 412 sequentially transmits a coupling signal to the data line 200, the voltage of the first node N1 is changed by the first parasitic capacitance Ca, CKH1 and CKH2 are sequentially turned on, the coupling signal is provided to the data line 200 through the input terminal 411, and the voltage difference of the data line is coupled to the gate N1 of the driving transistor to compensate for the leakage of N1, thereby avoiding flicker. The current efficiency of the different sub-pixels is different, for example the blue sub-pixel is driven with higher current than the red and green sub-pixels, so the blue sub-pixel requires a larger coupling signal when the same brightness needs to be compensated. Therefore, in this embodiment, the blue sub-pixel may use a separate data line, and different potentials may be coupled to the N1 nodes corresponding to the sub-pixels of different colors by alternately turning on CKH1 and CKH 2. For example: a larger coupling signal is coupled to the blue subpixel. Specifically, further, the display panel includes: a red pixel R, a green pixel G, and a blue pixel B; the anti-flicker module 30 provides a first coupling signal to the data lines corresponding to the red pixel R and the green pixel G, and provides a second coupling signal to the data lines corresponding to the blue pixel B, the second coupling signal being greater than the first coupling signal.

Alternatively, referring to fig. 9, the output terminal 412 simultaneously transmits a coupling signal to the data line 200, the voltage of the first node N1 is changed by the first parasitic capacitance Ca, CKH1 and CKH2 are simultaneously turned on, the coupling signal is provided to the data line 200 through the input terminal 411, and the voltage difference of the data line is coupled to the gate N1 of the driving transistor to compensate for the leakage of N1, thereby avoiding flicker. According to the method, the time for coupling can be saved, all the sub-pixels of the display panel are simultaneously coupled without being coupled in columns, the problem that the coupling in columns causes different columns to compensate the leakage of N1 nodes at different moments, for example, the odd rows compensate N1 nodes and the even rows do not compensate, so that the intense contrast can cause human eyes to perceive, and the coupling can avoid the problem.

Further, since the data signal voltage of the last write data line 200 in the refresh stage depends on the luminance information of the last row of subpixels, the luminance information is not the same in each column. The coupling signal is the target potential written in the data line again minus the residual potential of the data line at the last moment. If the residual potential of each row at the previous time is different, the target potential to be written needs to be calculated according to the residual potential at the previous time, which increases the load of the IC. Therefore, in this embodiment, an initialization signal is provided to the data line after the refresh phase and before the hold phase. The residual potential of each column is the same, so that the difference value between the target potential and the initializing signal is the coupling signal, thereby greatly reducing the calculation difficulty of the coupling signal, reducing the load of the IC and reducing the power consumption of the display panel.

Referring to fig. 8 and 9, the display panel further includes a second display mode; the display refresh rate of the first display mode is Q, and the display refresh rate of the second display mode is P; the first display mode comprises a refresh stage and M holding stages which are circularly arranged; wherein the M holding stages comprise a first holding stage to an Mth holding stage; m is an integer greater than or equal to 2;

For example, when the second display mode is 60Hz and the first display mode is 15Hz, the time of one frame of the second display mode is 16.67ms, and the time of the refresh stage is 16.67ms; the first display mode has a frame time of 66.67ms, wherein the refresh period has a time of 16.67ms, and the 3 hold periods of the hold period between two adjacent refresh periods each have a time of 16.67ms. In the first display mode, the anti-flicker module 30 provides a coupling signal to the data line in the hold phase; the coupling signal on the data line is transmitted to the gate first node N1 of the driving transistor through the parasitic capacitance Ca, and the potential variation of the N1 node is canceled, thereby improving or even eliminating the flicker phenomenon. The anti-flicker module 30 sequentially provides the 1 st to 3 rd coupling signals to the data lines in the 1 st to 3 rd holding phases; the first coupling signal is smaller than the second coupling signal, and the second coupling signal is equal to the Mth coupling signal. Since the data signals are written in the first row to the last row in turn at the first coupling of the first holding stage, parasitic capacitances exist between the data lines and the first nodes N1 of all rows, and thus are simultaneously coupled to the N1 nodes. However, according to the foregoing, the leakage time of the first row is different from the leakage time of the last row, the leakage time of the first row is the longest, and the leakage time of the last row is the shortest, so in this embodiment, the first coupling signal is calculated based on the leakage time of the middle row, and thus the leakage time involved in the calculation is relatively short, and thus the first coupling signal is relatively idle. After the first coupling, all rows are for a holding period of leakage, so the second to mth coupling signals are all the same and are all larger than the first coupling signal. The first coupling overcompensation can be avoided according to the arrangement of the embodiment.

In another embodiment of the present application, since the present application essentially couples the first node N1 by using the parasitic capacitance of the data line, the leakage current is compensated. While the multiplexer writes the coupling signal to the data line, it essentially charges the parasitic capacitance on the data line. When the parasitic capacitance is charged, the potential on the data line cannot jump to the target potential immediately, but a rising edge or a falling edge occurs, and when the coupling signal is relatively large, the time for rising or falling to the target potential is relatively long, so in this embodiment, the on-duration of the control signal is proportional to the absolute value of the coupling signal. So that, however, the coupling signal is relatively large, a sufficient charging time can be provided at the target potential. Specifically, for example: at the end of the refresh phase, the potential of the data line is 1V, the coupling signal is 1V and 5V, respectively, when the coupling signal is 1V, the target potential is 2V, and writing the potential of 2V to the data line only requires lifting the potential by 1V, so that the duration of the rising edge is relatively short, for example, 0.5 μs, the on time of the control signal can be 2 μs, and thus the charging time of 1.5 μs at the target potential is provided. When the coupling signal is 5V, the target potential is 6V, and writing the potential of 6V to the data line requires raising the potential by 5V, so that the duration of the rising edge is relatively long, for example, 1 μs, and the on time of the control signal may be 2.5 μs, so that there is still a charging time of 1.5 μs at the target potential. Therefore, the application can set the opening time of the control signal according to the magnitude of the coupling signal, and avoid the phenomenon of insufficient charging when the absolute value of the coupling signal is too large, thereby causing insufficient compensation.

Further, writing the coupling signal to the data line causes the first node N1 to jump in a short time, thereby causing the brightness to jump in a short time, and in order to avoid such jump being perceived, the embodiment further includes: a light emission control signal EMIT and front and rear lanes; the light-emitting control signal EMIT is a PWM modulation signal; when the control end is opened, the luminous control signals EMIT are effective signals in the front corridor and the rear corridor. Referring to fig. 10, fig. 10 is a schematic diagram of a display panel according to another embodiment of the application; pulse width modulation, PWM, which is to use a pulse train with equal pulse width as a PWM waveform, frequency can be modulated by changing the period of the pulse train, the width or duty ratio of the pulse can be changed to achieve brightness, and a proper control method can be adopted to coordinate and change the voltage and the frequency. The brightness can be controlled by adjusting the period of the PWM and the duty ratio of the PWM. In the figure, emit1 represents the emission control signal of the first row, emit2 represents the emission control signal of the second row, and so on, and Emit12 represents the emission control signal of the 12 th row. This embodiment is exemplified by 12, but the present application is not limited thereto. The light emission control signal of the present embodiment may be to control the first light emission control transistor M1 and the second light emission control transistor M6 in fig. 3, and control whether or not a current flows through the light emitting element. When the light emission control signal is at the off level, the pixels of the current row do not emit light; when the light emission control signal is at an on level, the pixels of the current row emit light. The light emission control signals are transmitted step by step through the shift register circuit, and as indicated by arrows in the figure, the light emission control signals are "scrolled" and the display panel is also "scrolled" displayed. Therefore, at a certain time t1, the light emission control signals of some pixel rows are at the active level, the pixels of these rows emit light, and these pixel rows form a bright band. The light emission control signals of other pixel rows are off-level, the pixels of the rows do not emit light, and the pixel rows form dark bands. In addition, the display panel preferably includes front and rear lanes, which do not correspond to actual pixels, are virtual rows, and are waiting phases for loading data signals, in addition to the display rows. In this embodiment, the light emission control signals in the front and rear lanes are all at an active level, so that the bright band is located in the front and rear lanes, but the front and rear lanes are not emitting light, so that the number of lines of the bright band in the actual display area is minimal, and thus the number of lines of the display is minimal due to the change of the coupling signal, so as to avoid the perception of human eyes.

On the other hand, the inventors have found through studies that the sensitivity of human eyes to luminance is related to the luminance value before the change. When the brightness value is lower, the brightness is raised or lowered at a moment can be obviously perceived. When the brightness is high, the brightness is raised or lowered instantaneously, so that the brightness is difficult to be perceived.

In this embodiment, the first display mode includes a low gray mode and a high gray mode, in which the anti-flicker module 30 provides the third coupling signal to the data line 200; in the low gray scale mode, the anti-flicker module 30 provides a fourth coupling signal to the data line 200; the fourth coupling signal is smaller than the third coupling signal. Therefore, the condition that the coupling signal is too large under the low gray scale and flicker is caused can be avoided, and meanwhile, the condition that the compensation value is insufficient under the high gray scale is avoided.

The display device of the present application may be any device comprising a drive unit as described above, including but not limited to a cellular phone 1000, a tablet computer, a display of a computer, a display applied to a smart wearable device, a display applied to a vehicle such as an automobile, etc., as shown in fig. 11. As long as the display device includes the driving unit included in the display device disclosed in the present application, it is considered to fall within the scope of the present application.

According to the foldable display panel and the display device provided by the application, the risk of wire breakage can be reduced, the driving capability is improved, and the display effect and the display stability are enhanced.

It will be appreciated by persons skilled in the art that the scope of the application referred to in the present application is not limited to the specific combinations of the technical features described above, but also covers other technical features formed by any combination of the technical features described above or their equivalents without departing from the inventive concept. Such as the above-mentioned features and the technical features disclosed in the present application (but not limited to) having similar functions are replaced with each other.

Claims (14)

1. A display panel is characterized by comprising,

A pixel, and a driving circuit driving the pixel; the driving circuit comprises a driving transistor, and the grid electrode of the driving transistor is a first node;

The scanning lines and the data lines are arranged in a crossing manner; the scanning line and the data line are both connected with the driving circuit; a first parasitic capacitance is included between the data line and the first node;

The anti-flicker module is used for providing a coupling signal for the data line in a holding stage in a first display mode; the first display mode includes a refresh phase and the hold phase between adjacent refresh phases;

The gate of the driving transistor is located on the first metal layer, the first node further comprises a first semiconductor layer, the data line is located on the source drain metal layer, and is located on one side, away from the first semiconductor layer, of the first metal layer along the thickness direction of the display panel, and the data line is not overlapped with the first semiconductor layer.

2. The display panel of claim 1, wherein the display panel comprises,

The display refresh rate of the first display mode is less than or equal to 30Hz.

3. The display panel of claim 1, wherein the display panel comprises,

The anti-flicker module comprises a multiplexer, wherein the multiplexer comprises a plurality of multiplexer units, and each multiplexer unit comprises 1 input end, N output ends and N control ends; each output end is correspondingly connected with the data line; n is an integer not less than 2;

The display panel also comprises a second display mode, wherein the display refresh rate of the second display mode is larger than that of the first display mode;

In a first display mode, N control ends are turned on in turn, and the input end flows to the output end to output data signals;

in a second display mode, in a refreshing stage, N control ends are turned on in turn, and the input end flows to the output end to output a data signal; in the holding stage, each control end is started at least once, and the output end transmits a coupling signal to the data line.

4. The display panel according to claim 3, wherein,

In a second display mode, in a refreshing stage, N control ends are turned on in turn, and the input end flows to the output end to output a data signal;

In the course of the hold-in phase,

Each control end is sequentially opened, the output end sequentially transmits coupling signals to the data line, and the first node voltage is changed through the first parasitic capacitance, or

And the control ends are simultaneously started, the output ends simultaneously transmit coupling signals to the data lines, and the voltage of the first node is changed through the first parasitic capacitance.

5. A display panel according to claim 3, comprising:

In the hold phase, the on-time of the control terminal is proportional to the absolute value of the coupling signal.

6. A display panel according to claim 3, further comprising: a lighting control signal and front and rear lanes; the light-emitting control signal is a PWM modulation signal;

When the control end is opened, the luminous control signals are effective signals in the front corridor and the rear corridor;

the front and rear lanes do not correspond to the pixels, the front and rear lanes do not scan the pixels, and the front and rear lanes are waiting phases for loading the data signals.

7. The display panel of claim 1, wherein the display panel comprises,

The display panel further includes a second display mode; the display refresh rate of the first display mode is Q, and the display refresh rate of the second display mode is P;

The first display mode comprises a refresh stage and M holding stages which are circularly arranged; wherein the M holding stages comprise a first holding stage to an Mth holding stage; m is an integer greater than or equal to 2;

the anti-flicker module sequentially provides a first coupling signal to an Mth coupling signal for the data line in the first holding stage to the Mth holding stage;

The first coupling signal is smaller than the second coupling signal, and the second coupling signal is equal to the Mth coupling signal.

8. The display panel of claim 1, wherein the display panel comprises,

After the refresh phase and before the hold phase, an initialization signal is provided to the data line.

9. The display panel according to claim 1, comprising:

Red, green and blue pixels; the anti-flicker module provides a first coupling signal to the data lines corresponding to the red pixels and the green pixels, and provides a second coupling signal to the data lines corresponding to the blue pixels, wherein the second coupling signal is greater than the first coupling signal.

10. The display panel of claim 1, wherein the display panel comprises,

The first display mode comprises a low gray scale mode and a high gray scale mode, and the anti-flicker module provides a third coupling signal for the data line in the high gray scale mode; in the low gray scale mode, the anti-flicker module provides a fourth coupling signal to the data line; the fourth coupling signal is smaller than the third coupling signal.

11. The display panel of claim 1, wherein the display panel comprises,

The driving circuit further comprises a power signal line, and in the driving circuit of the present stage, the data line is located at one side of the power signal line close to the first node.

12. The display panel of claim 11, wherein the display panel comprises,

The power signal line and the data line are arranged on the same layer.

13. A driving method of display panel is characterized in that,

The display panel includes: a pixel, and a driving circuit driving the pixel; the driving circuit comprises a driving transistor, and the grid electrode of the driving transistor is a first node;

The scanning lines and the data lines are arranged in a crossing manner; the scanning line and the data line are both connected with the driving circuit; a first parasitic capacitance is included between the data line and the first node; the grid electrode of the driving transistor is positioned on the first metal layer, the first node further comprises a first semiconductor layer, the data line is positioned on the source-drain metal layer, and along the thickness direction of the display panel, the data line is positioned on one side, far away from the first semiconductor layer, of the first metal layer, and the data line is not overlapped with the first semiconductor layer;

the driving method includes: a first display mode and a second display mode, the display refresh rate of the first display mode being less than the display refresh rate of the second display mode;

In a first display mode, comprising a refresh phase and a hold phase, the hold phase being located between adjacent refresh phases; in the hold phase, a coupling signal is provided to the data line.

14. A display device comprising the display panel according to any one of claims 1 to 12.