CN114979541A - Video display system - Google Patents
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- CN114979541A CN114979541A CN202210622112.5A CN202210622112A CN114979541A CN 114979541 A CN114979541 A CN 114979541A CN 202210622112 A CN202210622112 A CN 202210622112A CN 114979541 A CN114979541 A CN 114979541A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N7/00—Television systems
- H04N7/015—High-definition television systems
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/44—Decoders specially adapted therefor, e.g. video decoders which are asymmetric with respect to the encoder
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Abstract
The present disclosure provides a video display system, wherein the video display system comprises: the input data analysis module is used for converting the received high-speed serial signals into low-speed parallel signals and decoding the low-speed parallel signals into 8K video signals; the image processing module is connected with the input data analysis module and is used for carrying out resolution identification and HDR decoding on the 8K video signal to obtain a display linear light signal; and the output data display module is connected with the image processing module and used for outputting the linear display optical signals to a display screen for display. By the method and the device, the ultra-high-definition high-dynamic-range video display system which simultaneously supports DP2.0+ HDMI2.1+ HDR + VbyOne is realized.
Description
Technical Field
The invention relates to the technical field of image processing and display, in particular to a video display system.
Background
With the development of 5G communication technology and the commercial use of 8K ultra-high definition high dynamic range display products, a '5G +8K + High Dynamic Range (HDR)' video program is live broadcast, the high-speed development of an ultra-high definition industrial chain is promoted, and a plurality of audiences and friends who cannot be in the scene can really feel the hot atmosphere and the visual impact of the program.
Most of the market utilize a chip to build a display system, for example, haisi Hi3796CV300 receives and analyzes 8K data through HDMI _ RX, and then displays the 8K data through an HDMI _ TX dot screen. The new 8K chip can support the input and output of 8K ultrahigh-definition high-dynamic-range data to build a display system. But only supports HDMI2.1, and does not have HDR, DP2.0 interface and VbyOne interface at the same time, but some PC display cards have only DP interface and some display screens have only VbyOne interface at present. If the display system does not have a DP or VbyOne interface, the available scenes of the system are limited.
At present, no ultra-high definition high dynamic range display system which simultaneously supports DP2.0+ HDMI2.1+ HDR + VbyOne exists.
Disclosure of Invention
The present disclosure is directed to provide a video display system to solve at least the problem that there is no ultra-high definition high dynamic range display system supporting DP2.0+ HDMI2.1+ HDR + VbyOne at the same time in the related art.
According to an aspect of the present disclosure, there is provided a video display system including:
the input data analysis module is used for converting the received high-speed serial signals into low-speed parallel signals and decoding the low-speed parallel signals into 8K video signals;
the image processing module is connected with the input data analysis module and is used for carrying out resolution identification and HDR decoding on the 8K video signal to obtain a display linear light signal;
and the output data display module is connected with the image processing module and used for outputting the linear display optical signal to a display screen for displaying.
According to one or more technical schemes provided in the embodiments of the present disclosure, an input data parsing module is provided in a video display system, and is configured to convert a received high-speed serial signal into a low-speed parallel signal and decode the low-speed parallel signal into an 8K video signal; an image processing module is arranged and used for carrying out resolution identification and HDR decoding on the 8K video signal to obtain a display linear light signal; and an output data display module is arranged for outputting the display linear optical signal to a display screen for displaying, so that the ultra-high definition high dynamic range video display system which simultaneously supports DP2.0+ HDMI2.1+ HDR + Vbyone can be realized.
Drawings
Further details, features and advantages of the disclosure are disclosed in the following description of exemplary embodiments, taken in conjunction with the accompanying drawings, in which:
FIG. 1 shows a schematic diagram of a video display system according to an exemplary embodiment of the present disclosure;
FIG. 2 illustrates a block diagram of an exemplary electronic device that can be used to implement embodiments of the present disclosure.
Detailed Description
Embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While certain embodiments of the present disclosure are shown in the drawings, it is to be understood that the present disclosure may be embodied in various forms and should not be construed as limited to the embodiments set forth herein, but rather are provided for a more thorough and complete understanding of the present disclosure. It should be understood that the drawings and embodiments of the disclosure are for illustration purposes only and are not intended to limit the scope of the disclosure.
It should be understood that the various steps recited in the method embodiments of the present disclosure may be performed in a different order, and/or performed in parallel. Moreover, method embodiments may include additional steps and/or omit performing the illustrated steps. The scope of the present disclosure is not limited in this respect.
The term "include" and variations thereof as used herein are open-ended, i.e., "including but not limited to". The term "based on" is "based, at least in part, on". The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment"; the term "some embodiments" means "at least some embodiments". Relevant definitions for other terms will be given in the following description. It should be noted that the terms "first", "second", and the like in the present disclosure are only used for distinguishing different devices, modules or units, and are not used for limiting the order or interdependence of the functions performed by the devices, modules or units.
It is noted that references to "a", "an", and "the" modifications in this disclosure are intended to be illustrative rather than limiting, and that those skilled in the art will recognize that "one or more" may be used unless the context clearly dictates otherwise.
The names of messages or information exchanged between devices in the embodiments of the present disclosure are for illustrative purposes only, and are not intended to limit the scope of the messages or information.
Aspects of the present disclosure are described below with reference to the accompanying drawings.
Exemplary embodiments of the present disclosure provide a video display system.
Fig. 1 illustrates a schematic diagram of a video display system according to an exemplary embodiment of the present disclosure, which may include, as shown in fig. 1:
the input data analysis module 10 is configured to convert a received high-speed serial signal into a low-speed parallel signal, and decode the low-speed parallel signal into an 8K video signal;
the image processing module 20 is connected to the input data parsing module 10, and configured to perform resolution identification and HDR decoding on the 8K video signal to obtain a display linear light signal;
and the output data display module 30 is connected with the image processing module 20 and is used for outputting the display linear optical signal to a display screen for displaying.
In some of these embodiments, the input data parsing module 10 includes:
a high-speed transceiver 101 for converting the high-speed serial signal into the low-speed parallel signal;
the HDMI2.1 input IP module 102 is configured to perform protocol decoding on the low-speed parallel signal, and decode the 8K video signal;
DP2.0 inputs to IP block 103, and is configured to perform protocol decoding on the low-speed parallel signal, and decode the 8K video signal.
The high-speed transceiver 101 is connected to the HDMI2.1 input IP module 102 and the DP2.0 input IP module 103, respectively.
In some of these embodiments, the image processing module 20 comprises:
a resolution processing module 201, configured to perform resolution identification on the 8K video signal;
an HDR decoding module 202, configured to perform HDR decoding on the 8K video signal to obtain the display linear light signal.
The resolution processing module 201 is connected to the HDMI2.1 input IP module 102 and the DP2.0 input IP module 103, respectively, and the HDR decoding module 202 is connected to the resolution processing module 201.
In some of these embodiments, the HDR decoding module 202 supports at least one of the HLG standard, the HDR10 standard, and the Dolby Vision standard.
HLG: the HDR standard HLG is a mixed Log Gamma distribution (Hybrid Log Gamma, HLG for short) developed by combining BBC and NHK. The HLG output does not have metadata, the coding value of the HLG is a relative value, the HLG coding is carried out according to percentages, HDR effects of different degrees can be generated according to different display devices, the HLG coding has self-adaption performance, and the HLG coding can be compatible with HDR display and SDR display at the same time.
HDR 10: the HDR standard development is dominated by the American CTA consumer technology association and Samsung, and is widely applied to the fields of UGC video platforms, UHD blue light, film and television streaming media and the like. The transmission needs to carry dynamic metadata, and the absolute value of the brightness is displayed.
Dolby Vision: the HDR standard is developed by image quality technology introduced by dolby laboratories, usa, and enhances image effects by enhancing brightness and expanding dynamic range. It can improve the fidelity of video signal, thus make the picture very lifelike from the perspective of brightness, color or contrast. The transmission needs to carry dynamic metadata and display the absolute value of the brightness.
Compared with SDR, HDR can brighten the details of each dark part, make the dark part darker, enrich more detail colors, and make the image show rich and excellent effects.
In some of these embodiments, the output data display module 30 includes:
a VbyOne output IP module 301 connected to the HDR decoding module 202, wherein the display linear light signal is output to a display screen through the VbyOne output IP module 301 for display.
In some embodiments, the input data parsing module 10, the image processing module 20, and the output data display module 30 are disposed on an FPGA chip.
The FPGA chip is provided with a DP2.0 interface and/or an HDMI2.1 interface, wherein the high-speed serial signal enters the input data parsing module 10 through the DP2.0 interface and/or the HDMI2.1 interface. The FPGA chip is also provided with a VbyOne interface, wherein the linear display optical signal is output to a display screen for display through the VbyOne interface.
The system can realize the ultrahigh-definition high-dynamic-range video display system, and the system completes the conversion of front-end input signals based on the FPGA, outputs and lights up a display screen. 8K video signals of a computer or a television set top box enter an FPGA chip through a DP2.0 interface or an HDMI2.1 interface, a high-speed transceiver on the FPGA chip converts high-speed serial signals into low-speed parallel signals, the low-speed parallel signals are input into an IP through the DP2.0 interface or the HDMI2.1 for protocol decoding, the decoded 8K video signals are sent to a video resolution processing module for resolution recognition, and if the input resolution is 8, the 8K video signals are directly output to a rear-end HDR decoding module; if the input resolution is lower than 8K, the video resolution is amplified and then sent to the rear-end HDR decoding module. The HDR decoding module automatically identifies an HDR mode, carries out HDR video signal reduction and color processing according to parameters of a rear-end display screen and a color gamut space conversion principle, acquires a display linear light signal, directly outputs the processed display linear light signal to a rear-end Vbyone output IP, and finally outputs the processed display linear light signal to a display chip to control the display screen to display.
The DP2.0 interface and the VbyOne interface are added in the video signal transmission device, and a real 8K video signal without compression can be transmitted. And the application range of the DP interface and the VbyOne interface is wider, so the system can adapt to more application scenes.
The method adopts the FPGA scheme, utilizes the real-time processing capacity of the FPGA, can reduce the response time of video processing, and achieves the effects of low delay and flexible matching of different display screens.
The CUVA High Dynamic Range (HDR) standard formally released by CUVA of the ultra high definition industry alliance in China can be met, more technical expansion can be completed, and the CUVA High Dynamic Range (HDR) standard can be flexibly applied according to market demands.
An exemplary embodiment of the present disclosure also provides an electronic device including: at least one processor; and a memory communicatively coupled to the at least one processor. The memory stores a computer program executable by the at least one processor, the computer program, when executed by the at least one processor, is operable to cause the electronic device to perform a method of an embodiment of the disclosure, such as a resolution processing method of a resolution processing module in an image processing module.
The disclosed exemplary embodiments also provide a non-transitory computer readable storage medium storing a computer program, wherein the computer program, when executed by a processor of a computer, is configured to cause the computer to perform a method according to an embodiment of the present disclosure, for example, a resolution processing method of a resolution processing module in an image processing module.
The exemplary embodiments of the present disclosure also provide a computer program product comprising a computer program, wherein the computer program, when executed by a processor of a computer, is adapted to cause the computer to perform a method according to an embodiment of the present disclosure.
Referring to fig. 2, a block diagram of a structure of an electronic device 200, which may be a server or a client of the present disclosure, which is an example of a hardware device that may be applied to aspects of the present disclosure, will now be described. Electronic device is intended to represent various forms of digital electronic computer devices, such as laptops, desktops, workstations, personal digital assistants, servers, blade servers, mainframes, and other suitable computers. The electronic device may also represent various forms of mobile devices, such as personal digital processing, cellular phones, smart phones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions, are meant to be examples only, and are not meant to limit implementations of the disclosure described and/or claimed herein.
As shown in fig. 2, the electronic apparatus 200 includes a computing unit 201 that can perform various appropriate actions and processes in accordance with a computer program stored in a Read Only Memory (ROM)202 or a computer program loaded from a storage unit 208 into a Random Access Memory (RAM) 203. In the RAM 203, various programs and data necessary for the operation of the device 200 can also be stored. The computing unit 201, the ROM 202, and the RAM 203 are connected to each other via a bus 204. An input/output (I/O) interface 205 is also connected to bus 204.
A number of components in the electronic device 200 are connected to the I/O interface 205, including: an input unit 206, an output unit 207, a storage unit 208, and a communication unit 209. The input unit 206 may be any type of device capable of inputting information to the electronic device 200, and the input unit 206 may receive input numeric or character information and generate key signal inputs related to user settings and/or function control of the electronic device. Output unit 207 may be any type of device capable of presenting information and may include, but is not limited to, a display, speakers, a video/audio output terminal, a vibrator, and/or a printer. The storage unit 208 may include, but is not limited to, a magnetic disk, an optical disk. The communication unit 209 allows the electronic device 200 to exchange information/data with other devices via a computer network, such as the internet, and/or various telecommunications networks, and may include, but is not limited to, modems, network cards, infrared communication devices, wireless communication transceivers and/or chipsets, such as bluetooth devices, WiFi devices, WiMax devices, cellular communication devices, and/or the like.
The computing unit 201 may be a variety of general and/or special purpose processing components having processing and computing capabilities. Some examples of the computing unit 201 include, but are not limited to, a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), various dedicated Artificial Intelligence (AI) computing chips, various computing units running machine learning model algorithms, a Digital Signal Processor (DSP), and any suitable processor, controller, microcontroller, and so forth. The computing unit 201 performs the various methods and processes described above. For example, in some embodiments, the resolution processing method of the resolution processing module in the image processing module may be implemented as a computer software program tangibly embodied in a machine-readable medium, such as the storage unit 208. In some embodiments, part or all of the computer program may be loaded and/or installed onto the electronic device 200 via the ROM 202 and/or the communication unit 209. In some embodiments, the computing unit 201 may be configured to perform, for example, a resolution processing method of a resolution processing module in an image processing module, by any other suitable means (e.g., by means of firmware).
Program code for implementing the methods of the present disclosure may be written in any combination of one or more programming languages. These program codes may be provided to a processor or controller of a general purpose computer, special purpose computer, or other programmable data processing apparatus, such that the program codes, when executed by the processor or controller, cause the functions/operations specified in the flowchart and/or block diagram to be performed. The program code may execute entirely on the machine, partly on the machine, as a stand-alone software package partly on the machine and partly on a remote machine or entirely on the remote machine or server.
In the context of this disclosure, a machine-readable medium may be a tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device. The machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. More specific examples of a machine-readable storage medium would include an electrical connection based on one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.
As used in this disclosure, the terms "machine-readable medium" and "computer-readable medium" refer to any computer program product, apparatus, and/or device (e.g., magnetic discs, optical disks, memory, Programmable Logic Devices (PLDs)) used to provide machine instructions and/or data to a programmable processor, including a machine-readable medium that receives machine instructions as a machine-readable signal. The term "machine-readable signal" refers to any signal used to provide machine instructions and/or data to a programmable processor.
To provide for interaction with a user, the systems and techniques described here can be implemented on a computer having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to a user; and a keyboard and a pointing device (e.g., a mouse or a trackball) by which a user can provide input to the computer. Other kinds of devices may also be used to provide for interaction with a user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user may be received in any form, including acoustic, speech, or tactile input.
The systems and techniques described here can be implemented in a computing system that includes a back-end component (e.g., as a data server), or that includes a middleware component (e.g., an application server), or that includes a front-end component (e.g., a user computer having a graphical user interface or a web browser through which a user can interact with an implementation of the systems and techniques described here), or any combination of such back-end, middleware, or front-end components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: local Area Networks (LANs), Wide Area Networks (WANs), and the Internet.
The computer system may include clients and servers. A client and server are generally remote from each other and typically interact through a communication network. The relationship of client and server arises by virtue of computer programs running on the respective computers and having a client-server relationship to each other.
Claims (10)
1. A video display system, comprising:
the input data analysis module is used for converting the received high-speed serial signals into low-speed parallel signals and decoding the low-speed parallel signals into 8K video signals;
the image processing module is connected with the input data analysis module and is used for carrying out resolution identification and HDR decoding on the 8K video signal to obtain a display linear light signal;
and the output data display module is connected with the image processing module and used for outputting the linear display optical signal to a display screen for display.
2. The video display system of claim 1, wherein the input data parsing module comprises:
a high-speed transceiver for converting the high-speed serial signal into the low-speed parallel signal;
the HDMI2.1 input IP module is used for carrying out protocol decoding on the low-speed parallel signal and decoding the 8K video signal;
and the DP2.0 input IP module is used for carrying out protocol decoding on the low-speed parallel signal and decoding the 8K video signal.
3. The video display system of claim 2, wherein the high-speed transceiver is connected to the HDMI2.1 input IP block and DP2.0 input IP block, respectively.
4. The video display system of claim 2, wherein the image processing module comprises:
the resolution processing module is used for carrying out resolution identification on the 8K video signal;
and the HDR decoding module is used for carrying out HDR decoding on the 8K video signal to obtain the display linear light signal.
5. The video display system according to claim 4, wherein the resolution processing module is connected to the HDMI2.1 input IP module and DP2.0 input IP module, respectively, and the HDR decoding module is connected to the resolution processing module.
6. The video display system of claim 4, wherein the HDR decoding module supports at least one of an HLG standard, an HDR10 standard, and a Dolby Vision standard.
7. The video display system of claim 4, wherein the output data display module comprises:
and the VbyOne output IP module is connected with the HDR decoding module, wherein the display linear light signal is output to a display screen for display through the VbyOne output IP module.
8. The video display system of any one of claims 1-7, wherein the input data parsing module, the image processing module, and the output data display module are disposed on an FPGA chip.
9. The video display system of claim 8, wherein a DP2.0 interface and/or an HDMI2.1 interface is disposed on the FPGA chip, wherein the high-speed serial signal enters the input data parsing module through the DP2.0 interface and/or the HDMI2.1 interface.
10. The video display system of claim 8, wherein a VbyOne interface is disposed on the FPGA chip, wherein the display linear light signal is output to a display screen for display through the VbyOne interface.
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| CN202210622112.5A CN114979541A (en) | 2022-06-02 | 2022-06-02 | Video display system |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115914717A (en) * | 2022-11-03 | 2023-04-04 | 深圳创维－Rgb电子有限公司 | CUVA HDR video playing method, device and equipment and readable storage medium |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115914717A (en) * | 2022-11-03 | 2023-04-04 | 深圳创维－Rgb电子有限公司 | CUVA HDR video playing method, device and equipment and readable storage medium |
| CN115914717B (en) * | 2022-11-03 | 2024-09-17 | 深圳创维－Rgb电子有限公司 | CUVA HDR video playing method, CUVA HDR video playing device, CUVA HDR video playing equipment and readable storage medium |
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