CN114959606A - Preparation method of silicon through hole seed layer and preparation method of chip - Google Patents
Preparation method of silicon through hole seed layer and preparation method of chip Download PDFInfo
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- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
- C23C14/22—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the process of coating
- C23C14/34—Sputtering
- C23C14/35—Sputtering by application of a magnetic field, e.g. magnetron sputtering
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- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
- C23C14/06—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the coating material
- C23C14/14—Metallic material, boron or silicon
- C23C14/16—Metallic material, boron or silicon on metallic substrates or on substrates of boron or silicon
- C23C14/165—Metallic material, boron or silicon on metallic substrates or on substrates of boron or silicon by cathodic sputtering
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- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
- C23C14/22—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the process of coating
- C23C14/54—Controlling or regulating the coating process
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
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Abstract
The application discloses a preparation method of a silicon through hole seed layer and a preparation method of a chip, relates to the technical field of chips, and can improve the coverage rate of a film of the seed layer on the side wall of a silicon through hole so as to improve the quality and efficiency of subsequent TSV filling. A preparation method of a silicon through hole seed layer comprises the following steps: arranging a silicon through hole on a silicon substrate; seed layers are arranged on the surface of the silicon substrate and in the silicon through hole; and adjusting the temperature of a base bearing the silicon substrate and adjusting an alternating current electric field of a reaction chamber in which the silicon substrate is positioned in the process of arranging seed layers on the surface of the silicon substrate and in the silicon through hole.
Description
Technical Field
The application relates to the technical field of chips, in particular to a preparation method of a silicon through hole seed layer and a preparation method of a chip.
Background
At present, usually, an electroplating method is adopted to fill materials into the TSV (through silicon via), a seed layer needs to be prepared, and the film quality of the seed layer directly affects the effective performance of subsequent electroplating. The film of the seed layer has a certain thickness to ensure the normal operation of the electroplating filling process, however, the problem of side wall scallop effect can be caused by the Bosch (etching) type process of the TSV, namely, the side wall of the TSV is in an uneven scallop shape, and certain influence is caused on the subsequent process.
Therefore, in the process of preparing the thin film of the seed layer, the coverage rate of the thin film of the seed layer on the sidewall of the TSV is easily caused to be low, and the quality and the efficiency of the subsequent TSV filling are reduced.
Disclosure of Invention
The embodiment of the application provides a preparation method of a silicon through hole seed layer and a preparation method of a chip, which can improve the coverage rate of a film of the seed layer on the side wall of a TSV and further improve the quality and efficiency of subsequent TSV filling.
In a first aspect of the embodiments of the present application, a method for preparing a seed layer of a through silicon via is provided, including:
arranging a silicon through hole on a silicon substrate;
seed layers are arranged on the surface of the silicon substrate and in the silicon through hole;
and adjusting the temperature of a base bearing the silicon substrate and adjusting an alternating current electric field of a reaction chamber in which the silicon substrate is positioned in the process of arranging the seed layer on the surface of the silicon substrate and in the silicon through hole.
In some embodiments, the adjusting the temperature of the susceptor bearing the silicon substrate during the disposing of the seed layer on the surface of the silicon substrate and in the through-silicon-via includes:
and adjusting the temperature of the pedestal bearing the silicon substrate to be below room temperature in the process of arranging the seed layer on the surface of the silicon substrate and in the silicon through hole.
In some embodiments, the adjusting the temperature of the susceptor bearing the silicon substrate to below room temperature during the disposing of the seed layer on the surface of the silicon substrate and in the through silicon via includes:
and adjusting the temperature of the pedestal bearing the silicon substrate to-25 ℃ in the process of arranging the seed layer on the surface of the silicon substrate and in the silicon through hole.
In some embodiments, the seed layer is disposed on the surface of the silicon substrate and within the through silicon via using a magnetron sputtering process.
In some embodiments, the adjusting the alternating current electric field of the reaction chamber in which the silicon substrate is located during the process of disposing the seed layer on the surface of the silicon substrate and in the through-silicon-via includes:
and adjusting the alternating voltage applied in the magnetron sputtering chamber in the process of arranging the seed layer on the surface of the silicon substrate and in the silicon through hole.
In some embodiments, the adjusting the ac voltage applied within the magnetron sputtering chamber comprises:
increasing the alternating voltage applied in the magnetron sputtering chamber.
In some embodiments, the material of the seed layer comprises copper.
In some embodiments, the increasing the alternating voltage applied within the magnetron sputtering chamber comprises:
and increasing the alternating voltage applied in the magnetron sputtering chamber to control copper particles to deposit on the surface of the silicon substrate and the bottom of the through silicon via along the direction vertical to the silicon substrate, and controlling part of argon ions to bombard the copper film at the bottom of the through silicon via, so that the bombarded and sputtered copper is deposited on the side wall of the through silicon via.
In some embodiments, before disposing a seed layer on the surface of the silicon substrate and in the through silicon via, further comprising:
arranging insulating layers on the surface of the silicon substrate and in the silicon through hole;
and arranging an adhesion layer on the surface of the silicon substrate and in the through silicon via, wherein the insulation layer is arranged between the silicon substrate and the adhesion layer.
In a second aspect of the embodiments of the present application, a method for manufacturing a chip is provided, including:
preparing a seed layer on a silicon substrate by using the preparation method of the through silicon via seed layer according to the first aspect;
and arranging a filling layer in the silicon through hole by utilizing the seed layer.
According to the preparation method of the silicon through hole seed layer and the preparation method of the chip, provided by the embodiment of the application, in the process of arranging the seed layer on the surface of the silicon substrate and in the silicon through hole, the temperature of the base bearing the silicon substrate is adjusted, the heat dissipation performance at the bottom of the silicon through hole can be adjusted, the agglomeration and discontinuity of the seed layer at the bottom of the silicon through hole can be avoided, the film quality of the seed layer can be improved, and the preparation speed and the film quality of the subsequent filling layer are further improved. In the process of setting seed layers on the surface of the silicon substrate and in the silicon through hole, the alternating current electric field of a reaction chamber where the silicon substrate is located is adjusted, more seed layer material particles can be deposited at the bottom of the silicon through hole along the direction perpendicular to the silicon substrate, the film thickness of the seed layer at the bottom of the silicon through hole is thickened, more plasma bombards the seed layer at the bottom of the silicon through hole, bombarded seed layer material is sputtered onto the side wall of the silicon through hole, the thickness of the seed layer on the side wall of the silicon through hole is increased, the coverage rate of the seed layer on the side wall of the silicon through hole is improved, and the preparation speed and the film quality of a subsequent filling layer are improved.
Drawings
Fig. 1 is a schematic flow chart of a method for manufacturing a seed layer of a through silicon via according to an embodiment of the present disclosure;
fig. 2 is a schematic scanning electron microscope view of a cross section of a seed layer on a surface of a silicon substrate according to an embodiment of the present disclosure;
fig. 3 is a schematic scanning electron microscope view of a cross section of a seed layer on a sidewall of a through silicon via provided in an embodiment of the present application;
fig. 4 is a schematic scanning electron microscope view of a cross section of a seed layer at the bottom of a through silicon via provided in an embodiment of the present application;
fig. 5 is a schematic flowchart of a method for manufacturing a chip according to an embodiment of the present disclosure.
Detailed Description
In order to better understand the technical solutions provided by the embodiments of the present specification, the technical solutions of the embodiments of the present specification are described in detail below with reference to the accompanying drawings and specific embodiments, and it should be understood that the specific features of the embodiments and examples of the present specification are detailed descriptions of the technical solutions of the embodiments of the present specification, and are not limitations on the technical solutions of the embodiments, and the technical features of the embodiments and examples of the present specification may be combined with each other without conflict.
In this document, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element. The term "two or more" includes the case of two or more.
At present, usually, a plating method is adopted to fill the TSV with the material, a seed layer needs to be prepared, and the film quality of the seed layer directly affects the effective performance of the subsequent plating. The film of the seed layer has a certain thickness to ensure the normal operation of the electroplating filling process, however, the problem of side wall scallop effect can be caused by the Bosch type process of the TSV, namely, the side wall of the TSV is in an uneven scallop shape, and certain influence is caused on the subsequent process. Therefore, in the process of preparing the film of the seed layer, the coverage rate of the film of the seed layer on the sidewall of the TSV is easily caused to be low, and the quality and efficiency of the subsequent TSV filling are reduced.
In view of this, embodiments of the present application provide a method for manufacturing a seed layer of a through silicon via and a method for manufacturing a chip, which can improve a coverage rate of a thin film of the seed layer on a sidewall of a TSV, thereby improving quality and efficiency of subsequent TSV filling.
In a first aspect of the embodiments of the present application, a method for preparing a seed layer of a through silicon via is provided, and fig. 1 is a schematic flow chart of the method for preparing a seed layer of a through silicon via provided in the embodiments of the present application. As shown in fig. 1, the method for preparing a seed layer of a through silicon via provided in the embodiment of the present application includes:
s100: a through-silicon via is provided on a silicon substrate. The silicon substrate may be a single crystal silicon substrate, and may be a silicon substrate in a wafer, a die, or a chip, and embodiments of the present application are not limited in particular. The through-silicon vias may be obtained by etching a silicon substrate, and the number of the through-silicon vias is not particularly limited. The through-silicon via may or may not penetrate through the silicon substrate, and the embodiments of the present application are not particularly limited.
S200: seed layers are arranged on the surface of the silicon substrate and the silicon through hole; and adjusting the temperature of a base bearing the silicon substrate and the alternating current electric field of a reaction chamber in which the silicon substrate is positioned in the process of arranging the seed layer on the surface of the silicon substrate and in the silicon through hole. Adjusting the temperature of the susceptor bearing the silicon substrate and adjusting the alternating current electric field of the reaction chamber is the adjustment and optimization of the process conditions for setting the seed layer. In the process of preparing a seed layer on a silicon substrate, the silicon substrate is required to be placed on a pedestal, the pedestal is used for bearing and fixing the silicon substrate, and the seed layer is arranged on the surface of one side of the silicon substrate away from the pedestal and in a silicon through hole. The seed layer may be disposed by a magnetron sputtering process, or may be disposed by an atomic layer deposition process, and the embodiment of the present application is not particularly limited.
It should be noted that, the through-silicon via obtained by the TSV process usually has an uneven stepped or scallop-shaped sidewall, and in the process of preparing the seed layer, the coverage thickness of the seed layer on the sidewall of the through-silicon via is relatively thin, that is, the coverage rate of the seed layer on the sidewall of the through-silicon via is relatively low, and the coverage rate of the seed layer on the sidewall of the through-silicon via is the ratio of the thickness of the seed layer on the sidewall of the through-silicon via to the thickness of the seed layer on the surface of the through-silicon via. The seed layer on the side wall of the through silicon via has low coverage rate, so that the forming rate of the filling layer in the through silicon via is poor and the film quality of the filling layer is poor in the subsequent process of filling the through silicon via by using an electroplating process.
In order to solve the above problems, according to the preparation method of the seed layer of the through silicon via provided by the embodiment of the application, the temperature of the pedestal bearing the silicon substrate is adjusted in the process of arranging the seed layer on the surface of the silicon substrate and in the through silicon via, so that the heat dissipation performance at the bottom of the through silicon via can be adjusted, the agglomeration and discontinuity of the seed layer at the bottom of the through silicon via can be avoided, the film quality of the seed layer can be improved, and the preparation speed and the film quality of the subsequent filling layer can be further improved. In the process of setting seed layers on the surface of the silicon substrate and in the silicon through hole, the alternating current electric field of a reaction chamber where the silicon substrate is located is adjusted, more seed layer material particles can be deposited at the bottom of the silicon through hole along the direction perpendicular to the silicon substrate, the film thickness of the seed layer at the bottom of the silicon through hole is thickened, more plasma bombards the seed layer at the bottom of the silicon through hole, bombarded seed layer material is sputtered onto the side wall of the silicon through hole, the thickness of the seed layer on the side wall of the silicon through hole is increased, the coverage rate of the seed layer on the side wall of the silicon through hole is improved, and the preparation speed and the film quality of a subsequent filling layer are improved.
In some embodiments, the material of the seed layer includes copper, which may be referred to as a copper seed layer, and then a copper electroplating process may be further used, and the filling layer disposed in the through-silicon via is a copper filling layer, which has a good electrical conductivity and may realize electrical connection of lines through the copper filling layer. The seed layer may further include other metal materials or conductive materials, and the material of the corresponding filling layer corresponds to the material of the seed layer, which is not specifically limited in this embodiment of the application.
In some embodiments, a seed layer is disposed on the surface of the silicon substrate and within the through silicon via using a magnetron sputtering process. The seed layer can be formed by adopting a PVD (magnetron sputtering) process, the magnetron sputtering process needs to control plasma to bombard a target material by using an electric field, and particles sputtered from the bombarded target material are deposited on a substrate material to form a required film. Illustratively, in the process of arranging the copper seed layer on the surface of the silicon substrate and in the through-silicon via, the argon plasma can be used for bombarding the copper target, and bombarded copper atoms are sputtered from the target to deposit on the surface of the silicon substrate and in the through-silicon via to form the copper seed layer, so that the magnetron sputtering process is mature.
In some embodiments, before step S200, the method may further include:
and arranging an insulating layer on the surface of the silicon substrate and in the silicon through hole. Since the silicon substrate is a single crystal silicon having semiconductor properties and a certain conductivity, an insulating layer for insulating the silicon substrate and the seed layer is required to be prepared before preparing the seed layer. Illustratively, the insulating layer can comprise silicon oxide, the silicon substrate can be directly subjected to oxidation treatment, a layer of silicon oxide film is formed on the surface of the silicon substrate and the inner wall of the through silicon via, the silicon oxide film can be used as the insulating layer, the process is easy to implement, and other insulating materials are not needed. The insulating layer may be made of other insulating materials such as silicon nitride, and the embodiment of the present application is not particularly limited.
And arranging an adhesion layer on the surface of the silicon substrate and in the through silicon via, wherein the insulation layer is arranged between the silicon substrate and the adhesion layer. The adhesion layer can be arranged after the insulating layer is arranged, the adhesion between the seed layer and the insulating layer can be enhanced by the adhesion layer, and the adhesion of the film layer is poor because the seed layer is usually a conductive material and the insulating layer is an insulating material. Exemplary adhesion layers may include titanium and/or titanium nitride, and embodiments of the present application are not particularly limited. The adhesion layer can also be used as a barrier layer at the same time, and can block copper diffusion of the copper seed layer.
In some embodiments, adjusting the temperature of a susceptor bearing a silicon substrate during the process of providing a seed layer on the surface of the silicon substrate and in the through-silicon via comprises:
and in the process of arranging the seed layer on the surface of the silicon substrate and in the silicon through hole, regulating the temperature of the pedestal bearing the silicon substrate to be lower than the room temperature.
Generally, in the process of setting the seed layer, the temperature of the base bearing the silicon substrate is room temperature, which can be 25 ℃, the temperature of the base is adjusted to be below the room temperature, that is, the temperature of the base is adjusted to be lower than the room temperature, the low-temperature base can accelerate the heat dissipation of the bottom of the silicon through hole, thereby not only avoiding the agglomeration of copper and the appearance of discontinuous films, but also ensuring the uniformity of the copper films by fine copper grains.
In some embodiments, adjusting the temperature of the susceptor bearing the silicon substrate to below room temperature during the process of providing the seed layer on the surface of the silicon substrate and in the through silicon via includes:
and adjusting the temperature of the pedestal bearing the silicon substrate to-25 ℃ in the process of arranging the seed layer on the surface of the silicon substrate and in the silicon through hole.
The deposition of the copper seed layer also needs to be paid attention to avoid copper agglomeration, and the current-carrying performance of a discontinuous copper film is greatly reduced during electroplating, so that the base of the wafer silicon substrate needs to have good heat dissipation performance. The deposition of the film of the copper seed layer is generally carried out at the base normal temperature, the temperature of the base in the seed layer setting is set to be-25 ℃, the agglomeration of copper and the appearance of discontinuous films are avoided, and the uniformity of the films is ensured by fine grains.
In some embodiments, adjusting an ac electric field of a reaction chamber in which the silicon substrate is located during a process of providing a seed layer on a surface of the silicon substrate and in the through-silicon via includes:
and adjusting the alternating voltage applied in the magnetron sputtering chamber in the process of arranging the seed layer on the surface of the silicon substrate and in the silicon through hole. The alternating voltage in the magnetron sputtering chamber can control the movement direction of copper particles bombarded and sputtered by argon ions in the magnetron sputtering chamber, and the electric field intensity applied to the copper particles can be adjusted by adjusting the magnitude of the alternating voltage, so that the copper particles can move along the direction vertical to the silicon substrate to be deposited on the surface of the silicon substrate and the bottom of the through silicon via. The alternating voltage can also pull a part of argon ions to bombard the copper film at the bottom of the through silicon via so that copper particles are sputtered onto the side wall of the through silicon via again, the thickness of the copper film deposited on the side wall of the through silicon via is increased, namely the thickness of the seed layer on the side wall of the through silicon via is increased, and the coverage rate of the seed layer on the side wall of the through silicon via is further improved.
In some embodiments, the adjusting the ac voltage applied within the magnetron sputtering chamber comprises:
and increasing the alternating voltage applied in the magnetron sputtering chamber. The alternating voltage applied in the magnetron sputtering chamber can be improved according to the film layer parameters of the seed layer and the technological capability of the magnetron sputtering equipment.
And increasing the alternating voltage applied in the magnetron sputtering chamber, controlling copper particles to be deposited on the surface of the silicon substrate and the bottom of the through silicon via along the direction vertical to the silicon substrate, and controlling part of argon ions to bombard the copper film at the bottom of the through silicon via so that the bombarded and sputtered copper is deposited on the side wall of the through silicon via.
Illustratively, table 1 sets some of the process parameters for the seed layer using a magnetron sputtering process.
| Step Name | Chuck | Wait | Ignite | Dep |
| Time(s) | 1 | 8 | 1 | 7 |
| DC power(W) | 0 | 0 | 2000 | 38000 |
| AC bias(W) | 0 | 0 | 0 | 600 |
| Herter Tem(℃) | -25 | -25 | -25 | -25 |
| Ar Gas(sccm) | 0 | 140 | 140 | 0 |
| Herter Gas(sccm) | 0 | 8 | 4 | 4 |
TABLE 1
As shown in table 1, the names Step Name of the operation steps of the device in the magnetron sputtering process are respectively the pedestal vacuum pumping Chuck, Wait ready Wait, glow ignition and film deposition Dep, and the corresponding process parameters respectively have duration Time in seconds; direct current energy DC power, unit is watt W; AC power AC bias in watts W; the base temperature Herter Tem in units of deg.C; argon flow Ar Gas in sccm (volume flow units, standard conditions ml per serving); the base blows air Herter Gas, and the base blows air can be used for carrying out the temperature control of base, and the bigger to the base air blow flow, then the lower is the base temperature. The susceptor vacuum suction Chuck can fix the silicon substrate on the susceptor, and the silicon substrate is prevented from shifting in the deposition process of the seed layer. The process of waiting for ready Wait can be used for cooling the base, and the glow ignition can be performed until the temperature of the base reaches the preset temperature, and the glow ignition can be understood as ignition operation. The direct current energy DC power can change argon gas into argon plasma, and controls argon ions to bombard the target material. The thin film deposition Dep can be performed by argon ion bombardment of a target material and seed layer deposition. Usually, the temperature of the base in the prior art is 25 ℃, the temperature of the base can be adjusted to-25 ℃ in the embodiment of the application, and the heat dissipation capability of the bottom of the through silicon via can be enhanced. In the process of thin film Dep deposition, the AC bias in the prior art may be 300W, and the AC bias in the embodiment of the present application may be adjusted to 600W, which may be adjusted according to the actual process. The AC bias can more accurately control the directionality of ionized copper and ensure that the ionized copper is vertically deposited on the surface of the silicon substrate as far as possible, so that the deposition rate of the bottom in the TSV is ensured, meanwhile, the AC bias can also pull a part of argon ions to bombard the bottom deposited copper film in the TSV and back-sputter the copper film on the side wall, the step coverage rate on the side wall is improved, and a certain back-sputtering rate is kept while deposition is carried out in the process. The increased AC bias enhances the direction of ionized copper to be more concentrated, ensuring as much as possible vertical deposition to the surface of the silicon substrate, thus ensuring the deposition rate of the bottom inside the TSV and improving the step coverage on the sidewall.
Exemplarily, fig. 2 is a schematic scanning electron microscope view of a cross section of a seed layer on a surface of a silicon substrate according to an embodiment of the present application. As shown in FIG. 2, 5.0kV indicated by the lower frame is the accelerating voltage of the SEM, 7.7mm is the working distance of the lens, i.e. the distance from the lens to the sample, 40.0k is the magnification of the lens, SE (U) represents that the imaging mode is a secondary electron image, and 1.0 μm is the dimension represented by each grid of the scale bar. As shown in fig. 2; the thickness of the seed layer on the surface of the silicon substrate obtained by the preparation method of the silicon through hole seed layer provided by the embodiment of the application is 835nm, the thickness of the adhesion layer is 88.1nm, and the thickness of the insulation layer is 510 nm.
Exemplarily, fig. 3 is a schematic scanning electron microscope view of a cross section of a seed layer on a sidewall of a through silicon via provided in an embodiment of the present application. As shown in fig. 3, the acceleration voltage of the scanning electron microscope is 10.0kV, the magnification is 100k, the size of each grid of the scale bar is 500nm, the numerical values of the two points of the thickness of the seed layer on the sidewall of the through silicon via obtained by the method for preparing the seed layer of the through silicon via provided in the embodiment of the present application are 32.2nm and 25.3nm, respectively, and the average value is 28.75 nm.
Fig. 4 is a schematic scanning electron microscope view of a cross section of a seed layer at the bottom of a through silicon via provided in an embodiment of the present application. As shown in fig. 4, the thickness of the seed layer at the bottom of the through silicon via obtained by using the method for preparing the seed layer of the through silicon via provided by the embodiment of the present application is 72.4 nm.
Exemplarily, table 2 shows test data of the seed layer prepared by the method for preparing a seed layer of a through silicon via provided in the embodiment of the present application.
| Location | Film | SEM Thickness | Step Coverage |
| Top | Cu | 835nm | 1 |
| Sidewall | Cu | 28.75nm | 3.40％ |
| Bottom | Cu | 72.4nm | 8.90％ |
TABLE 2
As shown in table 2, the Film layer Film of the seed layer is Cu, the test positions of the seed layer are respectively a silicon substrate surface Top, a silicon through hole Sidewall and a silicon through hole Bottom, and the test Film Thickness SEM Thickness and Coverage rate Step Coverage data of the scanning electron microscope corresponding to the test positions are respectively shown in table 2, as can be seen from table 2, the Coverage rate of the seed layer of the silicon through hole Sidewall can reach 3.40%, the Coverage rate of the Bottom can reach 8.90%, and the Coverage rate of the seed layer of the silicon through hole Sidewall in the prior art is approximately in the range of 1% -1.5%.
It should be noted that the method for preparing the seed layer of the through silicon via provided by the embodiment of the present application can be better suitable for preparing the seed layer of the through silicon via with a high aspect ratio.
According to the preparation method of the through-silicon-via seed layer, due to the existence of the scallop effect problem on the side wall of the Bosch type process, certain influence is generated on the subsequent process, the unevenness is about dozens of nanometers, and the scallop effect can be eliminated only when the side wall of the deposited film of the seed layer covers dozens of nanometers. In addition, the deposition thickness of the side wall and the bottom of the through silicon via can be ensured only by increasing the deposition time, but the surface film is quite thick due to the high surface deposition rate, which is not beneficial to the subsequent grinding process.
The preparation method of the through-silicon-via seed layer provided by the embodiment of the application mainly publishes the temperature control parameters of DCpower, ACbias and a base, and the DCpower is used as a main power source for sputtering and controls argon ions to bombard a target material. Meanwhile, copper is easier to ionize, a self-ionized plasma is most stable, the ionization rate is also highest, the AC bias can more accurately control the directionality of the ionized copper and ensure that the ionized copper is vertically deposited on the surface of the silicon substrate as far as possible, so that the deposition rate of the bottom in the TSV is ensured, meanwhile, the AC bias can also pull a part of argon ions to bombard the bottom deposited copper film in the TSV and splash back to the side wall, the step coverage rate on the side wall is improved, and a certain sputtering rate is maintained while deposition is performed in the process. The coverage rate of the weakest part of the side wall of the TSV can reach more than 3%, the follow-up electroplating process is completely guaranteed, and the base controls the temperature to keep the temperature of the silicon substrate at about-25 ℃, so that the growth of copper is carried out at low temperature in the deposition process, a microstructure with fine grains can be obtained, and the uniformity of the film is guaranteed.
In a second aspect of the embodiments of the present application, a method for manufacturing a chip is provided, and fig. 5 is a schematic flowchart of the method for manufacturing a chip provided in the embodiments of the present application. As shown in fig. 5, the method for manufacturing a chip provided in the embodiment of the present application includes:
s300: preparing a seed layer on a silicon substrate by using the preparation method of the through silicon via seed layer according to the first aspect;
s400: and utilizing the seed layer to arrange the filling layer in the silicon through hole. Illustratively, where the seed layer includes copper, the fill layer is a copper fill material. The filling layer may be used as a connection structure of a line, and the embodiment of the present application is not particularly limited.
According to the preparation method of the chip, the temperature of the base bearing the silicon substrate is adjusted in the process of arranging the seed layer on the surface of the silicon substrate and in the silicon through hole, the heat dissipation performance at the bottom of the silicon through hole can be adjusted, the agglomeration and discontinuity of the seed layer at the bottom of the silicon through hole can be avoided, the membranous of the seed layer can be improved, and the speed and membranous of subsequent filling layer preparation are further improved. In the process of setting seed layers on the surface of the silicon substrate and in the silicon through hole, the alternating current electric field of a reaction chamber where the silicon substrate is located is adjusted, more seed layer material particles can be deposited at the bottom of the silicon through hole along the direction perpendicular to the silicon substrate, the film thickness of the seed layer at the bottom of the silicon through hole is thickened, more plasma bombards the seed layer at the bottom of the silicon through hole, bombarded seed layer material is sputtered onto the side wall of the silicon through hole, the thickness of the seed layer on the side wall of the silicon through hole is increased, the coverage rate of the seed layer on the side wall of the silicon through hole is improved, and the preparation speed and the film quality of a subsequent filling layer are improved.
It should be noted that, in the foregoing embodiments, the descriptions of the respective embodiments have respective emphasis, and reference may be made to relevant descriptions of other embodiments for parts that are not described in detail in a certain embodiment.
As will be appreciated by one skilled in the art, embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-readable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-readable program code embodied therein.
The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
The embodiment of the application further provides a computer program product, which includes computer software instructions, and when the computer software instructions are run on a processing device, the processing device is enabled to execute the method for preparing the through silicon via seed layer and the flow of the method for preparing the chip.
The computer program product includes one or more computer instructions. The procedures or functions according to the embodiments of the present application are all or partially generated when the computer program instructions are loaded and executed on a computer. The computer may be a general purpose computer, a special purpose computer, a network of computers, or other programmable device. The computer instructions may be stored on a computer readable storage medium or transmitted from one computer readable storage medium to another, for example, the computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, Digital Subscriber Line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. A computer-readable storage medium may be any available medium that a computer can store or a data storage device, such as a server, a data center, etc., that is integrated with one or more available media. The usable medium may be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., Solid State Disk (SSD)), among others.
It is clear to those skilled in the art that, for convenience and brevity of description, the specific working processes of the above-described systems, apparatuses and units may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.
In the several embodiments provided in the present application, it should be understood that the disclosed apparatus, device and method may be implemented in other manners. For example, the above-described apparatus embodiments are merely illustrative, and for example, a division of a unit is merely a logical division, and an actual implementation may have another division, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.
Units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In addition, functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.
The integrated unit, if implemented in the form of a software functional unit and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solutions of the present application, which are essential or part of the technical solutions contributing to the prior art, or all or part of the technical solutions, may be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods of the embodiments of the present application. And the aforementioned storage medium includes: various media capable of storing program codes, such as a usb disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk, or an optical disk.
The above embodiments are only used to illustrate the technical solutions of the present application, and not to limit the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions in the embodiments of the present application.
While preferred embodiments of the present specification have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all changes and modifications that fall within the scope of the specification.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present specification without departing from the spirit and scope of the specification. Thus, if such modifications and variations of the present specification fall within the scope of the claims of the present specification and their equivalents, the specification is intended to include such modifications and variations.
Claims (10)
1. A preparation method of a silicon through hole seed layer is characterized by comprising the following steps:
arranging a silicon through hole on a silicon substrate;
seed layers are arranged on the surface of the silicon substrate and in the silicon through hole;
and adjusting the temperature of a base bearing the silicon substrate and adjusting an alternating current electric field of a reaction chamber in which the silicon substrate is positioned in the process of arranging the seed layer on the surface of the silicon substrate and in the silicon through hole.
2. The method of claim 1, wherein the adjusting the temperature of a susceptor bearing the silicon substrate during the process of disposing the seed layer on the surface of the silicon substrate and in the through-silicon via comprises:
and adjusting the temperature of the pedestal bearing the silicon substrate to be below room temperature in the process of arranging the seed layer on the surface of the silicon substrate and in the silicon through hole.
3. The method of claim 2, wherein the adjusting the temperature of the susceptor bearing the silicon substrate to below room temperature during the process of disposing the seed layer on the surface of the silicon substrate and in the through-silicon via comprises:
and adjusting the temperature of the pedestal bearing the silicon substrate to-25 ℃ in the process of arranging the seed layer on the surface of the silicon substrate and in the silicon through hole.
4. The method for preparing a seed layer of a through silicon via according to claim 1, wherein the seed layer is disposed on the surface of the silicon substrate and in the through silicon via by a magnetron sputtering process.
5. The method for preparing the seed layer of the through silicon via according to claim 4, wherein adjusting the alternating current electric field of the reaction chamber in which the silicon substrate is located during the process of arranging the seed layer on the surface of the silicon substrate and in the through silicon via comprises:
and adjusting the alternating voltage applied in the magnetron sputtering chamber in the process of arranging the seed layer on the surface of the silicon substrate and in the silicon through hole.
6. The method for preparing a seed layer of a through silicon via according to claim 5, wherein the adjusting the AC voltage applied to the magnetron sputtering chamber comprises:
and increasing the alternating voltage applied in the magnetron sputtering chamber.
7. The method as claimed in claim 6, wherein the seed layer comprises copper.
8. The method for preparing a seed layer of a through silicon via according to claim 7, wherein the increasing the alternating voltage applied to the magnetron sputtering chamber comprises:
and increasing the alternating voltage applied in the magnetron sputtering chamber to control copper particles to deposit on the surface of the silicon substrate and the bottom of the through silicon via along the direction vertical to the silicon substrate, and controlling part of argon ions to bombard the copper film at the bottom of the through silicon via, so that the bombarded and sputtered copper is deposited on the side wall of the through silicon via.
9. The method for preparing a seed layer for a through silicon via of claim 1, wherein before the seed layer is disposed on the surface of the silicon substrate and in the through silicon via, the method further comprises:
arranging insulating layers on the surface of the silicon substrate and in the silicon through hole;
and arranging an adhesion layer on the surface of the silicon substrate and in the through silicon via, wherein the insulation layer is arranged between the silicon substrate and the adhesion layer.
10. A method for manufacturing a chip, comprising:
preparing a seed layer on the silicon substrate by using the preparation method of the through silicon via seed layer as claimed in any one of claims 1 to 9;
and arranging a filling layer in the silicon through hole by utilizing the seed layer.
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