CN114880389B - Data conversion method, system and device - Google Patents
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Abstract
The application discloses a data conversion method, a system and a device, which relate to the field of data conversion and are used for converting serial data into parallel data, wherein in the scheme, data bits of the serial data are adjusted when bitslip signals are received so as to align boundaries of parallel data in the serial data with the boundaries of a parallel data clock; and then fine-tuning the sampling position of the sampling clock to the optimal sampling point of each data bit of the serial data after the alignment processing so as to sample according to the sequence of the serial data after the alignment processing and convert the serial data into parallel data. Therefore, when serial data is converted into parallel data, the application not only ensures that the boundary of each parallel data in the serial data is aligned with the boundary of a parallel data clock so as to ensure the accuracy of data conversion, but also ensures that the sampling position of the serial data is the optimal sampling point when the serial data is sampled, and further ensures the accuracy and stability of data sampling.
Description
Technical Field
The present invention relates to the field of data conversion, and in particular, to a data conversion method, system and device.
Background
With the advent of high frame rate digital cameras, the data size of video images is increasing, which puts higher demands on various technical indexes of data acquisition, transmission and processing. The conventional parallel data transmission method cannot meet the requirement of complex and high-speed image data transmission. The advent of high-speed serial interfaces provides technical support for large data volumes and high-speed image transmission. However, when serial data is converted into parallel data, time delay and difference caused by hardware wiring design affect the stability of data sampling.
Disclosure of Invention
The invention aims to provide a data conversion method, a system and a device, which not only ensure that the boundary of each parallel data in serial data is aligned with the boundary of a parallel data clock when serial data is converted into parallel data so as to ensure the accuracy of data conversion, but also ensure that the sampling position of the serial data is the optimal sampling point when the serial data is sampled, and further ensure the accuracy and stability of data sampling.
In order to solve the above technical problems, the present invention provides a data conversion method, which is applied to ISERDESE of a data conversion device, and the method includes:
adjusting data bits of serial data when bitslip signals are received so that boundaries of parallel data in the serial data are aligned with parallel data clock boundaries;
And fine-adjusting the sampling position of the sampling clock to the optimal sampling point of each data bit of the serial data after the alignment processing so as to sample according to the sequence of the serial data after the alignment processing, and converting the serial data into parallel data.
Preferably, the serial data includes a plurality of rows of parallel data, a plurality of the parallel data are one row, and a synchronization code is set before the first bit data of each row of the parallel data or before the first bit data of each row of the parallel data and after the last bit data of each row of the parallel data; the data conversion device also comprises a Bitslip _G module;
Before adjusting the data bits of the serial data to align the boundaries of each parallel data in the serial data with the parallel data clock boundaries when receiving bitslip signals, the method further comprises:
Sampling the serial data according to the sequence of the received serial data so as to convert the serial data into first parallel data to be processed;
transmitting the first parallel data to be processed to the Bitslip _g module;
the Bitslip _g module is configured to search for the first parallel data to be processed in one virtual frame synchronization signal, and if the number of synchronization codes searched in one virtual frame synchronization signal is not greater than a first preset number, output the bitslip signal.
Preferably, the data conversion device further comprises a delay_value module and an IDELAY module;
The Bitslip _g module is further configured to generate a coarse tuning delay adjustment signal according to a preset time interval and a preset coarse tuning adjustment step when the number of synchronization codes retrieved in one virtual frame synchronization signal is not greater than a first preset number; the step length of the preset coarse adjustment step length is smaller than the length of one clock cycle of the serial data;
the delay_value module is used for generating a coarse adjustment signal based on the coarse adjustment Delay adjustment signal;
The IDELAY module is used for converting the coarse adjustment signal into a coarse adjustment instruction;
adjusting data bits of serial data upon receipt of bitslip signals to align boundaries of respective parallel data in the serial data with parallel data clock boundaries, comprising:
And adjusting data bits of the serial data when the bitslip signals and the coarse adjustment instruction are received, and performing coarse adjustment on sampling positions of the sampling clock so as to align boundaries of parallel data in the serial data with the boundaries of the parallel data clock.
Preferably, adjusting the data bits of the serial data and coarse adjusting the sampling position of the sampling clock when receiving the bitslip signal and the coarse adjusting instruction to align the boundary of each parallel data in the serial data with the boundary of the parallel data clock includes:
S201: shifting the phase of the data bits of the serial data one clock cycle forward or one clock cycle backward upon receipt of the bitslip signal;
s202: setting the rough adjustment instruction as a current rough adjustment instruction, and setting the preset rough adjustment step length as a current rough adjustment step length;
s204: performing first forward adjustment on the sampling position of the sampling clock based on the current coarse adjustment instruction;
S205: sampling the serial data after the data shift based on the sampling clock subjected to the first forward adjustment to generate current parallel data to be processed, enabling the Bitslip _G module to search the current parallel data to be processed in one virtual frame synchronizing signal, and if the number of the synchronizing codes searched in one virtual frame synchronizing signal is not greater than the first preset number, entering step S206; if yes, go to step S212;
S206: performing two-time reverse adjustment on the sampling position of the sampling clock based on the current coarse adjustment instruction;
S207: sampling the serial data after the data shift based on the sampling clock subjected to the two-time reverse adjustment, updating the current parallel data to be processed, enabling the Bitslip _G module to search the current parallel data to be processed in one virtual frame synchronizing signal, and if the number of the synchronous codes searched in one virtual frame synchronizing signal is not greater than the first preset number, entering step S208; if yes, go to step S212;
S208: performing second forward adjustment on the sampling position of the sampling clock based on the current coarse adjustment instruction;
s209: adding a preset coarse adjustment minimum unit to the current coarse adjustment step length, judging whether the current coarse adjustment step length is larger than a maximum adjustment step length, and if not, entering step S210; if yes, go to step S211;
s210: the Bitslip _G module updates the coarse adjustment delay adjustment signal according to the preset time interval and the current coarse adjustment step length; the delay_value module is enabled to update the current coarse adjustment signal based on the updated coarse adjustment Delay adjustment signal, and the IDELAY module is enabled to update the current coarse adjustment instruction based on the updated current coarse adjustment signal; returning to step S204;
s211: the Bitslip _g module outputs the bitslip signal and returns to step S201;
S212: and aligning the boundary of each parallel data in the serial data with the boundary of the parallel data clock, and entering the step of finely adjusting the sampling position of the sampling clock to the optimal sampling point of each data bit of the serial data after the alignment processing.
Preferably, fine-tuning the sampling position of the sampling clock to an optimal sampling point of each data bit of the serial data after the alignment processing to sample in the order of the serial data after the alignment processing, converting the serial data into parallel data includes:
Sampling a second preset number of times according to the sequence of the serial data after the alignment processing, outputting a second preset number of second parallel data to be processed, so that the Bitslip _G module searches the second preset number of second parallel data to be processed in the second preset number of virtual frame synchronizing signals respectively, and if the number of the synchronizing codes searched in the second preset number of virtual frame synchronizing signals is not equal to or larger than the second preset number, generating a fine-tuning delay adjusting signal according to the preset time interval and a preset fine-tuning adjusting period; the preset fine adjustment minimum unit of the fine adjustment period is smaller than the preset coarse adjustment minimum unit; and causing the Delay Value module to generate the fine adjustment signal based on the fine adjustment Delay adjustment signal; causing the IDELAY module to convert the fine-tuning signal into the fine-tuning instruction;
and fine-adjusting the sampling position of the sampling clock based on the fine-adjusting instruction until the sampling position of the sampling clock is adjusted to the optimal sampling point of each data bit of the serial data after the alignment processing.
Preferably, the Data conversion device further comprises a data_ Cnvs module for integrating and outputting the parallel Data outputted by the ISERDESE.
In order to solve the above technical problems, the present invention provides a data conversion system, which is applied to ISERDESE of a data conversion device, including:
A first adjustment unit, configured to adjust data bits of serial data when receiving bitslip signals, so that boundaries of parallel data in the serial data are aligned with parallel data clock boundaries;
and the second adjusting unit is used for finely adjusting the sampling position of the sampling clock to the optimal sampling point of each data bit of the serial data after the alignment processing so as to sample according to the sequence of the serial data after the alignment processing and convert the serial data into parallel data.
In order to solve the above technical problems, the present invention provides a data conversion device, including:
a memory for storing a computer program;
ISERDESE for implementing the steps of the data conversion method as described above when executing said computer program.
Preferably, the system also comprises a Bitslip _G module;
The Bitslip _g module is configured to search for the first parallel data to be processed in one virtual frame synchronization signal, and if the number of synchronization codes searched in one virtual frame synchronization signal is smaller than a first preset number, output bitslip signals.
Preferably, the device also comprises a delay_value module, an IDELAY module and a data_ Cnvs module;
the Bitslip _g module is further configured to generate a coarse adjustment delay adjustment signal according to a preset time interval and a preset coarse adjustment step when the number of synchronization codes retrieved in one virtual frame synchronization signal is smaller than the first preset number; the step length of the preset coarse adjustment step length is smaller than the length of one clock bit of the serial data;
the delay_value module is used for generating a coarse adjustment signal based on the coarse adjustment Delay adjustment signal;
The IDELAY module is used for converting the coarse adjustment signal into a coarse adjustment instruction;
the Data-Cnvs module is used to integrate and output the parallel Data output by the ISERDESE.
The application provides a data conversion method, a system and a device, which relate to the field of data conversion and are used for converting serial data into parallel data, wherein in the scheme, data bits of the serial data are adjusted when bitslip signals are received so as to align boundaries of parallel data in the serial data with the boundaries of a parallel data clock; and then fine-tuning the sampling position of the sampling clock to the optimal sampling point of each data bit of the serial data after the alignment processing so as to sample according to the sequence of the serial data after the alignment processing and convert the serial data into parallel data. Therefore, when serial data is converted into parallel data, the application not only ensures that the boundary of each parallel data in the serial data is aligned with the boundary of a parallel data clock so as to ensure the accuracy of data conversion, but also ensures that the sampling position of the serial data is the optimal sampling point when the serial data is sampled, and further ensures the accuracy and stability of data sampling.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required in the prior art and the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic flow chart of a data conversion method according to the present invention;
FIG. 2 is a timing chart of a normal sampling according to the present invention;
FIG. 3 is a timing diagram of a boundary alignment process according to the present invention;
FIG. 4 is a timing diagram of a sample position adjustment according to the present invention;
FIG. 5 is a schematic diagram of a data conversion system according to the present invention;
fig. 6 is a schematic structural diagram of a data conversion device according to the present invention;
Fig. 7 is a schematic structural diagram of a data conversion device according to the present invention;
fig. 8 is a schematic structural diagram of a specific module of the data conversion device provided by the invention.
Detailed Description
The core of the invention is to provide a data conversion method, a system and a device, when serial data is converted into parallel data, the boundary of each parallel data in the serial data is aligned with the boundary of a parallel data clock, so that the accuracy of data conversion is ensured, the sampling position of the serial data is ensured to be the optimal sampling point, and the accuracy and the stability of data sampling are further ensured.
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Referring to fig. 1, fig. 1 is a flow chart of a data conversion method provided by the present invention, which is applied to ISERDESE in a data conversion device, and the method includes:
s101: adjusting data bits of the serial data when receiving bitslip signals so as to align boundaries of each parallel data in the serial data with parallel data clock boundaries;
Considering that in the prior art, when serial data is converted into parallel data, the serial data needs to be sampled, namely, each bit of data of the serial data needs to be sampled, and when the serial data is sampled, if the boundary of the parallel data in the serial data is not clear enough, the boundary of the parallel data in the serial data is not aligned with the parallel clock boundary, namely, the boundary of the parallel data is not the first bit of data of the parallel data corresponding to the parallel clock boundary, the acquired parallel data is wrong, and the accurate parallel data cannot be sampled.
Specifically, referring to fig. 2, fig. 2 is a timing chart during normal sampling provided by the present invention, in which data_in in fig. 2 is serial Data, BIT0-BIT7 is parallel Data, in fig. 2 is a parallel Data clock boundary, that is, a rising edge of clk_div is aligned with BIT0, after sampling serial Data, correct parallel Data can be obtained, but due to problems such as a wiring length, phases of clock signals and serial Data cannot be accurately determined, which may cause BIT3 in the serial Data corresponding to the actually parallel Data clock boundary, as shown in fig. 3, fig. 3 is a timing chart for boundary alignment processing provided by the present invention, in which a group of Data aligned with Data0 in fig. 3 is parallel Data, a group of Data aligned with Data1 is parallel Data, a boundary of Data0 and a boundary of Data1 at this time is rising edge of a parallel Data clock, in fig. 3 is a boundary before adjustment, it can be seen that BIT3 in which a boundary of Data0 and Data1 is aligned with BIT3, BIT3 in BIT1 is also BIT3, BIT4 is sampled correctly, BIT6 is BIT1, BIT4 is sampled correctly, and BIT2 is sampled correctly.
In order to solve the above technical problem, in the data conversion device of the present application, when the signal bitslip is received, the data BIT of the serial data is adjusted first at ISERDESE, ISERDESE may be adjusted one BIT backward or forward each time the signal bitslip is received, specifically, for example, when the rising edge of clk_div is aligned with BIT3 and the signal ISERDESE receives bitslip, the data BIT of the serial data is shifted backward by one BIT, at this time, the rising edge of clk_div is aligned with BIT4, the boundary of each parallel data in the serial data is not aligned with the parallel data clock boundary, ISERDESE receives bitslip again and then shifts the data BIT of the serial data backward again by one BIT, at this time, the rising edge of clk_div is aligned with BIT5, ISERDESE continues to receive bitslip signals and continues to adjust the data BIT of the serial data until the rising edge of clk_div is not aligned with BIT0, at this time, it may be determined that the boundary of each data in the serial data is aligned with the parallel data clock boundary, ISERDESE does not need to receive bitslip signals again, and serial data adjustment is continued.
After the boundary alignment process, as seen in FIG. 3 at ②, the adjusted parallel data clock boundary is aligned with BIT0, where the boundary of each parallel data in the serial data is aligned with the parallel data clock boundary.
S102: and fine-adjusting the sampling position of the sampling clock to the optimal sampling point of each data bit of the serial data after the alignment processing so as to sample according to the sequence of the serial data after the alignment processing and convert the serial data into parallel data.
In addition, when each data of the serial data is sampled, if the sampling position of the sampling clock is not the optimal sampling point of each data bit, the sampled data may be unstable or the acquired data may have errors.
As shown in fig. 2, clk in fig. 2 is a sampling clock, fig. 2 is a sampling position of the sampling clock, that is, a rising edge of clk is located at a position relatively middle of each data bit of the serial data, at this time, the sampling position of the sampling clock is at an optimal sampling point of each data bit of the serial data, and also because of a PCB wiring length or other reasons, a phase of the serial data and a phase of the sampling clock cannot be accurately determined, in fact, the rising edge of clk may be aligned too close to a boundary of each data bit, as shown in fig. 4, fig. 4 is a timing chart of sampling position adjustment provided in the present invention, and ② in fig. 4 is a timing chart of sampling position adjustment, it can be seen that the sampling position of the sampling clock, that is, the rising edge of clk is close to a boundary of each data bit, is not located at a middle position of the data bit, at this time, and when data of the sampling position is not stable enough, and there may be fluctuation, so that the data bit is "0" is fluctuation that the data bit boundary fluctuation "data bit accurately" and the data is acquired "1".
In order to solve the above technical problems, in the present application, after the boundary of each parallel data in the serial data is aligned with the boundary of the parallel data clock, the sampling position of the sampling clock is further finely adjusted, so as to adjust the sampling position of the sampling clock to the optimal sampling point of each data bit of the serial data, as shown in fig. 4, the sampling position ② in fig. 4 is adjusted to obtain ③, the sampling position ③ in fig. 4 is in the middle of the data bit, and the accuracy of data acquisition of each data bit of the serial data is ensured.
And when the boundary of each parallel data in the serial data is aligned with the boundary of the parallel data clock, and the sampling position of the sampling clock is finely adjusted to the optimal sampling point of each data bit of the serial data, the serial data can be correctly sampled, each correct parallel data in the serial clock is determined, and the serial data is converted into the parallel data.
It should be noted that, when clock boundary alignment adjustment is performed and the sampling clock is fine-tuned, serial data is continuously sampled, so as to determine whether the clock boundaries are aligned according to the sampled parallel data.
As the modules of the application are universal modules, the self-adaptive adjustment of the time sequence is realized by adopting software programming more, so that the convenience of transplanting among different platforms is improved.
In summary, when serial data is converted into parallel data, the application not only ensures that the boundary of each parallel data in the serial data is aligned with the boundary of a parallel data clock so as to ensure the accuracy of data conversion, but also ensures that the sampling position of the serial data is the optimal sampling point when the serial data is sampled, and further ensures the accuracy and stability of data sampling.
Based on the above embodiments:
As a preferred embodiment of the present invention,
The serial data comprises a plurality of lines of parallel data, the parallel data are one line, and a synchronous code is arranged before the first bit data of each line of parallel data or before the first bit data of each line of parallel data and after the last bit data of each line of parallel data; the data conversion device also comprises a Bitslip _G module;
before adjusting the data bits of the serial data to align the boundaries of each parallel data in the serial data with the parallel data clock boundaries upon receiving the bitslip signal, further comprising:
sampling the serial data according to the sequence of the received serial data so as to convert the serial data into first parallel data to be processed;
the first parallel data to be processed is sent to a Bitslip _G module;
the Bitslip _g module is configured to search for the first parallel data to be processed in one virtual frame synchronization signal, and if the number of synchronization codes searched in one virtual frame synchronization signal is not greater than the first preset number, output bitslip signals.
In this embodiment, the Bitslip _g module determines whether the bitslip signal needs to be output currently to enable the ISERDESE module to adjust the data bit of the serial data, specifically, ISERDESE samples the serial data when the clock boundary is not aligned and the sampling position of the sampling clock is not adjusted, and outputs the first parallel data to be processed obtained after converting the current serial data, so that the Bitslip _g module determines whether the boundary of each parallel data in the serial data is aligned with the clock boundary of the parallel data based on the first parallel data to be processed.
Specifically, the serial data includes a plurality of parallel data, each parallel data includes a plurality of parallel data, in order to align the boundary of each parallel data in the serial data with the parallel data clock boundary, a synchronization code is set before the first data of each parallel data in the serial data to indicate the start boundary of the parallel data in the line, or a synchronization code is set before the first data and after the last data of each parallel data in the line to indicate the start boundary and the end boundary of the parallel data in the line, the Bitslip _g module generates a virtual frame synchronization signal when judging whether to output bitslip signals, the virtual frame synchronization signal needs to be large enough, for example, the virtual frame synchronization signal includes at least ten parallel data in one virtual frame synchronization signal, each parallel data includes 64 parallel data, if the synchronization code is set before the first data and after the last data of each parallel data in the line, the Bitslip _g module can retrieve 20 parallel data in one virtual frame synchronization signal. Based on this, in the present application, when a first preset number is set, it is determined that the number of lines of parallel data in a virtual frame synchronization signal is line_num, the first preset number is set to num_t= (line_num-2), if Bitslip _g module retrieves that the number of synchronization codes in the first parallel data to be processed is greater than num_t in a virtual frame synchronization signal, it indicates that the boundary of each parallel data in the serial data is clear at this time, and the boundary of each parallel data in the first parallel data to be processed is aligned with the clock boundary of the parallel data, so that clock boundary alignment processing is not required for the serial data, that is, bitslip _g module does not need to output bitslip signals. Otherwise, if the Bitslip _g module retrieves that the number of synchronization codes in the first parallel data to be processed is not greater than the first preset number in one virtual frame synchronization signal, each parallel data in the collected first parallel data to be processed is incomplete and inaccurate, and at this time, the Bitslip _g module needs to output a bitslip signal to make ISERDESE perform adjustment on data bits of the serial data.
It should be noted that the synchronization code may be, but not limited to, a fixed string of data set by the user, and the synchronization code may be, but not limited to, fixed data of 4 bytes, so as to avoid that the serial data accidentally has the same data as the synchronization code, which results in influence on the judgment result of the synchronization code in the first parallel data to be processed.
In addition, considering that although the synchronization code in the present application is set by the user, the same data as the synchronization code may exist in the parallel data, so in the present application, the Bitslip _g module retrieves that the number of synchronization codes in the first parallel data to be processed is greater than the first preset number in one virtual frame synchronization signal, to indicate that the boundary of each parallel data in the serial data is clear at this time, and the boundary of each parallel data in the first parallel data to be processed is aligned with the boundary of the parallel data clock, so as to ensure the accuracy of judgment.
As a preferred embodiment, the data conversion device further includes a delay_value module and an IDELAY module;
The Bitslip _G module is further used for generating a coarse adjustment delay adjustment signal according to a preset time interval and a preset coarse adjustment step length when the number of the synchronous codes retrieved in one virtual frame synchronous signal is not greater than a first preset number; the step length of the preset coarse adjustment step length is smaller than the length of one clock cycle of the serial data;
the delay_value module is used for generating a coarse adjustment signal based on the coarse adjustment Delay adjustment signal;
the IDELAY module is used for converting the coarse adjustment signal into a coarse adjustment instruction;
adjusting data bits of serial data upon receipt of bitslip signals to align boundaries of respective parallel data in the serial data with parallel data clock boundaries, comprising:
And when receiving bitslip signals and coarse adjustment instructions, adjusting data bits of the serial data, and performing coarse adjustment on sampling positions of a sampling clock so as to align boundaries of parallel data in the serial data with boundaries of the parallel data clock.
In this embodiment, it is considered that, when the boundary alignment processing is performed, if the sampling boundary of the sampling clock is not at the relatively inaccurate sampling point of the data bits of the serial data, an error still exists in the collected first parallel data to be processed, which may cause that although the boundary alignment processing is performed to align the boundary of each parallel data in the serial data with the boundary of the parallel data clock, the number of synchronization codes is still insufficient when the number of synchronization codes is determined due to inaccuracy of data collection, and the shift of the data bits of the serial number is continued to cause that the boundary of each parallel data in the serial data deviates more from the boundary of the parallel data clock.
In order to solve the above-mentioned technical problem, the Bitslip _g module in this embodiment outputs the bitslip signal to make ISERDESE perform adjustment of the data bits of the serial data, and generates a coarse Delay adjustment signal to make the delay_value module generate a coarse adjustment signal, and then the coarse adjustment signal is converted into a coarse adjustment instruction by the ideelay module to make ISERDESE coarse adjust the sampling position of the sampling clock, which may not be completely adjusted to the optimal sampling point at this time, but is sufficient to ensure the accuracy of determining whether the boundary of the parallel data is aligned with the boundary of the parallel data clock at this time.
In summary, in this embodiment, coarse adjustment is performed on the phase of the sampling clock while the data bits are moved, so that accuracy of sampling serial data is ensured, and meanwhile, whether the boundary of each parallel data in the serial data is aligned with the boundary of the parallel clock is determined, so that whether continuous boundary alignment processing is required is accurately determined, and resource waste caused by multiple erroneous adjustment is avoided.
Specifically, as a preferred embodiment, adjusting the data bits of the serial data and coarse adjusting the sampling position of the sampling clock to align the boundary of each parallel data in the serial data with the parallel data clock boundary when receiving bitslip signals and coarse adjusting instructions, includes:
S201: shifting the phase of the data bits of the serial data one clock cycle forward or one clock cycle backward upon receipt of the bitslip signal;
s202: setting a rough adjustment instruction as a current rough adjustment instruction, and setting a preset rough adjustment step length as a current rough adjustment step length;
S204: performing first forward adjustment on the sampling position of the sampling clock based on the current coarse adjustment instruction;
S205: sampling the serial data after the data shift based on the sampling clock subjected to the first forward adjustment to generate current parallel data to be processed, enabling the Bitslip _G module to search the current parallel data to be processed in a virtual frame synchronizing signal, and if the number of the synchronous codes searched in the virtual frame synchronizing signal is not more than a first preset number, entering step S206; if yes, go to step S212;
S206: performing two-time reverse adjustment on the sampling position of the sampling clock based on the current rough adjustment instruction;
S207: based on the sampling clock after the two times of reverse adjustment, sampling the serial data after the data shift, updating the current parallel data to be processed, enabling the Bitslip _G module to search the current parallel data to be processed in a virtual frame synchronizing signal, and if the number of the synchronous codes searched in the virtual frame synchronizing signal is not more than a first preset number, entering step S208; if yes, go to step S212;
s208: performing second forward adjustment on the sampling position of the sampling clock based on the current coarse adjustment instruction;
s209: increasing the current coarse adjustment step length by a preset coarse adjustment minimum unit, judging whether the current coarse adjustment step length is larger than the maximum adjustment step length, and if not, entering step S210; if yes, go to step S211;
S210: the Bitslip _G module updates the coarse adjustment delay adjustment signal according to the preset time interval and the current coarse adjustment step length; the delay_value module updates the current coarse adjustment signal based on the updated coarse adjustment Delay adjustment signal, and the IDELAY module updates the current coarse adjustment instruction based on the updated current coarse adjustment signal; returning to step S204;
s211: the Bitslip _g module outputs bitslip signal and returns to step S201;
S212: and aligning the boundary of each parallel data in the serial data with the boundary of the parallel data clock, and entering the step of finely adjusting the sampling position of the sampling clock to the optimal sampling point of each data bit of the serial data after the alignment processing.
In this embodiment, when performing clock boundary alignment processing on serial data, if the Bitslip _g module outputs bitslip signal according to the first parallel data to be processed, the phase of the data BIT of the serial data is shifted forward by one clock cycle or shifted backward by one clock cycle when receiving the bitslip signal, for example, the parallel data clock boundary is aligned with BIT3 of the parallel data in the serial data before receiving the bitslip signal, the parallel data clock boundary is aligned with BIT4 of the parallel data after shifting forward by one clock cycle after receiving the bitslip signal, or the parallel data clock boundary is aligned with BIT2 of the parallel data in the serial data after shifting backward by one clock cycle after receiving the bitslip signal. Setting a coarse adjustment instruction as a current coarse adjustment instruction, setting a preset coarse adjustment step size as a current coarse adjustment step size, performing first forward adjustment on the sampling position of a sampling clock based on the current coarse adjustment instruction, namely performing first backward adjustment on the sampling position of the sampling clock, and then sampling serial data after data shift based on the sampling clock after the first forward adjustment, so that Bitslip _G module searches current parallel data to be processed in a virtual frame synchronization signal, judging whether the current parallel data are aligned in a boundary, if the number of synchronous codes searched in one virtual frame synchronization signal is not greater than the first preset number, the sampling clock position is bad or the boundary of the parallel data clock is not aligned, considering the problem of the sampling clock position at the moment, continuously performing second backward adjustment on the sampling position of the sampling clock, and performing second backward adjustment on the sampling position of the sampling clock after the first backward adjustment and the sampling position of the sampling clock before the first forward adjustment are the same, so that different positions can be sampled. If the Bitslip _g module still outputs bitslip signal after the two times of reverse adjustment, at this time, a forward adjustment is performed to restore the sampling position of the sampling clock to the initial position, so that the current coarse adjustment step is increased by a preset coarse adjustment minimum unit, and a round of forward adjustment and reverse adjustment is performed again until the Bitslip _g module no longer outputs bitslip signal or the current coarse adjustment step is longer than the maximum adjustment step.
It should be noted that, the current coarse adjustment step length is formed by a plurality of preset coarse adjustment minimum units, and of course, the preset coarse adjustment step length can be set to be the preset coarse adjustment minimum units, the current coarse adjustment step length is adjusted by the preset coarse adjustment minimum units at intervals of preset time, the total adjustment step length after adjustment of the preset coarse adjustment minimum units is the current coarse adjustment step length, for example, the current coarse adjustment step length is formed by 20 preset coarse adjustment minimum units, and each preset coarse adjustment minimum unit ISERDESE is used for sampling the serial clock once, so that the Bitslip _g module searches the current parallel data to be processed once in a virtual frame synchronization signal, and the current coarse adjustment is stopped when the number of the searched coarse synchronization codes in the virtual frame synchronization signal is greater than the first preset number.
In addition, no matter whether the Bitslip _g module searches the current parallel data to be processed in a virtual frame synchronization signal in the forward direction adjustment or the backward direction adjustment, and the number of the synchronization codes searched in the virtual frame synchronization signal is larger than the first preset number, the boundary of each parallel data in the serial data can be determined to be aligned with the boundary of the parallel data clock, and then the step of fine-adjusting the sampling position of the sampling clock to the optimal sampling point of each data bit of the aligned serial data is carried out.
As a preferred embodiment, fine-tuning the sampling position of the sampling clock to an optimal sampling point of each data bit of the aligned serial data to sample in the order of the aligned serial data, converting the serial data into parallel data, includes:
Sampling a second preset number of times according to the sequence of the aligned serial data, outputting a second preset number of second parallel data to be processed, so that Bitslip _G modules search the second preset number of second parallel data to be processed in the second preset number of virtual frame synchronizing signals respectively, and if the number of the synchronizing codes searched in the second preset number of virtual frame synchronizing signals is not equal to or larger than the second preset number, generating a fine-tuning delay adjustment signal according to a preset time interval and a preset fine-tuning adjustment period; the preset fine adjustment minimum unit of the fine adjustment period is smaller than the preset coarse adjustment minimum unit; and causing the Delay Value module to generate a fine adjustment signal based on the fine adjustment Delay adjustment signal; causing the ideelay module to convert the fine-tuning signal into a fine-tuning instruction;
and fine-adjusting the sampling position of the sampling clock based on the fine-adjusting instruction until the sampling position of the sampling clock is adjusted to the optimal sampling point of each data bit of the aligned serial data.
Specifically, for example, the Bitslip _g module outputs a fine adjustment Delay adjustment signal, the delay_value module generates a fine adjustment signal, and then the fine adjustment signal is converted into a fine adjustment instruction for forward adjustment by the IDELAY module, the fine adjustment signal and the forward adjustment are the adjusted timing lag original timing sequence, ISERDESE performs forward adjustment on the sampling position of the sampling clock according to the fine adjustment instruction after receiving the fine adjustment instruction for forward adjustment, and the adjustment length is a preset fine adjustment step length, at this time ISERDESE samples based on serial data after adjustment of the adjusted sampling clock, so that the Bitslip _g module determines whether the fine adjustment Delay adjustment signal needs to be continuously output to perform phase adjustment of the sampling clock; if the phase adjustment of the sampling clock is still needed, the Bitslip _g module generates a fine adjustment Delay adjustment signal again, the delay_value module generates a fine adjustment signal, the fine adjustment signal is converted into a fine adjustment instruction of reverse adjustment by the IDELAY module, the reverse adjustment and the forward adjustment are opposite in time sequence, the reverse adjustment is that the adjusted time sequence leads the original time sequence, ISERDESE carries out two times of reverse adjustment on the sampling position of the sampling clock according to the fine adjustment instruction after receiving the fine adjustment instruction of the reverse adjustment, the adjustment length is a preset fine adjustment step length, and ISERDESE samples the adjusted serial data based on the adjusted sampling clock at the moment so as to judge whether the Bitslip _g module needs to continuously output the fine adjustment Delay adjustment signal to carry out the phase adjustment of the sampling clock; if the phase adjustment of the sampling clock is still needed, the Bitslip _G module generates a fine adjustment Delay adjustment signal, the delay_value module generates a fine adjustment signal, the fine adjustment signal is converted into a fine adjustment instruction for forward adjustment by the IDELAY module, after the fine adjustment instruction for forward adjustment is received, ISERDESE carries out forward adjustment on the sampling position of the sampling clock again according to the fine adjustment instruction, the adjustment length is a preset fine adjustment step length, and at the moment, the sampling position of the sampling clock is restored to the sampling position before the first forward adjustment; after the adjustment process is finished, the Bitslip _g module increases the preset fine adjustment step length, for example, increases the preset fine adjustment step length by a preset fine adjustment minimum unit, and continues to generate a fine adjustment delay adjustment signal so as to continue adjustment until the sampling position of the sampling clock is the optimal sampling point. It should be noted that the preset fine adjustment minimum unit is smaller than the preset coarse adjustment minimum unit.
It should be noted that, when the process of fine adjustment is the same as the process of coarse adjustment, the Bitslip _g module determines whether to continue adjustment in the adjustment process, and also performs forward adjustment first, then performs reverse adjustment twice, then performs forward adjustment once, continues adjustment after increasing the preset fine adjustment step length, and does not perform adjustment once in ISERDESE when performing forward adjustment or reverse adjustment each time, until the Bitslip _g module determines that the sampling position of the sampling clock is the optimal sampling point. In the application, when the Bitslip _g module determines that the sampling position of the sampling clock is the optimal sampling point, specifically, ISERDESE samples the serial data after alignment processing for a second preset number of times, so as to output a second preset number of second parallel data to be processed, and the Bitslip _g module retrieves the second preset number of second parallel data to be processed in the second preset number of virtual frame synchronizing signals, that is, the Bitslip _g module needs to determine whether the number of synchronous codes in the second preset number of second parallel data to be processed sampled by ISERDESE is greater than the second preset number, and only when the numbers are greater than the second preset number, the second parallel data to be processed sampled by ISERDESE can be determined to be accurate, that is, the sampling position of the current sampling clock is the optimal sampling point.
As a preferred embodiment, the Data conversion device further comprises a data_ Cnvs module for integrating and outputting the parallel Data outputted by ISERDESE.
In this embodiment, a data_ Cnvs module is further provided, so that the parallel Data output after the serial Data is sampled by ISERDESE is integrated and output, and the subsequent processing of the parallel Data is facilitated.
Referring to fig. 5, fig. 5 is a schematic structural diagram of a data conversion system provided by the present invention, where the system is applied to ISERDESE of a data conversion device, and includes:
a first adjusting unit 51, configured to adjust data bits of the serial data when receiving the bitslip signal, so as to align boundaries of each parallel data in the serial data with parallel data clock boundaries;
The second adjusting unit 52 is configured to fine-tune the sampling position of the sampling clock to an optimal sampling point of each data bit of the aligned serial data, so as to sample the aligned serial data in order, and convert the serial data into parallel data.
For an introduction of a data conversion system provided by the present invention, refer to the above method embodiment, and the present invention is not described herein.
Referring to fig. 6, fig. 6 is a schematic structural diagram of a data conversion device according to the present invention, where the device includes:
a memory 61 for storing a computer program;
ISERDESE62 for implementing the steps of the data conversion method as described above when executing a computer program.
For an introduction of the data conversion device provided by the present invention, please refer to the above method embodiment, and the description of the present invention is omitted herein.
As a preferred embodiment, the device further comprises a Bitslip _g module;
The Bitslip _g module is configured to search for the first parallel data to be processed in one virtual frame synchronization signal, and if the number of synchronization codes searched in one virtual frame synchronization signal is less than the first preset number, output bitslip signals.
Referring to fig. 7 and fig. 8, fig. 7 is a schematic structural diagram of a data conversion device according to the present invention, and fig. 8 is a schematic structural diagram of a specific module of the data conversion device according to the present invention. In fig. 7, delay_add and delay_dec are coarse delay adjustment signals, INC and CE are coarse delay adjustment signals, fig. 8 is a specific structure of selectio _serial module in fig. 7, and Optional Input Delay module, i.e. ideelay module, receives the coarse delay adjustment signals and converts the coarse delay adjustment signals into coarse delay instructions to send to ISERDESE.
As a preferred embodiment, the device further comprises a delay_value module, an IDELAY module and a data_ Cnvs module;
the Bitslip _G module is further used for generating a coarse adjustment delay adjustment signal according to a preset time interval and a preset coarse adjustment step length when the number of the synchronization codes retrieved in one virtual frame synchronization signal is smaller than a first preset number; the step length of the preset coarse adjustment step length is smaller than the length of one clock bit of the serial data;
the delay_value module is used for generating a coarse adjustment signal based on the coarse adjustment Delay adjustment signal;
the IDELAY module is used for converting the coarse adjustment signal into a coarse adjustment instruction;
the data_ Cnvs module is used for integrating and outputting the parallel Data output by ISERDESE.
It should also be noted that in this specification, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (4)
1. A data conversion method, characterized by being applied to ISERDESE in a data conversion apparatus, the method comprising:
adjusting data bits of serial data when bitslip signals are received so that boundaries of parallel data in the serial data are aligned with parallel data clock boundaries;
Fine-adjusting the sampling position of the sampling clock to the optimal sampling point of each data bit of the serial data after the alignment processing so as to sample according to the sequence of the serial data after the alignment processing, and converting the serial data into parallel data;
The serial data comprises a plurality of lines of parallel data, the parallel data are one line, and synchronous codes are arranged before the first data of each line of parallel data or before the first data of each line of parallel data and after the last data of each line of parallel data; the data conversion device also comprises a Bitslip _G module;
Before adjusting the data bits of the serial data to align the boundaries of each parallel data in the serial data with the parallel data clock boundaries when receiving bitslip signals, the method further comprises:
Sampling the serial data according to the sequence of the received serial data so as to convert the serial data into first parallel data to be processed;
transmitting the first parallel data to be processed to the Bitslip _g module;
The Bitslip _g module is configured to search the first parallel data to be processed in one virtual frame synchronization signal, and if the number of synchronization codes searched in one virtual frame synchronization signal is not greater than a first preset number, output the bitslip signal;
The data conversion device also comprises a delay_value module and an IDELAY module;
The Bitslip _g module is further configured to generate a coarse tuning delay adjustment signal according to a preset time interval and a preset coarse tuning adjustment step when the number of synchronization codes retrieved in one virtual frame synchronization signal is not greater than a first preset number; the step length of the preset coarse adjustment step length is smaller than the length of one clock cycle of the serial data;
the delay_value module is used for generating a coarse adjustment signal based on the coarse adjustment Delay adjustment signal;
The IDELAY module is used for converting the coarse adjustment signal into a coarse adjustment instruction;
adjusting data bits of serial data upon receipt of bitslip signals to align boundaries of respective parallel data in the serial data with parallel data clock boundaries, comprising:
When receiving the bitslip signal and the coarse adjustment instruction, adjusting the data bit of the serial data, and performing coarse adjustment on the sampling position of the sampling clock so as to align the boundary of each parallel data in the serial data with the boundary of the parallel data clock;
Adjusting data bits of serial data and coarse adjusting sampling positions of the sampling clock when receiving bitslip signals and the coarse adjusting instruction so as to align boundaries of parallel data in the serial data with boundaries of the parallel data clock, wherein the method comprises the following steps:
S201: shifting the phase of the data bits of the serial data one clock cycle forward or one clock cycle backward upon receipt of the bitslip signal;
s202: setting the rough adjustment instruction as a current rough adjustment instruction, and setting the preset rough adjustment step length as a current rough adjustment step length;
s204: performing first forward adjustment on the sampling position of the sampling clock based on the current coarse adjustment instruction;
S205: sampling the serial data after the data shift based on the sampling clock subjected to the first forward adjustment to generate current parallel data to be processed, enabling the Bitslip _G module to search the current parallel data to be processed in one virtual frame synchronizing signal, and if the number of the synchronizing codes searched in one virtual frame synchronizing signal is not greater than the first preset number, entering step S206; if yes, go to step S212;
S206: performing two-time reverse adjustment on the sampling position of the sampling clock based on the current coarse adjustment instruction;
S207: sampling the serial data after the data shift based on the sampling clock subjected to the two-time reverse adjustment, updating the current parallel data to be processed, enabling the Bitslip _G module to search the current parallel data to be processed in one virtual frame synchronizing signal, and if the number of the synchronous codes searched in one virtual frame synchronizing signal is not greater than the first preset number, entering step S208; if yes, go to step S212;
S208: performing second forward adjustment on the sampling position of the sampling clock based on the current coarse adjustment instruction;
s209: adding a preset coarse adjustment minimum unit to the current coarse adjustment step length, judging whether the current coarse adjustment step length is larger than a maximum adjustment step length, and if not, entering step S210; if yes, go to step S211;
S210: the Bitslip _G module updates the coarse adjustment delay adjustment signal according to the preset time interval and the current coarse adjustment step length; the delay_value module updates a current coarse adjustment signal based on the updated coarse adjustment Delay adjustment signal, and the IDELAY module updates the current coarse adjustment instruction based on the updated current coarse adjustment signal; returning to step S204;
s211: the Bitslip _g module outputs the bitslip signal and returns to step S201;
S212: aligning the boundary of each parallel data in the serial data with the boundary of the parallel data clock, and entering a step of finely adjusting the sampling position of the sampling clock to the optimal sampling point of each data bit of the serial data after alignment processing;
Fine-adjusting a sampling position of a sampling clock to an optimal sampling point of each data bit of the serial data after alignment processing so as to sample the serial data after alignment processing in order, and converting the serial data into parallel data, including:
Sampling a second preset number of times according to the sequence of the serial data after the alignment processing, outputting a second preset number of second parallel data to be processed, so that the Bitslip _G module searches the second preset number of second parallel data to be processed in the second preset number of virtual frame synchronizing signals respectively, and if the number of the synchronizing codes searched in the second preset number of virtual frame synchronizing signals is not equal to or larger than the second preset number, generating a fine-tuning delay adjusting signal according to the preset time interval and a preset fine-tuning adjusting period; the preset fine adjustment minimum unit of the fine adjustment period is smaller than the preset coarse adjustment minimum unit; and causing the delay_value module to generate a fine adjustment signal based on the fine adjustment Delay adjustment signal; causing the IDELAY module to convert the fine-tuning signal into a fine-tuning instruction;
and fine-adjusting the sampling position of the sampling clock based on the fine-adjusting instruction until the sampling position of the sampling clock is adjusted to the optimal sampling point of each data bit of the serial data after the alignment processing.
2. The Data conversion method of claim 1, wherein the Data conversion device further comprises a data_ Cnvs module for integrating and outputting the parallel Data outputted by the ISERDESE.
3. A data conversion system, characterized by ISERDESE for use in a data conversion device, comprising:
A first adjustment unit, configured to adjust data bits of serial data when receiving bitslip signals, so that boundaries of parallel data in the serial data are aligned with parallel data clock boundaries;
The second adjusting unit is used for finely adjusting the sampling position of the sampling clock to the optimal sampling point of each data bit of the serial data after the alignment processing so as to sample according to the sequence of the serial data after the alignment processing and convert the serial data into parallel data;
The serial data comprises a plurality of lines of parallel data, the parallel data are one line, and synchronous codes are arranged before the first data of each line of parallel data or before the first data of each line of parallel data and after the last data of each line of parallel data; the data conversion device also comprises a Bitslip _G module;
Before adjusting the data bits of the serial data to align the boundaries of each parallel data in the serial data with the parallel data clock boundaries when receiving bitslip signals, the method further comprises:
Sampling the serial data according to the sequence of the received serial data so as to convert the serial data into first parallel data to be processed;
transmitting the first parallel data to be processed to the Bitslip _g module;
The Bitslip _g module is configured to search the first parallel data to be processed in one virtual frame synchronization signal, and if the number of synchronization codes searched in one virtual frame synchronization signal is not greater than a first preset number, output the bitslip signal;
The data conversion device also comprises a delay_value module and an IDELAY module;
The Bitslip _g module is further configured to generate a coarse tuning delay adjustment signal according to a preset time interval and a preset coarse tuning adjustment step when the number of synchronization codes retrieved in one virtual frame synchronization signal is not greater than a first preset number; the step length of the preset coarse adjustment step length is smaller than the length of one clock cycle of the serial data;
the delay_value module is used for generating a coarse adjustment signal based on the coarse adjustment Delay adjustment signal;
The IDELAY module is used for converting the coarse adjustment signal into a coarse adjustment instruction;
adjusting data bits of serial data upon receipt of bitslip signals to align boundaries of respective parallel data in the serial data with parallel data clock boundaries, comprising:
When receiving the bitslip signal and the coarse adjustment instruction, adjusting the data bit of the serial data, and performing coarse adjustment on the sampling position of the sampling clock so as to align the boundary of each parallel data in the serial data with the boundary of the parallel data clock;
Adjusting data bits of serial data and coarse adjusting sampling positions of the sampling clock when receiving bitslip signals and the coarse adjusting instruction so as to align boundaries of parallel data in the serial data with boundaries of the parallel data clock, wherein the method comprises the following steps:
S201: shifting the phase of the data bits of the serial data one clock cycle forward or one clock cycle backward upon receipt of the bitslip signal;
s202: setting the rough adjustment instruction as a current rough adjustment instruction, and setting the preset rough adjustment step length as a current rough adjustment step length;
s204: performing first forward adjustment on the sampling position of the sampling clock based on the current coarse adjustment instruction;
S205: sampling the serial data after the data shift based on the sampling clock subjected to the first forward adjustment to generate current parallel data to be processed, enabling the Bitslip _G module to search the current parallel data to be processed in one virtual frame synchronizing signal, and if the number of the synchronizing codes searched in one virtual frame synchronizing signal is not greater than the first preset number, entering step S206; if yes, go to step S212;
S206: performing two-time reverse adjustment on the sampling position of the sampling clock based on the current coarse adjustment instruction;
S207: sampling the serial data after the data shift based on the sampling clock subjected to the two-time reverse adjustment, updating the current parallel data to be processed, enabling the Bitslip _G module to search the current parallel data to be processed in one virtual frame synchronizing signal, and if the number of the synchronous codes searched in one virtual frame synchronizing signal is not greater than the first preset number, entering step S208; if yes, go to step S212;
S208: performing second forward adjustment on the sampling position of the sampling clock based on the current coarse adjustment instruction;
s209: adding a preset coarse adjustment minimum unit to the current coarse adjustment step length, judging whether the current coarse adjustment step length is larger than a maximum adjustment step length, and if not, entering step S210; if yes, go to step S211;
S210: the Bitslip _G module updates the coarse adjustment delay adjustment signal according to the preset time interval and the current coarse adjustment step length; the delay_value module updates a current coarse adjustment signal based on the updated coarse adjustment Delay adjustment signal, and the IDELAY module updates the current coarse adjustment instruction based on the updated current coarse adjustment signal; returning to step S204;
s211: the Bitslip _g module outputs the bitslip signal and returns to step S201;
S212: aligning the boundary of each parallel data in the serial data with the boundary of the parallel data clock, and entering a step of finely adjusting the sampling position of the sampling clock to the optimal sampling point of each data bit of the serial data after alignment processing;
Fine-adjusting a sampling position of a sampling clock to an optimal sampling point of each data bit of the serial data after alignment processing so as to sample the serial data after alignment processing in order, and converting the serial data into parallel data, including:
Sampling a second preset number of times according to the sequence of the serial data after the alignment processing, outputting a second preset number of second parallel data to be processed, so that the Bitslip _G module searches the second preset number of second parallel data to be processed in the second preset number of virtual frame synchronizing signals respectively, and if the number of the synchronizing codes searched in the second preset number of virtual frame synchronizing signals is not equal to or larger than the second preset number, generating a fine-tuning delay adjusting signal according to the preset time interval and a preset fine-tuning adjusting period; the preset fine adjustment minimum unit of the fine adjustment period is smaller than the preset coarse adjustment minimum unit; and causing the delay_value module to generate a fine adjustment signal based on the fine adjustment Delay adjustment signal; causing the IDELAY module to convert the fine-tuning signal into a fine-tuning instruction;
and fine-adjusting the sampling position of the sampling clock based on the fine-adjusting instruction until the sampling position of the sampling clock is adjusted to the optimal sampling point of each data bit of the serial data after the alignment processing.
4. A data conversion apparatus, comprising:
a memory for storing a computer program;
ISERDESE, for implementing the steps of the data conversion method according to any one of claims 1 to 2 when said computer program is executed;
Also comprises Bitslip _G module;
The Bitslip _g module is configured to search for first parallel data to be processed in one virtual frame synchronization signal, and if the number of synchronization codes searched in one virtual frame synchronization signal is smaller than a first preset number, output bitslip signals;
The device also comprises a delay_value module, an IDELAY module and a data_ Cnvs module;
the Bitslip _g module is further configured to generate a coarse adjustment delay adjustment signal according to a preset time interval and a preset coarse adjustment step when the number of synchronization codes retrieved in one virtual frame synchronization signal is smaller than the first preset number; the step length of the preset coarse adjustment step length is smaller than the length of one clock bit of the serial data;
the delay_value module is used for generating a coarse adjustment signal based on the coarse adjustment Delay adjustment signal;
The IDELAY module is used for converting the coarse adjustment signal into a coarse adjustment instruction;
the Data-Cnvs module is used to integrate and output the parallel Data output by the ISERDESE.
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| CN107222219A (en) * | 2017-06-28 | 2017-09-29 | 中国电子科技集团公司第五十八研究所 | Possesses the high speed serial parallel exchange circuit of frame alignment function |
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| CN107222219A (en) * | 2017-06-28 | 2017-09-29 | 中国电子科技集团公司第五十八研究所 | Possesses the high speed serial parallel exchange circuit of frame alignment function |
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