CN114839453A - Slave board wiring method of HIL test system and HIL test system - Google Patents
Slave board wiring method of HIL test system and HIL test system Download PDFInfo
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- 238000005070 sampling Methods 0.000 claims abstract description 144
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- 238000012163 sequencing technique Methods 0.000 claims abstract description 5
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/005—Testing of electric installations on transport means
- G01R31/006—Testing of electric installations on transport means on road vehicles, e.g. automobiles or trucks
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
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Abstract
The application discloses a slave board wiring method of an HIL test system and the HIL test system, which are applied to a battery management system, wherein the slave board wiring method comprises the following steps: obtaining voltage and temperature sampling channel information of each AFE sampling chip according to sampling channels of the AFE sampling chips in the first slave plate and the second slave plate and an electrical principle topological graph; confirming the multiplexing mode of the sampling channel according to the set multiplexing principle and the voltage and temperature sampling channel information to form a multiplexing channel; naming and sequencing pins of an I/O output port; and connecting the multiplexing channel with the corresponding pin of the I/O output port according to the electrical principle topological diagram. Compared with the prior art that each slave board sampling channel independently occupies one I/O output port, the voltage and temperature loops which need to be redesigned from the slave board can be reduced through reasonable and scientific multiplexing of the slave board wiring of the HIL test system, so that the structural design of the slave board HIL test system is simplified, and the cost is saved.
Description
Technical Field
The application relates to the technical field of automotive electronic controller HIL test systems, in particular to a slave board wiring method of an HIL test system and the HIL test system.
Background
HIL (Hardware-in-the Loop) testing plays an extremely important role in the development process of automobile electronic controllers. The HIL test system can replace the electronic controller to be tested and other device components except the controlled object through a simulation model, and the electronic controller to be tested and the controlled object are connected with the simulation system in a closed loop mode to perform function and performance tests on the electronic control unit or the component to be tested. The period of the whole vehicle verification is long, and the whole vehicle verification is restricted by testers, a test environment, natural conditions and the like, so that the development nodes cannot be guaranteed to be completed on time, the HIL test system can simulate part or all control strategies of the whole vehicle test environment verification in different stages of project development, execute dangerous test cases in a real vehicle test environment, reduce the restriction of external environment conditions, execute work in all weather in 7x24 hours, greatly shorten the test period and the development cost and release test manpower, and therefore the HIL test system plays an irreplaceable role in the development flow of an electronic controller of an automobile.
The BMS-HIL test system has the big problems that after the iterative switching of the development project of the electronic controller, the test wire harnesses of a main board and a slave board are required to be re-manufactured according to the definition, particularly the wire harnesses for collecting the voltage and the temperature information of the slave board are required, each sampling channel of the slave board occupies an I/O port of a rack test system independently, more than 200 loops are required to be re-designed and manufactured, and after the iterative switching of the project, the HIL test system environment is required to be re-built according to the definition of the slave board, so that the great time cost and the labor consumption are brought.
Therefore, how to design and improve the slave board wiring scheme, reasonably optimize the slave board voltage and temperature information sampling loop, save the time for building the HIL test system, realize the quick switching of test items, and have great significance for BMS-HIL test development.
Disclosure of Invention
The application provides a slave board wiring method of an HIL test system and the HIL test system, and aims to solve the problem that in the prior art, the reconstruction of the HIL test system requires extremely high time cost and labor consumption.
In order to solve the above technical problem, the present application provides a slave board wiring method of an HIL test system, including: obtaining voltage and temperature sampling channel information of each AFE sampling chip according to sampling channels of the AFE sampling chips in the first slave plate and the second slave plate and an electrical principle topological graph; confirming the multiplexing mode of the sampling channel according to the set multiplexing principle and the voltage and temperature sampling channel information to form a multiplexing channel; naming and sequencing pins of an I/O output port; and connecting the multiplexing channel with the corresponding pin of the I/O output port according to the electrical principle topological diagram.
Optionally, the first slave board and the second slave board each include a plurality of identical AFE sampling chips; obtaining voltage and temperature sampling channel information of each AFE sampling chip according to sampling channels of the AFE sampling chips in the first slave plate and the second slave plate and an electrical principle topological graph, wherein the voltage and temperature sampling channel information comprises: naming pins of each AFE sampling chip according to naming rules of voltage and temperature sampling channels, so that voltage and temperature sampling channel information of each AFE sampling chip is obtained; wherein, the naming rule is as follows: from plate number _ AFE sampling chip number _ pin number _ vendor.
Optionally, the set multiplexing principle includes: the same serial numbers of different AFE sampling chips share one I/O output port; only a confluence copper plate is bridged between the two sampling channels of the same AFE sampling chip, and the two sampling channels share one I/O output port.
Optionally, naming the pins of the I/O outlet includes: determining as a voltage sample or a temperature sample; the sequence number is included in the naming, which follows the principle of increasing one by one starting from 0.
Optionally, sorting pins of the I/O output port includes: gradually increasing according to the names; after the previous connector is fully arranged, the next connector is spliced; the sequence number does not jump and miss.
In order to solve the above technical problem, the present application provides an HIL test system, which is applied to a battery management system, and includes: the device comprises a first slave plate and a second slave plate, wherein the first slave plate and the second slave plate are provided with a plurality of AFE sampling chips, and each AFE sampling chip comprises a sampling channel; the first slave plate and the second slave plate are connected with the I/O board card through the I/O output ports, and the I/O output ports are sorted according to names; the sampling channels form multiplexing channels according to a set multiplexing principle, and the multiplexing channels are connected with the I/O output ports in a one-to-one correspondence mode according to an electrical principle topological diagram.
Optionally, the first slave board and the second slave board each include a plurality of identical AFE sampling chips; the pins of the AFE sampling chip include the nomenclature, which is: from plate number _ AFE sampling chip number _ pin number _ vendor.
Optionally, the set multiplexing principle includes: the same serial numbers of different AFE sampling chips share one I/O output port; only a confluence copper plate is bridged between the two sampling channels of the same AFE sampling chip, and the two sampling channels share one I/O output port.
Optionally, the naming rule of the I/O egress port includes: determining as a voltage sample or a temperature sample; the sequence number is included in the naming, which follows the principle of increasing one by one starting from 0.
Optionally, the I/O egress port ordering rule includes: gradually increasing according to the name; after the previous connector is fully arranged, the next connector is spliced; the sequence number does not jump and miss.
The application provides a slave board wiring method of an HIL test system and the HIL test system, which are applied to a battery management system, wherein the slave board wiring method comprises the following steps: obtaining voltage and temperature sampling channel information of each AFE sampling chip according to sampling channels of the AFE sampling chips in the first slave plate and the second slave plate and an electrical principle topological graph; confirming the multiplexing mode of the sampling channel according to the set multiplexing principle and the voltage and temperature sampling channel information to form a multiplexing channel; naming and sequencing pins of an I/O output port; and connecting the multiplexing channel with the corresponding pin of the I/O output port according to the electrical principle topological diagram. Compared with the prior art that each slave board sampling channel independently occupies one I/O output port, the voltage and temperature loops which need to be redesigned from the slave board can be reduced through reasonable and scientific multiplexing of the slave board wiring of the HIL test system, so that the structural design of the slave board HIL test system is simplified, and the cost is saved.
Drawings
In order to more clearly illustrate the technical solution of the present application, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings without creative efforts.
FIG. 1 is a schematic flow chart diagram of one embodiment of a slave board wiring method of the HIL test system of the present application;
fig. 2 is a schematic diagram of the channel multiplexing method after step S120 is executed in fig. 1;
FIG. 3 is a schematic diagram illustrating pin naming and ordering of I/O output ports after step S130 is performed in FIG. 1;
FIG. 4 is a schematic diagram of a connection table corresponding to the pins of the multiplexing channels and the I/O output ports after step S140 is executed in FIG. 1;
FIG. 5 is a block diagram of an embodiment of a slave board wiring of the HIL test system of the present application;
FIG. 6 is a block diagram of one embodiment of a prior art HIL test system wiring from a board.
Detailed Description
In order to make those skilled in the art better understand the technical solution of the present application, the method for wiring from a board and the HIL test system provided in the present application are further described in detail below with reference to the accompanying drawings and the detailed description.
Referring to fig. 1, fig. 1 is a schematic flowchart illustrating an embodiment of a board connection method of the HIL test system of the present application, which may specifically include the following steps:
s110: and obtaining the voltage and temperature sampling channel information of each AFE sampling chip according to the sampling channels of the AFE sampling chips in the first slave plate and the second slave plate and the electrical principle topological diagram.
The slave board wiring method of the HIL test System can be applied to a Battery Management System (BMS). The HIL test system may include a master board and at least two slave boards, illustrated in this embodiment as two slave boards, a first slave board and a second slave board.
The first slave board and the second slave board may include a plurality of identical AFE sampling chips therein, respectively. In this embodiment, the number of AFE sampling chips per slave board is 4. Different AFE sampling chips may differ in accuracy, resolution, range, and dynamic responsiveness, so the same AFE sampling chip may reduce errors.
The AFE sampling chip may include several pins, and one pin of the AFE sampling chip may serve as one sampling channel.
The electrical principle topological diagram can be understood as the corresponding relation between each AFE sampling chip in the slave board and the sampling objects such as temperature, voltage and the like. The corresponding relationship may be different according to different items.
Furthermore, according to naming rules of the voltage and temperature sampling channels, naming pins of each AFE sampling chip so as to obtain voltage and temperature sampling channel information of each AFE sampling chip; wherein, the naming rule is as follows: from the board number _ AFE sampling chip number _ pin number _ vendor, e.g., CMC1_ X2_7_ AFE2_ GND.
It should be noted that each AFE sampling chip includes two sampling channels, namely a voltage sampling channel and a temperature sampling channel, which can be embodied in the number of pins, and the definition is different according to different items. According to the naming rule of the embodiment, the voltage sampling channel and the temperature sampling channel are named as a kind to form a standard output.
S120: and confirming the multiplexing mode of the sampling channel according to the set multiplexing principle and the voltage and temperature sampling channel information to form a multiplexing channel.
The set multiplexing principle may include the following two:
1) the same number of different AFE sampling chips may share one I/O output port.
2) If only a bus copper plate is bridged between two sampling channels of the same AFE sampling chip, the two sampling channels share one I/O output port.
It should be noted that, the sampling channel connected across the bus copper plate has only a few mV of sampling voltage, and has no practical significance in the HIL test system, so the I/O output ports can be shared.
Referring to fig. 2, fig. 2 is a schematic diagram illustrating a channel multiplexing manner after step S120 is executed in fig. 1. As can be seen, a total of 8 AFE sampling chips of two slave boards can be divided into three multiplexed channels.
S130: pins of the I/O outlet are named and ordered.
The naming of the pins of the I/O output port can refer to the design and construction modes of I/O boards of different HIL test systems, but the rules for naming the pins of the I/O output port need to include the following two rules:
1) determined as either a voltage sample or a temperature sample.
The purpose is to make the named pins of the I/O output port clearly express as voltage sampling or temperature sampling.
2) The sequence number is included in the naming, which follows the principle of increasing one by one starting from 0.
The rules for ordering pins of the I/O outlet include the following three:
1) progressively increase one by one according to the name.
2) The next connector is spliced to the previous connector when the previous connector is full.
3) The sequence number does not jump and miss.
Referring to fig. 3, fig. 3 is a schematic diagram illustrating naming and ordering of pins of the I/O output port after step S130 is executed in fig. 1. As can be seen, a total of three I/O outlets are included.
S140: and connecting the multiplexing channel with the corresponding pin of the I/O output port according to the electrical principle topological diagram.
Wherein the following principles also need to be followed in this step: and gradually increasing the number of pins of the I/O output port corresponding to the multiplexing channel one by one for filling, finally obtaining a schematic diagram of a connection table, and then connecting according to the connection table.
Referring to fig. 4, fig. 4 is a schematic diagram of a pin mapping connection table of the multiplexing channel and the I/O output port after step S140 is executed in fig. 1. As can be seen from the figure, the sampling channels of the AFE sampling chips of the first slave board and the second slave board form three multiplexing channels in total, and each multiplexing channel corresponds to one I/O output port.
The embodiment provides a slave board wiring method of an HIL test system, which includes: obtaining voltage and temperature sampling channel information of each AFE sampling chip according to sampling channels of the AFE sampling chips in the first slave plate and the second slave plate and an electrical principle topological graph; confirming the multiplexing mode of the sampling channel according to the set multiplexing principle and the voltage and temperature sampling channel information to form a multiplexing channel; naming and sequencing pins of an I/O output port; and connecting the multiplexing channel with the corresponding pin of the I/O output port according to the electrical principle topological diagram. Compared with the prior art that each slave board sampling channel independently occupies one I/O output port, the voltage and temperature loops which need to be redesigned from the slave board can be reduced through reasonable and scientific multiplexing of the slave board wiring of the HIL test system, so that the structural design of the slave board HIL test system is simplified, and the cost is saved.
Based on the slave board wiring method of the HIL test system, the application also provides the HIL test system. Referring to fig. 5, fig. 5 is a schematic structural diagram of an embodiment of a slave board connection line of the HIL test system of the present application.
In this embodiment, the HIL test system 500 may include a master board BMS, a first slave board CMC1, a second slave board CMC2, a number of connectors, and a number of I/O output ports 110.
Wherein the main board BMS may include three chips, which are a chip a1, a chip a2, and a chip C, respectively. The first slave board CMC1 and the second slave board CMC2 may include four AFE sampling chips, respectively, chip X1, chip X2, chip X3, and chip X4. Chip a2 of the main board BMS connects chip X4 of the first slave board CMC1 and chip X1 of the second slave board CMC2, respectively. The AFE sampling chips in the first slave board CMC1 and the second slave board CMC2 may be the same.
In this embodiment, the I/O output port 110 may include a male connector and a female connector, wherein the female connector may be connected to an I/O board; the male connector may be connected to the main board BMS or the slave board through a connector.
Alternatively, the model of the I/O outlet 110 connected to the master board BMS may be different from the model of the I/O outlet 110 connected to the slave board, and the model of the I/O outlet 110 connected to the slave board may be the same.
Note that three chips of the main board BMS are connected to two male terminals through the connectors a and B, and a total of eight chips of the first slave board CMC1 and the second slave board CMC2 are connected to three male terminals through the connectors 1, 2, and 3. In this embodiment, because the sampling channels are multiplexed, the same connector may include both the sampling channels of the first slave plate AFE sampling chip and the sampling channels of the second slave plate AFE sampling chip.
Specifically, the first slave board CMC1 and the second slave board CMC2 are provided with several AFE sampling chips, which include sampling channels; the first slave plate CMC1 and the second slave plate CMC2 are connected with the I/O board card through an I/O output port 110, and the I/O output port 110 is arranged according to the name; the sampling channels form multiplexing channels according to a set multiplexing principle, and the multiplexing channels are connected with the I/O output ports 110 in a one-to-one correspondence manner according to an electrical principle topological diagram.
The pins of the AFE sampling chip include the nomenclature, which is: from plate number _ AFE sampling chip number _ pin number _ vendor.
Optionally, the set multiplexing principle includes the following:
1) the same numbers of different AFE sampling chips share one I/O output port 110;
2) only a bus copper plate is bridged between the two sampling channels of the same AFE sampling chip, and the two sampling channels share one I/O output port 110.
Optionally, the naming convention for the I/O egress 110 may include the following:
1) determining as a voltage sample or a temperature sample;
2) the sequence number is included in the naming, which follows the principle of increasing one by one starting from 0.
Optionally, the ordering rules of the I/O outlets 110 may include the following:
1) gradually increasing according to the name;
2) the next connector is spliced after the previous connector is fully arranged;
3) the sequence number does not jump and miss.
Referring to fig. 6, fig. 6 is a schematic structural diagram of an embodiment of a board connection line of a HIL test system in the prior art. In the prior art, each sampling channel from the board needs to occupy one I/O output port individually. As can be seen, the same connector in the prior art can only connect the first slave plate AFE sampling chip or the second slave plate AFE sampling chip. And according to the wiring method of the prior art, a total of 4I/O output ports are required.
And every time after the project is switched and iterated, the slave plate HIL test wiring harness is required to be re-manufactured according to the slave plate definitions of different projects, more than 200 loops are required to be re-designed and manufactured, and every time after the project is switched and iterated, the HIL test system environment is required to be re-built according to the slave plate definitions, so that great time cost and labor consumption are brought, and the project is not favorable for quick switching.
The HIL test system slave board adopts a multichannel multiplexing wiring scheme, and compared with the prior art that each slave board sampling channel independently occupies one I/O output port, the HIL test system slave board can reduce the voltage and temperature loops which need to be redesigned, only 3I/O output ports are needed, so that the structural design of the HIL test system slave board is more reasonable, more than 100 sampling channels can be saved in each project, the cost of a wire harness and the cost of a rack I/O board card are saved, and meanwhile, the project can be rapidly switched.
It is to be understood that the specific embodiments described herein are merely illustrative of the application and are not limiting of the application. In addition, for convenience of description, only a part of structures related to the present application, not all of the structures, are shown in the drawings. The step numbers used herein are also for convenience of description only and are not intended as limitations on the order in which the steps are performed. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
The terms "first", "second", etc. in this application are used to distinguish between different objects and not to describe a particular order. Furthermore, the terms "include" and "have," as well as any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those steps or elements listed, but may alternatively include other steps or elements not listed, or inherent to such process, method, article, or apparatus.
Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the application. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. It is explicitly and implicitly understood by one skilled in the art that the embodiments described herein can be combined with other embodiments.
The above description is only for the purpose of illustrating embodiments of the present application and is not intended to limit the scope of the present application, and all modifications of equivalent structures and equivalent processes, which are made by the contents of the specification and the drawings of the present application or are directly or indirectly applied to other related technical fields, are also included in the scope of the present application.
Claims (10)
1. A method of slave board wiring for an HIL test system, comprising:
obtaining voltage and temperature sampling channel information of each AFE sampling chip according to sampling channels of the AFE sampling chips in the first slave plate and the second slave plate and an electrical principle topological graph;
confirming the multiplexing mode of the sampling channel according to a set multiplexing principle and the voltage and temperature sampling channel information to form a multiplexing channel;
naming and sequencing pins of an I/O output port;
and connecting the multiplexing channel with the corresponding pin of the I/O output port according to the electrical principle topological diagram.
2. The slave plate wiring method according to claim 1, wherein the first slave plate and the second slave plate respectively include therein a plurality of identical AFE sampling chips;
the obtaining of the voltage and temperature sampling channel information of each AFE sampling chip according to the sampling channels of the AFE sampling chips in the first slave board and the second slave board and the electrical principle topological diagram includes:
naming pins of each AFE sampling chip according to naming rules of voltage and temperature sampling channels, so that voltage and temperature sampling channel information of each AFE sampling chip is obtained; wherein the naming rule is as follows: from plate number _ AFE sampling chip number _ pin number _ vendor.
3. The slave board wiring method according to claim 1, wherein the set multiplexing rule comprises:
the same serial numbers of different AFE sampling chips share one I/O output port;
and only a confluence copper plate is bridged between the two sampling channels of the same AFE sampling chip, so that the two sampling channels share one I/O output port.
4. A method of wiring from a board according to any of claims 1 to 3, wherein the naming of the pins of the I/O outlets comprises:
determining as a voltage sample or a temperature sample;
sequence numbers are included in the nomenclature that follows the principle of increasing one by one starting from 0.
5. The method of claim 4, wherein the ordering pins of the I/O outlets comprises:
gradually increasing according to the name;
the next connector is spliced after the previous connector is fully arranged;
the sequence numbers do not hop or miss.
6. An HIL test system, applied to a battery management system, the HIL test system comprising:
a first slave plate and a second slave plate, the first slave plate and the second slave plate being provided with several AFE sampling chips, the AFE sampling chips comprising sampling channels;
the first slave plate and the second slave plate are connected with an I/O board card through the I/O output ports, and the I/O output ports are sorted according to names;
the sampling channels form multiplexing channels according to a set multiplexing principle, and the multiplexing channels are connected with the I/O output ports in a one-to-one correspondence mode according to an electrical principle topological diagram.
7. The HIL test system according to claim 6, wherein the first slave board and the second slave board each include therein a plurality of identical AFE sampling chips;
the pins of the AFE sampling chip comprise names, and the naming rule is as follows: from plate number _ AFE sampling chip number _ pin number _ vendor.
8. The HIL test system according to claim 6, wherein the set multiplexing principle includes:
the same serial numbers of different AFE sampling chips share one I/O output port;
and only a confluence copper plate is bridged between the two sampling channels of the same AFE sampling chip, so that the two sampling channels share one I/O output port.
9. The HIL test system according to any one of claims 6 to 8, wherein the naming convention for the I/O outlets includes:
determining as a voltage sample or a temperature sample;
sequence numbers are included in the nomenclature that follows the principle of increasing one by one starting from 0.
10. The HIL test system of claim 9, wherein the rules for ordering of the I/O outlets include:
gradually increasing according to the name;
after the previous connector is fully arranged, the next connector is spliced;
the sequence numbers do not hop or miss.
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