CN114822413A

CN114822413A - Pixel circuit, pixel driving method and display device

Info

Publication number: CN114822413A
Application number: CN202210504292.7A
Authority: CN
Inventors: 樊涛; 康报虹
Original assignee: HKC Co Ltd; Mianyang HKC Optoelectronics Technology Co Ltd
Current assignee: HKC Co Ltd; Mianyang HKC Optoelectronics Technology Co Ltd
Priority date: 2022-05-10
Filing date: 2022-05-10
Publication date: 2022-07-29

Abstract

The disclosure relates to a pixel circuit, a pixel driving method and a display device. The pixel circuit comprises a light-emitting element, a first capacitor, a second capacitor and a driving transistor, wherein a first switching element is used for responding to a first control signal so as to apply a first power supply signal to a first end of the first capacitor; a second switching element for responding to a second control signal to connect the control terminal of the driving transistor with the second terminal of the driving transistor and the first terminal of the second capacitor, respectively; a third switching element for connecting the second terminal of the driving transistor with the second power supply signal in response to a third control signal; the fourth switching element is used for responding to the first control signal so as to apply the data signal to the second end of the second capacitor. The second end of the first capacitor, the first end of the second capacitor and the control end of the driving transistor are connected; the first end of the light-emitting element is connected with the first power supply signal, and the second end of the light-emitting element is connected with the first end of the driving transistor. The display uniformity can be improved.

Description

Pixel circuit, pixel driving method and display device

Technical Field

The disclosure belongs to the technical field of display, and particularly relates to a pixel circuit, a pixel driving method and a display device.

Background

An AMOLED (Active Matrix/Organic Light Emitting Diode) has advantages of self-luminescence, low power consumption, wide viewing angle, high color gamut, high contrast, and fast response.

Currently, in an OLED display panel, the luminance of an OLED light emitting device is mainly determined by the magnitude of its driving current, and the larger the current is, the larger the luminance is. However, the OLED driving current is very unstable, and thus the display effect of the display panel is affected.

Disclosure of Invention

The present disclosure provides a pixel circuit, a pixel driving method, and a display device, which can improve display uniformity.

A first aspect of the present disclosure provides a pixel circuit, including a light emitting element, a first capacitor, a second capacitor, a driving transistor, a first switch element, a second switch element, a third switch element, and a fourth switch element, where a control terminal of the first switch element is configured to receive a first control signal, a first terminal of the first switch element is configured to receive a first power signal, and a second terminal of the first switch element is connected to a first node, so as to apply the first power signal to the first terminal of the first capacitor;

the control end of the second switch element is used for receiving a second control signal, the first end is connected with the second node, and the second end is connected with the third node so as to connect the control end of the driving transistor with the second end of the driving transistor;

the third switching element has a control terminal for receiving a third control signal, a first terminal connected to the third node, and a second terminal for receiving a second power signal to connect the second terminal of the driving transistor to the second power signal;

the control terminal of the fourth switching element is used for receiving the first control signal, the first terminal of the fourth switching element is used for receiving a data signal, and the second terminal of the fourth switching element is connected with the second terminal of the second capacitor so as to apply the data signal to the second terminal of the second capacitor;

the second end of the first capacitor, the first end of the second capacitor and the control end of the driving transistor are connected to the second node;

the first end of the light emitting element is used for receiving the first power supply signal, and the second end of the light emitting element, the first end of the first capacitor and the first end of the driving transistor are connected to the first node.

In an exemplary embodiment of the present disclosure, the first, second, third and fourth switching elements respectively include a first transistor, a second transistor, a third transistor and a fourth transistor; wherein,

in a sampling phase, the first transistor, the second transistor and the fourth transistor are in a conducting state, and the third transistor is in a turn-off state;

in a data input stage, the first transistor and the fourth transistor are in a conducting state, and the second transistor and the third transistor are in a turn-off state;

in a light emitting stage, the third transistor is in an on state, and the first transistor, the second transistor, and the fourth transistor are in an off state.

In one exemplary embodiment of the present disclosure, the driving transistor and the first, second, third, and fourth transistors are all oxide thin film transistors.

In an exemplary embodiment of the present disclosure, the driving transistor and the first, second, third, and fourth transistors are all P-type thin film transistors.

In an exemplary embodiment of the present disclosure, the light emitting element is an organic light emitting diode, an anode of the organic light emitting diode is configured to receive the first power signal, and a cathode of the organic light emitting diode is connected to the first node.

A second aspect of the present disclosure provides a pixel driving method for driving the pixel circuit as described above, the pixel driving method including:

in a sampling phase, the first switching element and the fourth switching element are turned on by the first control signal, the second switching element is turned on by the second control signal, and simultaneously, the third switching element is turned off by the third control signal;

in a data input stage, turning on the first switching element and the fourth switching element with the first control signal, while turning off the second switching element with the second control signal and turning off the third switching element with the third control signal;

in a light emitting phase, the third switching element is turned on by the third control signal, and at the same time, the first switching element and the fourth switching element are turned off by the first control signal, and the second switching element is turned off by the second control signal.

In another exemplary embodiment of the present disclosure, the first power signal is a dc high level signal, and the second power signal is a dc low level signal; wherein,

in the sampling phase, the first control signal and the second control signal are at a low level, and the third control signal is at a high level;

in the data entry phase; the first control signal is at a low level, and the second control signal and the third control signal are at a high level;

in the light emitting phase, the third control signal is at a low level, and the first control signal and the second control signal are at a high level.

in the sampling phase, the first control signal and the second control signal are at a high level, and the third control signal is at a low level;

in the data entry phase; the first control signal is at a high level, and the second control signal and the third control signal are at a low level;

in the light emitting phase, the third control signal is at a high level, and the first control signal and the second control signal are at a low level.

A third aspect of the present disclosure provides a display device including a substrate having a display area and a plurality of pixel groups located in the display area, the pixel groups including:

the pixel circuit as described above;

a first power supply signal line electrically connected to the first switching element and the light emitting element, for supplying the first power supply signal;

a first control signal line electrically connected to the first switching element and the fourth switching element for providing the first control signal;

a second control signal line electrically connected to the second switching element for supplying the second control signal;

a third control signal line electrically connected to the third switching element, for providing the third control signal;

a data signal line electrically connected to the fourth switching element for providing the data signal;

and a second power supply signal line electrically connected to the third switching element for supplying a second power supply signal.

In still another exemplary embodiment of the present disclosure, the substrate further has a non-display region disposed around the display region;

the display device further comprises a gate driving circuit located in the non-display area, and the gate driving circuit is connected with the first control signal line, the second control signal line and the third control signal line.

The scheme disclosed by the invention has the following beneficial effects:

the pixel circuit, the pixel driving method and the display device can be used for realizing pixel compensation. The pixel circuit comprises a light-emitting element, a first capacitor, a second capacitor, a driving transistor, a first switching element, a second switching element, a third switching element and a fourth switching element, wherein the four switching elements and the driving transistor are controlled to be switched on or switched off by scanning signals to realize the circuit sampling stage and dataAn input stage and a light emitting stage; the pixel circuit can reduce the threshold voltage V in the light-emitting stage _th And the influence of the voltage drop of the power supply voltage on the driving current, so that the problem of uneven brightness of the light-emitting element can be reduced, and the picture display effect can be improved.

Additional features and advantages of the disclosure will be set forth in the detailed description which follows, or in part will be obvious from the description, or may be learned by practice of the disclosure.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and together with the description, serve to explain the principles of the disclosure. It should be apparent that the drawings in the following description are merely examples of the disclosure and that other drawings may be derived by those of ordinary skill in the art without inventive effort.

Fig. 1 illustrates a module connection diagram of the pixel circuit provided in an embodiment of the present disclosure;

fig. 2 is a schematic diagram of the pixel circuit provided in the first embodiment of the disclosure;

fig. 3 is a schematic flow chart illustrating the pixel driving method provided in the second embodiment of the present disclosure;

FIG. 4 is a schematic diagram showing a driving timing of the pixel circuit of FIG. 2;

fig. 5 shows an equivalent circuit diagram of the pixel circuit of fig. 2 in a sampling phase;

fig. 6 shows an equivalent circuit diagram of the pixel circuit in fig. 2 at a data input stage;

fig. 7 shows an equivalent circuit diagram of the pixel circuit in fig. 2 in a light-emitting stage;

fig. 8 shows a connection diagram of the display area and the non-display area provided in the third embodiment.

Description of reference numerals:

11. a first switching element; 12. a second switching element; 13. a third switching element; 14. a fourth switching element; t5, drive transistor; l, a light-emitting element; c1, a first capacitance; c2, a second capacitor; t1, a first transistor; t2, a second transistor; t3, a third transistor; t4, a fourth transistor; SEL1, a first control signal; SEL2, second control signal; SEL3, third control signal; VDD, a first power supply signal; vdata, a data signal; A. a first node; B. a second node; C. a third node; t1, sampling phase; t2, data input stage; t3, light emitting stage; 100. a display area; 200. a non-display area.

Detailed Description

Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art.

In the present disclosure, the terms "first", "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present disclosure, "a plurality" means two or more unless specifically limited otherwise.

In the present disclosure, unless expressly stated or limited otherwise, the terms "mounted," "connected," and the like are to be construed broadly and can include, for example, fixed connections, removable connections, or integral connections; can be mechanically or electrically connected; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meaning of the above terms in the present disclosure can be understood by those of ordinary skill in the art as appropriate.

Furthermore, the described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of embodiments of the disclosure. One skilled in the relevant art will recognize, however, that the subject matter of the present disclosure can be practiced without one or more of the specific details, or with other methods, components, devices, steps, and so forth. In other instances, well-known methods, devices, implementations, or operations have not been shown or described in detail to avoid obscuring aspects of the disclosure.

Example one

The embodiment of the present disclosure provides a pixel circuit for implementing pixel compensation, as shown in fig. 1, the pixel circuit includes a light emitting element L, a first capacitor C1, a second capacitor C2, a driving transistor T5, and a first switching element 11, a second switching element 12, a third switching element 13, and a fourth switching element 14.

It is understood that the light emitting element L, the first capacitor C1 and the second capacitor C2 each have a first terminal and a second terminal, and the driving transistor T5 has a control terminal in addition to the first terminal and the second terminal.

The relationship among the first switching element 11, the second switching element 12, the third switching element 13, and the fourth switching element 14, the light emitting element L, the first capacitor C1, the second capacitor C2, and the driving transistor T5 is as follows.

A first switching element 11 for responding to a first control signal SEL1 to apply a first power signal VDD to a first terminal of the first capacitor C1;

a second switching element 12 for connecting the control terminal of the driving transistor T5 with the second terminal of the driving transistor T5 in response to a second control signal SEL 2;

and a third switching element 13 for connecting the second terminal of the driving transistor T5 with the second power signal in response to a third control signal SEL 3.

And a fourth switching element 14 for responding to the first control signal SEL1 to apply the data signal Vdata to the second terminal of the second capacitor C2.

It should be noted that, referring to fig. 1, the second terminal of the first capacitor C1 and the first terminal of the second capacitor C2 are connected to the control terminal of the driving transistor T5; a first terminal of the light emitting element L is connected to the first power signal VDD, and a second terminal of the light emitting element L is connected to a first terminal of the driving transistor T5.

In the embodiment of the present disclosure, the four switching elements and the driving transistor T5 are controlled to be turned on or off by three control signals, so that the sampling period T1, the data input period T2, and the light emitting period T3 can be entered; the pixel circuit can reduce the threshold voltage of the driving transistor T5 and the influence of the voltage drop of the power line voltage on the driving current in the light-emitting stage T3, can ensure the uniform brightness of the light-emitting element L, enhance the display picture effect, and can reduce the damage to the light-emitting element L, thereby prolonging the service life of the light-emitting element L.

For example, referring to fig. 1, the first control signal SEL1 is provided by a first control line, the second control signal SEL2 is provided by a second control signal line, and the third control signal SEL3 is provided by a third control signal line; the data signal Vdata is supplied from a data signal line.

For example, referring to fig. 2, the first switching element 11 includes a first transistor T1, the second switching element 12 includes a second transistor T2, the third switching element 13 includes a third transistor T3, and the fourth switching element 14 includes a fourth transistor T4.

It should be understood that the first transistor T1, the second transistor T2, the third transistor T3, and the fourth transistor T4 all have a first terminal, a second terminal, and a control terminal, like the driving transistor T5. The control terminal of each transistor corresponds to the gate of the transistor, one of the first terminal and the second terminal corresponds to the source of the transistor, and the other corresponds to the drain of the transistor.

Illustratively, the driving transistor T5, the first transistor T1, the second transistor T2, the third transistor T3 and the fourth transistor T4 of the embodiments of the present disclosure may all be oxide thin film transistors, that is: the active layer of each transistor may be made of an Oxide, for example, a metal Oxide material such as IZGO (Indium Gallium Zinc Oxide) or an a-Si (amorphous silicon) thin film transistor may be used, and the active layer may be designed according to different embodiments.

For example, each transistor may be of the bottom-gate type, i.e.: the gate of the transistor is located below the active layer (on the side close to the glass substrate) to enable proper thinning of the product, but is not limited thereto, and each transistor may also be of a top gate type, as the case may be.

In addition, each transistor may be an enhancement type transistor or a depletion type transistor, which is not particularly limited in the embodiments of the present disclosure.

For example, all transistors in the pixel circuit may be P-type thin film transistors, that is: the driving transistor T5, the first transistor T1, the second transistor T2, the third transistor T3 and the fourth transistor T4 may all be P-type thin film transistors, and the driving voltage of each transistor corresponds to a low level voltage; the first power signal VDD may be a dc high level signal, and the second power signal VDD may be a dc low level signal.

It should be understood that the transistors in the pixel circuit are not limited to the aforementioned P-type thin film transistors, but may be all N-type thin film transistors, or may be partially P-type thin film transistors and partially N-type thin film transistors. When the transistor is an N-type transistor, the driving voltage thereof may correspond to a high level voltage.

Illustratively, the light emitting element L may be a current-driven type light emitting element L which is controlled to emit light by a current flowing through the driving transistor T5, for example: the light emitting device L may be an Organic Light Emitting Diode (OLED), that is, the pixel circuit may be applied to an OLED display device. The first end of the light emitting element L is an anode of the OLED, and the second end of the light emitting element L is a cathode of the OLED.

The connection relationship between the structures in the pixel circuit will be described in detail with reference to fig. 2, in which the transistors are P-type thin film transistors, the first power signal VDD is a dc high level signal, the second power signal VDD is a dc low level signal, the first end of the light emitting element L is an anode of the OLED, and the second end of the light emitting element L is a cathode of the OLED.

The first switching element 11, the second switching element 12, the third switching element 13, and the fourth switching element 14 respectively include a first transistor T1, a second transistor T2, a third transistor T3, and a fourth transistor T4; wherein,

the first transistor T1 has a control terminal for receiving a first control signal SEL1, a first terminal for receiving a first power signal VDD, and a second terminal connected to the first node a.

The second transistor T2 has a control terminal for receiving a second control signal SEL2, a first terminal connected to the second node B, and a second terminal connected to the third node C.

A control terminal of the third transistor T3 is for receiving a third control signal SEL3, a first terminal is connected to the third node C, and a second terminal is for receiving a second power signal.

The control terminal of the fourth transistor T4 is for receiving the first control signal SEL1, the first terminal is for receiving the data signal Vdata, and the second terminal is connected to the second terminal of the second capacitor C2.

The first capacitor C1 has a first terminal connected to the first node a and a second terminal connected to the second node B. The second capacitor C2 has a first terminal connected to the second node B and a second terminal connected to the second terminal of the fourth transistor T4. The first terminal of the light emitting element L is used for receiving the first power signal VDD, the second terminal is connected to the first node a, that is, the anode of the light emitting element L is used for receiving the first power signal VDD, and the cathode is connected to the first node a.

That is, the second terminal of the first transistor T1, the first terminal of the first capacitor C1, the second terminal of the light emitting element L, and the first terminal of the driving transistor T5 are all connected to the first node a; the second terminal of the first capacitor C1, the control terminal of the driving transistor T5, the first terminal of the second transistor T2 and the first terminal of the second capacitor C2 are all connected to the second node B; the second terminal of the driving transistor T5, the second terminal of the second transistor T2, and the first terminal of the third transistor T3 are all connected to a third node C.

In the sampling period T1, the first transistor T1, the second transistor T2, and the fourth transistor T4 are turned on, the third transistor T3 is turned off, and no current flows through the light emitting element L; in the data input stage T2, the first transistor T1 and the fourth transistor T4 are in an on state, the second transistor T2 and the third transistor T3 are in an off state, and no current flows through the light emitting element L; in the light emitting period T3, the third transistor T3 is turned on, the first transistor T1, the second transistor T2, and the fourth transistor T4 are turned off, and the light emitting element L emits light.

Based on this, the pixel circuit of the embodiment of the present disclosure adopts a 5T2C structure to realize the circuit sampling phase T1, the data input phase T2, and the light emitting phase T3. Therefore, the pixel circuit has a compensation effect on the voltage drop of the threshold voltage and the power supply voltage, the influence of the threshold voltage and the power supply voltage on the driving current is reduced, the brightness uniformity of the light-emitting element L can be further ensured, and the picture display effect is improved.

Example two

Referring to fig. 3 and 4, based on the pixel circuit mentioned in the first embodiment, a second embodiment of the disclosure further provides a pixel driving method, where the pixel driving method may include:

in step S100, in the sampling period t1, the first switch element 11 and the fourth switch element 14 are turned on by the first control signal SEL1, the second switch element 12 is turned on by the second control signal SEL2, and the third switch element 13 is turned off by the third control signal SEL 3.

In step S200, in the data input stage t2, the first switch element 11 and the fourth switch element 14 are turned on by the first control signal SEL1, the second switch element 12 is turned off by the second control signal SEL2, and the third switch element 13 is turned off by the third control signal SEL 3.

In step S300, in the light emitting period t3, the third switching element 13 is turned on by the third control signal SEL3, the first switching element 11 and the fourth switching element 14 are turned off by the first control signal SEL1, and the second switching element 12 is turned off by the second control signal SEL 2.

The pixel driving method (i.e., operation) corresponding to the pixel circuit shown in fig. 2 will be described in detail with reference to the operation timing diagram of the pixel circuit shown in fig. 4.

The operation timing diagram of the pixel circuit shown in fig. 4 shows the level states of the first control signal SEL1, the second control signal SEL2, the third control signal SEL3 and the data signal Vdata in three periods, and also shows whether the current flows through the light emitting element L in three periods. Fig. 4 corresponds to a level state when the driving transistor T5 and the first, second, third and fourth transistors T1, T2, T3 and T4 are P-type transistors.

Referring collectively to fig. 4 and 5, during the sampling phase t 1: the first control signal SEL1 and the second control signal SEL2 are low, and the third control signal SEL3 is high; the first transistor T1, the second transistor T2, and the fourth transistor T4 are turned on, and at the same time, the third transistor T3 is turned off, the data signal Vdata is at a high level, and the voltage is zero, that is, no data signal Vdata is input; in other embodiments, when the first transistor T1, the second transistor T2, the third transistor T3, and the fourth transistor T4 are N-type transistors, the first control signal SEL1 and the third control signal SEL3 are at a high level, and the second control signal SEL2 is at a low level.

At this stage, since the first control signal SEL1 is at a low level, the first transistor T1 is turned on, and the first node a writes the voltage of the first power signal VDD such that the voltage of the first node a is equal to the voltage of the first power signal VDD. Since the third control signal SEL3 is at a high level and the third transistor T3 is turned off, no current flows through the light emitting element L, and the light emitting element L is not shown. Moreover, since the second control signal SEL2 is at a low level, the second transistor T2 is turned on, and the second node B and the third node C are shorted, and since the control terminal of the driving transistor T5 is connected to the second node B, the second terminal of the driving transistor T5 is connected to the third node C, that is, the control terminal and the second terminal of the driving transistor T5 are shorted to form a diode connection structure, the second node B is charged through the first capacitor C1 and the second capacitor C2, that is, the control terminal of the driving transistor T5 is charged until the voltage of the first capacitor C1 and the threshold voltage V of the driving transistor T5 reach a low level _th Are equal. In addition, the first terminal of the first capacitor C1 is connected to the first node a, and the second terminal is connected to the second node B, so the voltage of the first capacitor C1 is equal to the voltage of the second node B minus the voltage of the first node a. The specific voltages are as follows: v _A ＝Vdd，V _c1 ＝V _B -V _A ，V _c1 ＝V _th (ii) a That is, the V _B ＝V _th +Vdd。

Referring to fig. 4 and 6 in combination, during the data input stage t2, the first control signal SEL1 is at a low level, and the second control signal SEL2 and the third control signal SEL3 are at a high level; the first transistor T1 and the fourth transistor T4 are made to be turned on, and at the same time, the second transistor T2 and the third transistor T3 are made to be turned off; in other embodiments, when the first transistor T1, the second transistor T2, the third transistor T3, and the fourth transistor T4 are N-type transistors, the first control signal SEL1 is at a high level, and the second control signal SEL2 and the third control signal SEL3 are at a low level.

At this stage, the data signal Vdata writes the data signal into the second node B through the fourth transistor T4, and the voltage of the second node B is divided by the capacitance coupling effect and the series connection of the first capacitor C1 and the second capacitor C2, so that a part of the data voltage is added to the voltage of the second node B. Moreover, since the first control signal SEL1 is at a low level, the first transistor T1 is still turned on, the first node a is continuously written with the first power signal VDD, and the voltage of the first capacitor C1 is continuously kept at the sampling voltage until the next frame data signal Vdata is inputted. And since the first transistor T1 is still turned on and the third transistor T3 is still turned off, no current flows through the voltage of the light emitting element L, and the light emitting element L does not display. The specific voltages are as follows:

V _c1 ＝V _B -V _A ，V _A vdd; that is to say

As shown with combined reference to fig. 4 and 7, in the light emitting period t3, the third control signal SEL3 is at a low level, and the first control signal SEL1, the second control signal SEL2 and the data signal Vdata are at a high level; the third transistor T3 is made to be turned on, and at the same time, the first transistor T1, the second transistor T2, and the fourth transistor T4 are made to be turned off; in other embodiments, when the first transistor T1, the second transistor T2, the third transistor T3, and the fourth transistor T4 are N-type transistors, the third control signal SEL3 is at a high level, and the first control signal SEL1 and the second control signal SEL2 are at a low level.

At this stage, the first power signal VDD flows in from the first terminal of the light emitting element L, and flows out from the second terminal to charge the light emitting element L, and a current flows through the light emitting element L to emit light. In addition, since the fourth transistor T4 is turned off, no data signal Vdata is written into the first capacitor C1, and thus the voltage of the first capacitor C1 maintains the voltage of the previous stage data input stage T2. The specific voltages are as follows: v _A ＝Vdd-V _OLED ，

That is to say

The driving current of the light emitting element L can be expressed by the following formula:

it should be noted that the control terminal, i.e., the gate voltage, of the driving transistor T5 is the voltage of the second node B, and the first terminal, i.e., the source voltage, of the driving transistor T5 is the voltage of the first node a, i.e., V _GS ＝V _B -V _A . Due to V _B ＝V _A +V _C1 ，V _A ＝Vdd-V _OLED (ii) a Therefore, the temperature of the molten metal is controlled,

therefore, the formula of the driving current is substituted to obtain

Where μ is the carrier mobility, W is the channel width of the TFT, L is the length of the TFT channel, C _GI Vdata is a data voltage inputted to the driving transistor T5 for the gate capacitance determined by the gate insulating layer thickness and material.

Based on this, it can be understood from the above-mentioned driving current calculation formula that the driving current of the light emitting element L is related only to the data voltage Vdata and the first capacitor C1 and the second capacitor C2, and the threshold voltage V is lowered _th And the effect of the supply voltage drop on the drive current.

In summary, in the exemplary embodiment, the driving current of the OLED and the threshold voltage V of the driving transistor T5 _th Voltage V of light emitting element L _OLED If the first power supply signal VDD is irrelevant, the shift of the threshold voltage of the driving transistor T5, the life degradation of the light emitting element L, and the difference of the first power supply signal VDD do not contribute to the driving current I _OLED The influence is generated, the uniformity and the stability of the driving current are ensured, so that the brightness of the OLED display device is more uniform, the generation of residual shadows is reduced, and the display effect is enhanced.

EXAMPLE III

The embodiment also provides a display device, which can be an OLED display device. The display device may include a substrate and a plurality of pixel groups (not shown), and the substrate may be made of glass, but not limited thereto, and may also be Polyimide (PI) as the case may be.

The substrate may have a display area 100, and a plurality of pixel groups are located in the display area 100. The pixel group may include a pixel circuit, and details of the first embodiment are specifically referred to, and will not be repeated herein. The pixel set may further include: a first power supply signal VDD line electrically connected to the first switching element 11 and the light emitting element L for supplying a first power supply signal VDD; a first control signal SEL1 line electrically connected to the first switching element 11 and the fourth switching element 14 for providing a first control signal SEL 1; a second control signal SEL2 line electrically connected to the second switching element 12 for providing a second control signal SEL 2; a third control signal SEL3 line electrically connected to the third switching element 13 for providing a third control signal SEL 3; a data signal line electrically connected to the fourth switching element 14 for supplying a data signal Vdata; and a second power signal line electrically connected to a second terminal of the third transistor T3 for supplying a second power signal.

Illustratively, the substrate also has a non-display region 200 disposed around the display region 100; the display device further includes a gate driving circuit in the non-display region 200, the gate driving circuit being connected to the first control signal SEL1 line, the second control signal SEL2 line, and the third control signal SEL3 line.

The display device of the embodiment of the disclosure can be an AMOLED (Active-matrix organic light-emitting diode) display, and has the advantages of thin body, power saving, bright color, strong image quality, and the like, and is widely applied. Such as: OLED televisions, mobile phones, notebook computer screens, etc., are gradually dominating in the field of flat panel displays.

In the description herein, references to the description of the terms "some embodiments," "exemplary," etc. mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or exemplary is included in at least one embodiment or exemplary of the present disclosure. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples and features of different embodiments or examples described in this specification can be combined and combined by one skilled in the art without contradiction.

Although embodiments of the present disclosure have been shown and described, it is understood that the above embodiments are exemplary and should not be construed as limiting the present disclosure, and that changes, modifications, substitutions and alterations can be made to the above embodiments by those of ordinary skill in the art within the scope of the present disclosure, and therefore all changes and modifications that are intended to be covered by the claims and the specification of this disclosure are within the scope of the patent disclosure.

Claims

1. A pixel circuit includes a light emitting element, a first capacitor, a second capacitor, a driving transistor, a first switching element, a second switching element, a third switching element, and a fourth switching element,

the first switch element has a control terminal for receiving a first control signal, a first terminal for receiving a first power signal, and a second terminal connected to a first node for applying the first power signal to a first terminal of the first capacitor;

2. The pixel circuit according to claim 1, wherein the first switching element, the second switching element, the third switching element, and the fourth switching element respectively include a first transistor, a second transistor, a third transistor, and a fourth transistor; wherein,

3. The pixel circuit according to claim 2, wherein the driving transistor and the first, second, third, and fourth transistors are each an oxide thin film transistor.

4. The pixel circuit according to claim 3, wherein the driving transistor and the first, second, third, and fourth transistors are each a P-type thin film transistor.

5. The pixel circuit according to claim 4, wherein the light emitting element is an organic light emitting diode, an anode of the organic light emitting diode is configured to receive the first power signal, and a cathode of the organic light emitting diode is connected to the first node.

6. A pixel driving method for driving the pixel circuit according to claim 1, the pixel driving method comprising:

in a data input stage, turning on the first switching element and the fourth switching element with the first control signal, and simultaneously, turning off the second switching element with the second control signal and turning off the third switching element with the third control signal;

7. The pixel driving method according to claim 6, wherein the first power supply signal is a dc high level signal, and the second power supply signal is a dc low level signal; wherein,

8. The pixel driving method according to claim 6, wherein the first power supply signal is a dc high level signal, and the second power supply signal is a dc low level signal; wherein,

9. A display device comprising a substrate having a display area and a plurality of pixel groups located in the display area, the pixel groups comprising:

the pixel circuit according to claim 1;

10. The display device according to claim 9,

the substrate is also provided with a non-display area arranged around the display area;