CN114826163A - Low-power-consumption high-performance trigger based on sensitive amplifier and working method thereof - Google Patents

Abstract

The invention discloses a low-power-consumption high-performance trigger based on a sensitive amplifier and a working method thereof, wherein the trigger comprises a trigger main stage and a trigger slave stage; wherein, the flip-flop primary includes: the device comprises a pre-charging part, an RAM-like structure, a data input part, a switch tube and a short-circuit tube; the flip-flop slave stage comprises two inverters inv3, inv4 and one C-cell. The invention can greatly reduce the possibility of generating burrs inside the trigger so as to reduce the power consumption; the dependence of Q and QB can be eliminated, so that the running speed is improved; meanwhile, the influence of an external load on the performance of the trigger can be greatly reduced.

Description

Low-power and high-performance flip-flop based on sense amplifier and its working method

technical field

The invention belongs to the technical field of integrated circuits, in particular to a low-power-consumption and high-performance trigger based on a sense amplifier and an implementation method thereof.

Background technique

In recent years, with the continuous development of semiconductor technology, the feature size of integrated circuits has been continuously reduced, and the power consumption of chips has also increased. The power consumption of chips has become the main factor restricting the development of integrated circuits. The increase in power consumption is not conducive to portable The use of the device and the problem of insufficient heat dissipation caused by the increase in power consumption may cause the chip to not work properly, so it is particularly important to reduce the power consumption of the integrated circuit. The flip-flop is the basic unit of the digital circuit. The power consumption of the flip-flop accounts for about 30% to 50% of the total power consumption of the digital circuit. Frequent flipping of the flip-flop or internal glitches will greatly increase the power consumption of the chip. As a result, the function of the chip cannot be realized normally; at the same time, the flip-flop is the basic component of the digital circuit, and the speed of the flip-flop greatly restricts the overall speed of the chip. Therefore, inventing a flip-flop with low power consumption and high performance has become an urgent problem to be solved in the field of integrated circuits.

SUMMARY OF THE INVENTION

In order to solve the above-mentioned shortcomings of the prior art, the present invention proposes a low-power and high-performance trigger based on a sense amplifier and a working method thereof, so as to greatly reduce the trigger speed while ensuring the speed requirement of the trigger. It can reduce the power consumption of the device and the possibility of internal glitches, and can get rid of the dependence of Q and QB, so that the running speed is improved; and the external capacitive load can be isolated from the internal trigger to improve the anti-interference ability of the trigger.

The present invention adopts the following technical scheme in order to achieve the above-mentioned purpose of the invention:

The features of the low-power-consumption and high-performance trigger based on the sense amplifier of the present invention include: a trigger master stage and a trigger slave stage;

The main stage of the trigger includes: a data input part, a precharge part, a RAM-like structure, a short-circuit tube, and a switch tube;

The data input part includes: a second NMOS transistor N2 and a fourth NMOS transistor N4;

The precharging part includes: a first PMOS transistor P1 and a second PMOS transistor P2;

The RAM-like structure is composed of two cross-coupled inverters, and includes: a third PMOS transistor P3, a fourth PMOS transistor P4, a third NMOS transistor N3, and a fifth NMOS transistor N5; The first inverter inv1 is composed of the tube P3 and the third NMOS tube N3; the second inverter inv2 is composed of the fourth PMOS tube P4 and the fifth NMOS tube N5;

The short-circuit tube is the sixth NMOS tube N6;

The switch tube is a first NMOS tube N1;

The flip-flop slave stage includes: the third inverter inv3 and the fourth inverter inv4 and 1 C unit;

The third inverter inv3 is composed of a seventh PMOS transistor P7 and a ninth NMOS transistor N9;

The fourth inverter inv4 is composed of an eighth PMOS transistor P8 and a tenth NMOS transistor N10;

The C unit includes: a fifth PMOS transistor P5, a sixth PMOS transistor P6, a seventh NMOS transistor N7 and an eighth NMOS transistor N8;

When the clock signal CLK=0, the first PMOS transistor P1 and the second PMOS transistor P2 of the precharge part set the full swing signals SB and RB output by the main stage of the flip-flop to a high level; at the same time, all the The switch is turned off when CLK=0, so that the pull-down path between the third NMOS transistor N3, the second NMOS transistor N2, and the first NMOS transistor N1 cannot be formed or the fifth NMOS transistor N5, the fourth NMOS transistor N4, and the first NMOS transistor N1 cannot be formed. A pull-down path formed between an NMOS transistor N1 cannot be formed, so as to maintain the full swing signals SB and RB output by the main stage of the flip-flop to be in a high-level state;

The first PMOS transistor P1 and the second PMOS transistor P2 of the precharge part are turned off when the clock signal CLK=1, so that the full swing signals SB and RB output by the main stage of the flip-flop are in a non-set state, and the switch transistor It is turned on when CLK=1, so that the second NMOS transistor N2 and the fourth NMOS transistor N4 can selectively form the third NMOS transistor N3, the second NMOS transistor N2, and the first NMOS transistor N1 according to the values of the differential input signals D and DB. The pull-down path between them or the pull-down path formed between the fifth NMOS transistor N5, the fourth NMOS transistor N4, and the first NMOS transistor N1, so that the level of the full swing signal SB or RB output by the main stage of the flip-flop is placed low level;

The second NMOS transistor N2 and the fourth NMOS transistor N4 read external differential input signals D and DB respectively and use them as the input of the main stage of the flip-flop;

When the clock signal CLK=1, the first inverter inv1 and the second inverter inv2 pass through the first inverter inv1 or the second inverter according to the higher level signals in the differential input signals D and DB. The inverter inv2 selectively pulls down the full swing signal SB or RB output by the main stage of the flip-flop, and pulls up another full swing output of the main stage of the flip-flop through the second inverter inv2 or the first inverter inv1 signal RB or SB, and output the full swing signal SB and RB to the flip-flop slave stage;

The short-circuit tube is always in a conducting state, and discharges the wrong flip of the full-swing signal signals SB and RB output by the main stage of the flip-flop caused by the leakage of the third PMOS tube P3 or the fourth PMOS tube P4;

The third inverter inv3 inverts the full swing signal SB output by the main stage of the flip-flop, and generates the input signal S of the C unit;

The C unit receives the input signal S and the full swing signal RB output by the main stage of the flip-flop, and generates an output signal QB;

When the clock signal CLK=0, the seventh NMOS transistor N7 or the eighth NMOS transistor N8 is turned on; the fifth PMOS transistor P5 or the sixth PMOS transistor P6 is turned on, and the output signal QB of the C unit maintains a high-impedance state;

When the clock signal CLK=1, the C unit generates the output signal QB of the C unit according to the received output signals RB and S;

The fourth inverter inv4 inverts the output signal QB of the C unit and generates the output signal Q of the flip-flop.

The features of the low-power-consumption and high-performance flip-flop based on the sense amplifier of the present invention are:

The first input end of the main stage of the trigger is the gate of the second NMOS transistor N2, and is connected to the external input signal D;

The second input end of the main stage of the trigger is the gate of the fourth NMOS transistor N4, and is connected to the external input signal DB;

The first output end of the main stage of the flip-flop is the drain of the first PMOS transistor P1 and the third PMOS transistor P3, and outputs a full swing signal SB;

The second output end of the main stage of the flip-flop is the drain of the second PMOS transistor P2 and the fourth PMOS transistor P4, and outputs a full swing signal RB;

The sources of the first PMOS transistor P1 and the second PMOS transistor P2 are connected to the power supply VDD, the gates of the first PMOS transistor P1 and the second PMOS transistor P2 are connected to the clock signal CLK, and the drain of the first PMOS transistor P1 generates the main stage of the flip-flop The output full swing signal SB, the drain of the second PMOS transistor P2 generates the full swing signal RB output by the main stage of the flip-flop;

The third PMOS transistor P3 is connected in parallel with the first PMOS transistor P1, the source of the third PMOS transistor P3 is connected to the source of the first PMOS transistor P1, the drain of the third PMOS transistor P3 is connected to the drain of the first PMOS transistor P1, and the third PMOS transistor P3 is connected to the drain of the first PMOS transistor P1. The gate of the three PMOS transistors P3 is connected to the drain of the fourth PMOS transistor P4; the fourth PMOS transistor P4 and the second PMOS transistor P2 are connected in parallel, and the source of the fourth PMOS transistor P4 is connected to the source of the second PMOS transistor P2, The drain of the fourth PMOS transistor P4 is connected to the drain of the second PMOS transistor P2, and the gate of the fourth PMOS transistor P4 is connected to the drain of the third PMOS transistor P3;

The source of the third NMOS transistor N3 is connected to the drain of the second NMOS transistor N2, the drain of the third NMOS transistor N3 is connected to the drain of the third PMOS transistor P3, and the gate of the third NMOS transistor N3 is connected to the third PMOS transistor The gate of the transistor P3; the source of the fifth NMOS transistor N5 is connected to the drain of the fourth NMOS transistor N4, the drain of the fifth NMOS transistor N5 is connected to the drain of the fourth PMOS transistor P4, and the drain of the fifth NMOS transistor N5 The gate is connected to the gate of the fourth PMOS transistor P4;

In the data input part, the source of the second NMOS transistor N2 and the source of the fourth NMOS transistor N4 are connected to the drain of the first NMOS transistor N1, and the drain of the second NMOS transistor N2 is connected to the third NMOS transistor. The source of N3, the gate of the second NMOS transistor N2 is used as the first output terminal of the trigger main stage and connected to the external input signal D, the drain of the fourth NMOS transistor N4 is connected to the source of the fifth NMOS transistor N5, the fourth The gate of the NMOS transistor N4 is used as the second output end of the trigger main stage and is connected to the external input signal DB;

The source or drain of the sixth NMOS transistor N6 is connected to the source of the third NMOS transistor N3; the drain or source of the sixth NMOS transistor N6 is connected to the source of the fifth NMOS transistor N5; The source and gate are connected to the power supply VDD and remain on;

The source of the first NMOS transistor N1 is grounded to GND, the drain is connected to the sources of the second NMOS transistor N2 and the fourth NMOS transistor N4, and the gate of the first NMOS transistor N1 is connected to the clock signal CLK.

The first input end of the trigger slave stage is the gate of the eighth NMOS transistor N8 and the fifth PMOS transistor P5, and is connected to the full swing signal RB output by the trigger master stage;

The second input end of the trigger slave stage is the gate of the ninth NMOS transistor N9, and is connected to the full swing signal SB output by the trigger master stage;

The output terminals of the slave stage of the flip-flop are the drains of the eighth PMOS transistor P8 and the tenth NMOS transistor N10, and generate the output signal Q of the slave stage of the flip-flop;

In the third inverter inv3, the seventh PMOS transistor P7 and the ninth NMOS transistor N9 are connected in series, the gate of the seventh PMOS transistor P7 is connected to the drains of the first PMOS transistor P1 and the third PMOS transistor P3, and the seventh PMOS transistor The source of P7 is connected to the power supply VDD, the source of the ninth NMOS transistor N9 is connected to the ground GND, and after the drain of the seventh PMOS transistor P7 and the ninth NMOS transistor N9 are short-circuited, the signal S generated by the drain is connected to the sixth PMOS transistor The gates of P6 and the seventh NMOS transistor N7;

In unit C, the fifth PMOS transistor P5, the sixth PMOS transistor P6, the seventh NMOS transistor N7 and the eighth NMOS transistor N8 are connected in series in sequence, the source of the fifth PMOS transistor P5 is connected to the power supply VDD, and the source of the fifth PMOS transistor P5 is connected to the power supply VDD. The drain is connected to the source of the sixth PMOS transistor P6, the drain of the sixth PMOS transistor P6 is connected to the drain of the seventh NMOS transistor N7, and the source of the seventh NMOS transistor N7 is connected to the drain of the eighth NMOS transistor N8 , the drain of the eighth NMOS transistor N8 is connected to the ground GND, the gate of the fifth PMOS transistor P5 and the gate of the eighth NMOS transistor N8 are short-circuited and connected to the drains of the second PMOS transistor P2 and the fourth PMOS transistor P4 ;

In the inverter inv4, the eighth PMOS transistor P8 and the tenth NMOS transistor N10 are connected in series, the source of the eighth PMOS transistor P8 is connected to the power supply VDD, and the source of the tenth NMOS transistor N10 is connected to the ground GND; the eighth PMOS transistor After the gates of P8 and the tenth NMOS transistor N10 are short-circuited, they are connected to the drains of the sixth PMOS transistor P6 and the seventh NMOS transistor N7, and the drains of the eighth PMOS transistor P8 and the tenth NMOS transistor N10 are short-circuited.

The working method of the low-power-consumption high-performance flip-flop of the sense amplifier of the present invention is characterized in that it is applied to a flip-flop composed of a flip-flop master stage and a flip-flop slave stage; wherein the flip-flop master stage includes: data Input part, precharge part, RAM-like structure, short-circuit tube, switch tube;

The data input part includes: a second NMOS transistor N2 and a fourth NMOS transistor N4;

The precharging part includes: a first PMOS transistor P1 and a second PMOS transistor P2;

The RAM-like structure is composed of two cross-coupled inverters, and includes: a third PMOS transistor P3, a fourth PMOS transistor P4, a third NMOS transistor N3, and a fifth NMOS transistor N5; The first inverter inv1 is composed of the tube P3 and the third NMOS tube N3; the second inverter inv2 is composed of the fourth PMOS tube P4 and the fifth NMOS tube N5;

The short-circuit tube is the sixth NMOS tube N6;

The switch tube is a first NMOS tube N1;

The flip-flop slave stage includes: the third inverter inv3 and the fourth inverter inv4 and 1 C unit;

The third inverter inv3 is composed of a seventh PMOS transistor P7 and a ninth NMOS transistor N9;

The fourth inverter inv4 is composed of an eighth PMOS transistor P8 and a tenth NMOS transistor N10;

The C unit includes: the fifth PMOS transistor P5, the sixth PMOS transistor P6, the seventh NMOS transistor N7 and the eighth NMOS transistor N8; the working method is as follows:

Step 1. When the flip-flop is in the pre-charging stage, the clock signal CLK=0, the first PMOS transistor P1 and the second PMOS transistor P2 are turned on, and the first NMOS transistor N1 is turned off, so that the full swing output of the main stage of the flip-flop is The amplitude signals SB and RB are both 1. The full swing signal SB output by the main stage of the flip-flop passes through the third inverter inv3 and then outputs the signal S=0. At the same time, the input signal RB=1 and S=0 of the C unit, so that the first The six PMOS transistors P6 and the eighth NMOS transistor N8 are turned on, and the fifth PMOS transistor P5 and the seventh NMOS transistor N7 are turned off, so that a conductive path cannot be formed. At this time, the C unit is in a high resistance state, and the output signal QB of the C unit remains inactive. changes, the output signal Q of the flip-flop slave stage remains unchanged;

Step 2. When the flip-flop is in the data sampling stage, the clock signal CLK=1, the first PMOS transistor P1 and the second PMOS transistor P2 are turned off, the first NMOS transistor N1 is turned on, and after the pre-charging process, the main stage of the flip-flop is turned off. The output full swing signals SB and RB are both high level, the third NMOS transistor N3 and the fifth NMOS transistor N5 are both on, and the second NMOS transistor N2 and the fourth NMOS transistor N4 are in the input differential signal D. Sampling with DB, and according to the higher level signal in the input differential signals D and DB, turn on the second NMOS transistor N2 or the fourth NMOS transistor N4 to form a discharge path on one side, thereby pulling down the output of the main stage of the flip-flop The full swing signal SB or RB of the trigger turns on the fourth PMOS transistor P4 or the third PMOS transistor P3, and the full swing signal RB or SB output by the main stage of the flip-flop is charged to a high level; the full swing output by the main stage of the flip-flop One of the signals SB and RB is high and the other is low;

When SB=0, RB=1, the input signal S=1, RB=1 of the C unit, the seventh NMOS transistor N7 and the eighth NMOS transistor N8 are turned on, the fifth PMOS transistor P5 and the sixth PMOS transistor P6 are turned off, The output signal QB=0 of the C unit generates the output signal Q=1 of the slave stage of the flip-flop after the fourth inverter inv4;

When SB=1, RB=0, the input signal S=0, RB=0 of the C unit, the seventh NMOS transistor N7 and the eighth NMOS transistor N8 are turned off, the fifth PMOS transistor P5 and the sixth PMOS transistor P6 are turned on, The output signal QB=1 of the C unit passes through the fourth inverter inv4 to generate the output signal Q=0 of the slave stage of the flip-flop.

Compared with the prior art, the beneficial effects of the present invention are:

1. The conventional sense amplifier-based flip-flop Con SAFF in the prior art consists of a cross-coupled inverter with Q and QB as input and two inverters with SB and RB as input. Signals Q and QB There is a correlation between the Q and QB settling times, which differ by a gate delay of a NAND gate, which makes the rising delay and falling delay of the output signal unequal, thus affecting the operating speed of the flip-flop. However, the low-power high-performance flip-flop based on the sense amplifier of the present invention isolates QB and Q through an inverter, and the slave stage does not use a symmetrical structure to generate Q and QB at the same time, and the rising delay and falling delay are equal, thereby improving the operating speed of the flip-flop. .

2. The conventional sense amplifier-based trigger Con SAFF in the prior art consists of a cross-coupled inverter with Q and QB as input and two inverters with SB and RB as input. Logic: The pull-up network and the pull-down network form a competition, which affects the stability of the flip-flop and may cause the flip-flop logic error. The low power consumption and high performance flip-flop based on the sense amplifier of the present invention adopts the C unit at the slave stage while ensuring the same polarity of the input signals S and RB of the C unit, avoiding the competition problem of the specific logic and improving the stability of the flip-flop. .

3. In the Strollo SAFF of the prior art, the slave stage can effectively avoid the competition phenomenon and reduce the generation of burrs by inserting a clock-controlled strobe tube, but it introduces additional devices and increases the power consumption. However, the low-power-consumption high-performance flip-flop based on the sense amplifier of the present invention only needs 10 MOS tubes in the slave stage, which is less than the 12 MOS tubes of the Strollo SAFF, thereby reducing the power consumption.

Description of drawings

FIG. 1 is a schematic diagram of the main stage structure of a trigger with low power consumption and high performance based on a sense amplifier according to the present invention;

Fig. 2 is the relational waveform diagram of the signal CLK, SB, RB, D, DB of the present invention;

FIG. 3 is a schematic diagram of the slave-level structure of a low-power-consumption and high-performance flip-flop based on a sense amplifier of the present invention;

FIG. 4 is a schematic diagram of the overall structure of the low-power-consumption and high-performance flip-flop based on the sense amplifier of the present invention.

Detailed ways

In this embodiment, a low-power and high-performance flip-flop based on a sense amplifier is mainly applied to a digital circuit that faces power consumption challenges with the continuous progress of the technology, and specifically includes: a flip-flop main stage, a flip-flop slave class.

In this embodiment, as shown in FIG. 1 , the main stage of the flip-flop includes a data input part, a precharge part, a RAM-like structure, a short-circuit tube, and a switch tube. Among them, the precharge part is used to set the output signals SB and RB of the main stage of the flip-flop to 1 when the clock signal CLK is 0; the RAM-like structure is used to amplify the difference between the differential inputs D and DB of the main stage of the flip-flop, thereby The main stage output signals SB and RB are driven to become full swing signals; the data input part is used to read the differential input signals D and DB of the flip-flop; the switch tube is used to turn off the discharge path when the clock signal CLK=0, so that no matter the input signal D What is the value of and DB, the output signals SB and RB of the main stage are both 1, and when the clock signal CLK=1, the values of the output signals SB and RB of the main stage of the flip-flop are controlled according to the values of the input signals D and DB of the flip-flop; short circuit The tube is used to connect the internal nodes A and B, so that the main stage output signals SB and RB have a pull-down path to prevent the internal nodes A and B from floating at a low level, thereby preventing the flip-flop output signal Q from flipping incorrectly;

Specifically, the data input part includes a second NMOS transistor N2 and a fourth NMOS transistor N4;

The switch tube is the first NMOS tube N1;

The precharge part is composed of a first PMOS transistor P1 and a second PMOS transistor P2. In this embodiment, as shown in FIG. When CLK = 0, the full swing signals SB and RB output by the main stage of the flip-flop are set to high level; at the same time, the switch tube is turned off when CLK = 0, so that the third NMOS tube N3 and the second NMOS tube are turned off. The pull-down path between the transistor N2 and the first NMOS transistor N1 cannot be formed or the pull-down path formed between the fifth NMOS transistor N5, the fourth NMOS transistor N4 and the first NMOS transistor N1 cannot be formed, so as to maintain the main stage of the flip-flop. The output full swing signals SB and RB are in the high level state;

The first PMOS transistor P1 and the second PMOS transistor P2 of the precharge part are turned off when the clock signal CLK=1, so that the full swing signals SB and RB output by the main stage of the flip-flop are in a non-set state, and the switch transistor It is turned on when CLK=1, so that the pull-down path between the third NMOS transistor N3, the second NMOS transistor N2, and the first NMOS transistor N1 or the fifth NMOS transistor N5, A pull-down path formed between the fourth NMOS transistor N4 and the first NMOS transistor N1, thereby setting the level of the trigger main stage output signal SB or RB to a low level;

Specifically, when CLK is at a high level, when D=0 and DB=1 are input, the fourth NMOS transistor N4, the fifth NMOS transistor N5, and the first NMOS transistor N1 are turned on to form a discharge path, and the RB node is connected to the ground. It is a low level, the signal RB passes through the first inverter inv1, and the SB node is charged to a high level; when input D=1, DB=0, the second NMOS transistor N2, the third NMOS transistor N3, and the first NMOS transistor N1 conduct A discharge path is formed through the pass, the SB node is connected to the ground and pulled to a low level, the signal SB passes through the first inverter inv2, and the RB node is charged to a high level;

The RAM-like structure is composed of two cross-coupled inverters inv1 and inv2, and includes: a third PMOS transistor P3, a fourth PMOS transistor P4, a third NMOS transistor N3, and a fifth NMOS transistor N5, which are composed of the third PMOS transistor P3 and the fourth PMOS transistor P4. The PMOS transistor P3 and the third NMOS transistor N3 form the first inverter inv1; the fourth PMOS transistor P4 and the fifth NMOS transistor N5 form the second inverter inv2; in this embodiment, as shown in Table 1, When the clock signal CLK=1, according to the higher level signal in the differential input signals D and DB, the main stage output signal SB or RB of the flip-flop is selectively pulled down, and the other flip-flop output signal RB is pulled up through inv2 or inv1 or SB, and output to the flip-flop slave stage;

Table 1: The truth table of the RAM-like structure clock input signal CLK, input D and DB, and output SB and RB;

The short-circuit tube is the sixth NMOS tube N6 that is always on, discharging the wrong flip of the output signals SB and RB of the trigger main stage caused by the leakage of the third PMOS tube P3 or the fourth PMOS tube P4;

The flip-flop slave stage includes a third inverter inv3 and a fourth inverter inv4 and 1 C cell. inv3 is used to invert the output signal SB of the main stage of the flip-flop to generate the input signal S of the C unit; the C unit is used to ensure that when the clock signal CLK=0, the output signal Q of the flip-flop remains unchanged, and when the clock signal CLK=1 , the flip-flop works normally, and the flip-flop output signal Q changes according to the values of the signals S and RB; inv4 is used to invert the C-unit output signal QB to generate the flip-flop output signal Q;

Specifically, the inverter inv3 includes a seventh PMOS transistor P7 and a ninth NMOS transistor N9, which are used to invert the full swing signal SB output by the main stage of the flip-flop, and generate the input signal S of the C unit;

The inverter inv4 includes: an eighth PMOS transistor P8 and a tenth NMOS transistor N10 for inverting the output signal QB of the C unit and generating the output signal Q of the flip-flop.

Unit C includes a fifth PMOS transistor P5, a sixth PMOS transistor P6, a seventh NMOS transistor N7 and an eighth NMOS transistor N8, receives the input signal S and the full swing signal RB output by the main stage of the flip-flop, and generates an output signal QB. In this embodiment, as shown in Table 2:

Table 2: The truth table of the C unit clock input signal CLK, input S, RB, and output QB;

When the clock signal CLK=0, the seventh NMOS transistor N7 or the eighth NMOS transistor N8 is turned on; the fifth PMOS transistor P5 or the sixth PMOS transistor P6 is turned on, and the output signal QB of the C unit maintains a high-impedance state;

When the clock signal CLK=1, the C unit generates the output signal QB of the C unit according to the received output signals RB and S;

Specifically, when CLK=0 and the two inputs S and RB of the C unit are not equal (S=0, RB=1 or S=1, RB=0), neither the pull-up path nor the pull-down path of the C unit can conduct On, the C unit is in a high-impedance state, the output QB remains unchanged, and the C unit can effectively filter the single-node inversion; when CLK=1, when the two inputs S and RB of the C unit are equal, when S=RB=0, pull up The passage (the fifth PMOS transistor P5, the sixth PMOS transistor P6) is turned on, and QB=1. When S=RB=1, the pull-down path (the seventh NMOS transistor N7, the eighth NMOS transistor N8) is turned on, and QB=0.

The first input end of the main stage of the flip-flop is the gate of the second NMOS transistor N2, and is connected to the external input signal D;

The second input end of the main stage of the flip-flop is the gate of the fourth NMOS transistor N4, and is connected to the external input signal DB;

The first output end of the main stage of the flip-flop is the drain of the first PMOS transistor P1 and the third PMOS transistor P3, and outputs a full swing signal SB;

The second output end of the main stage of the flip-flop is the drain of the second PMOS transistor P2 and the fourth PMOS transistor P4, and outputs the full swing signal RB;

The sources of the first PMOS transistor P1 and the second PMOS transistor P2 are connected to the power supply VDD, the gates of the first PMOS transistor P1 and the second PMOS transistor P2 are connected to the clock signal CLK, and the drain of the first PMOS transistor P1 generates the main stage of the flip-flop The output full swing signal SB, the drain of the second PMOS transistor P2 generates the full swing signal RB output by the main stage of the flip-flop;

The third PMOS transistor P3 is connected in parallel with the first PMOS transistor P1, the source of the third PMOS transistor P3 is connected to the source of the first PMOS transistor P1, the drain of the third PMOS transistor P3 is connected to the drain of the first PMOS transistor P1, and the third PMOS transistor P3 is connected to the drain of the first PMOS transistor P1. The gate of the three PMOS transistors P3 is connected to the drain of the fourth PMOS transistor P4; the fourth PMOS transistor P4 and the second PMOS transistor P2 are connected in parallel, and the source of the fourth PMOS transistor P4 is connected to the source of the second PMOS transistor P2, The drain of the fourth PMOS transistor P4 is connected to the drain of the second PMOS transistor P2, and the gate of the fourth PMOS transistor P4 is connected to the drain of the third PMOS transistor P3;

The source of the third NMOS transistor N3 is connected to the drain of the second NMOS transistor N2, the drain of the third NMOS transistor N3 is connected to the drain of the third PMOS transistor P3, and the gate of the third NMOS transistor N3 is connected to the third PMOS transistor The gate of the transistor P3; the source of the fifth NMOS transistor N5 is connected to the drain of the fourth NMOS transistor N4, the drain of the fifth NMOS transistor N5 is connected to the drain of the fourth PMOS transistor P4, and the drain of the fifth NMOS transistor N5 The gate is connected to the gate of the fourth PMOS transistor P4;

In the data input part, the source of the second NMOS transistor N2 and the source of the fourth NMOS transistor N4 are connected to the drain of the first NMOS transistor N1 together, and the drain of the second NMOS transistor N2 is connected to the drain of the third NMOS transistor N3. The source, the gate of the second NMOS transistor N2 is used as the first output terminal of the trigger main stage and is connected to the external input signal D, the drain of the fourth NMOS transistor N4 is connected to the source of the fifth NMOS transistor N5, and the fourth NMOS transistor The gate of N4 serves as the second output terminal of the main stage of the flip-flop and is connected to the external input signal DB.

The source or drain of the sixth NMOS transistor N6 is connected to the source of the third NMOS transistor N3; the drain or source of the sixth NMOS transistor N6 is connected to the source of the fifth NMOS transistor N5; The source and gate are connected to the power supply VDD and remain on;

The source of the first NMOS transistor N1 is grounded to GND, the drain is connected to the sources of the second NMOS transistor N2 and the fourth NMOS transistor N4, and the gate of the first NMOS transistor N1 is connected to the clock signal CLK.

In this embodiment, as shown in FIG. 3 , the first input terminal of the slave stage of the flip-flop is the gate of the eighth NMOS transistor N8 and the fifth PMOS transistor P5, and is connected to the full swing signal RB output by the master stage of the flip-flop;

The second input terminal of the flip-flop slave stage is the gate of the ninth NMOS transistor N9, and is connected to the full swing signal SB output by the flip-flop master stage;

The output end of the slave stage of the flip-flop is the drain of the eighth PMOS transistor P8 and the tenth NMOS transistor N10, and generates the output signal Q of the slave stage of the flip-flop;

In the third inverter inv3, the seventh PMOS transistor P7 and the ninth NMOS transistor N9 are connected in series, the gate of the seventh PMOS transistor P7 is connected to the drains of the first PMOS transistor P1 and the third PMOS transistor P3, and the seventh PMOS transistor The source of P7 is connected to the power supply VDD, the source of the ninth NMOS transistor N9 is connected to the ground GND, and after the drain of the seventh PMOS transistor P7 and the ninth NMOS transistor N9 are short-circuited, the signal S generated by the drain is connected to the sixth PMOS transistor The gates of P6 and the seventh NMOS transistor N7;

In unit C, the fifth PMOS transistor P5, the sixth PMOS transistor P6, the seventh NMOS transistor N7 and the eighth NMOS transistor N8 are connected in series in sequence, the source of the fifth PMOS transistor P5 is connected to the power supply VDD, and the source of the fifth PMOS transistor P5 is connected to the power supply VDD. The drain is connected to the source of the sixth PMOS transistor P6, the drain of the sixth PMOS transistor P6 is connected to the drain of the seventh NMOS transistor N7, and the source of the seventh NMOS transistor N7 is connected to the drain of the eighth NMOS transistor N8 , the drain of the eighth NMOS transistor N8 is connected to the ground GND, the gate of the fifth PMOS transistor P5 and the gate of the eighth NMOS transistor N8 are short-circuited and connected to the drains of the second PMOS transistor P2 and the fourth PMOS transistor P4 ;

In the fourth inverter inv4, the eighth PMOS transistor P8 and the tenth NMOS transistor N10 are connected in series, the source of the eighth PMOS transistor P8 is connected to the power supply VDD, and the source of the tenth NMOS transistor N10 is connected to the ground GND; After the gates of the PMOS transistor P8 and the tenth NMOS transistor N10 are short-circuited, they are connected to the drains of the sixth PMOS transistor P6 and the seventh NMOS transistor N7, and the drains of the eighth PMOS transistor P8 and the tenth NMOS transistor N10 are short-circuited.

In this embodiment, as shown in FIG. 4 , a low-power-consumption and high-performance flip-flop based on a sense amplifier works as follows:

Step 1. When the flip-flop is in the pre-charging stage, the clock signal CLK=0, the first PMOS transistor P1 and the second PMOS transistor P2 are turned on, and the first NMOS transistor N1 is turned off, so that the full swing output of the main stage of the flip-flop is The amplitude signals SB and RB are both 1. The full swing signal SB output by the main stage of the flip-flop passes through the third inverter inv3 and then outputs the signal S=0. At the same time, the input signal RB=1 and S=0 of the C unit, so that the first The six PMOS transistors P6 and the eighth NMOS transistor N8 are turned on, and the fifth PMOS transistor P5 and the seventh NMOS transistor N7 are turned off, so that a conductive path cannot be formed. At this time, the C unit is in a high resistance state, and the output signal QB of the C unit remains inactive. changes, the output signal Q of the flip-flop slave stage remains unchanged;

Step 2, in this embodiment, as shown in Table 3:

Table 3 Flip Flop Truth Table

When the flip-flop is in the data sampling stage, the clock signal CLK=1, the first PMOS transistor P1 and the second PMOS transistor P2 are turned off, the first NMOS transistor N1 is turned on, and after the pre-charging process, the full output of the main stage of the flip-flop is turned off. The swing signals SB and RB are both at high level, the third NMOS transistor N3 and the fifth NMOS transistor N5 are both in the conducting state, and the second NMOS transistor N2 and the fourth NMOS transistor N4 conduct the input differential signals D and DB. Sampling, and according to the higher level signal in the input differential signals D and DB, turn on the second NMOS transistor N2 or the fourth NMOS transistor N4 to form a discharge path on one side, thereby pulling down the full swing output of the main stage of the flip-flop The amplitude signal SB or RB makes the fourth PMOS transistor P4 or the third PMOS transistor P3 turn on, and the full swing signal RB or SB output by the main stage of the flip-flop is charged to a high level; the full swing signal SB and SB output by the main stage of the flip-flop are charged. One of the signals in RB is high and the other is low;

When SB=0, RB=1, the input signal S=1, RB=1 of the C unit, the seventh NMOS transistor N7 and the eighth NMOS transistor N8 are turned on, the fifth PMOS transistor P5 and the sixth PMOS transistor P6 are turned off, The output signal QB=0 of the C unit generates the output signal Q=1 of the slave stage of the flip-flop after the fourth inverter inv4;

When SB=1, RB=0, the input signal S=0, RB=0 of the C unit, the seventh NMOS transistor N7 and the eighth NMOS transistor N8 are turned off, the fifth PMOS transistor P5 and the sixth PMOS transistor P6 are turned on, The output signal QB=1 of the C unit passes through the fourth inverter inv4 to generate the output signal Q=0 of the slave stage of the flip-flop.

Claims (4)

1. A low-power consumption high-performance trigger based on a sensitive amplifier is characterized by comprising: a master flip-flop stage, a slave flip-flop stage;

the flip-flop primary includes: the device comprises a data input part, a pre-charging part, a RAM-like structure, a short-circuit tube and a switching tube;

the data input section includes: a second NMOS transistor N2 and a fourth NMOS transistor N4;

the precharge section includes: a first PMOS transistor P1 and a second PMOS transistor P2;

the RAM-like structure is composed of two cross-coupled inverters and includes: a third PMOS transistor P3, a fourth PMOS transistor P4, a third NMOS transistor N3 and a fifth NMOS transistor N5; a first inverter inv1 is formed by the third PMOS transistor P3 and a third NMOS transistor N3; a second inverter inv2 is formed by the fourth PMOS transistor P4 and a fifth NMOS transistor N5;

the short-circuit tube is a sixth NMOS tube N6;

the switch tube is a first NMOS tube N1;

the flip-flop slave stage includes: a third inverter inv3 and a fourth inverter inv4 and 1C cell;

the third inverter inv3 is composed of a seventh PMOS transistor P7 and a ninth NMOS transistor N9;

the fourth inverter inv4 is composed of an eighth PMOS transistor P8 and a tenth NMOS transistor N10;

the C unit includes: a fifth PMOS transistor P5, a sixth PMOS transistor P6, a seventh NMOS transistor N7 and an eighth NMOS transistor N8;

when a clock signal CLK is equal to 0, a first PMOS tube P1 and a second PMOS tube P2 of the pre-charging part place full swing signals SB and RB output by the main stage of the trigger at a high level; meanwhile, the switch tube is turned off when the CLK is equal to 0, so that a pull-down path between the third NMOS tube N3, the second NMOS tube N2 and the first NMOS tube N1 cannot be formed, or a pull-down path between the fifth NMOS tube N5, the fourth NMOS tube N4 and the first NMOS tube N1 cannot be formed, so as to maintain the full swing signals SB and RB output by the master stage of the flip-flop in a high level state;

the first PMOS tube P1 and the second PMOS tube P2 of the pre-charging part are turned off when a clock signal CLK is 1, so that full swing signals SB and RB output by the main stage of the trigger are in a non-setting state, and meanwhile, the switch tube is turned on when the clock signal CLK is 1, so that the second NMOS tube N2 and the fourth NMOS tube N4 can selectively form a pull-down path among the third NMOS tube N3, the second NMOS tube N2 and the first NMOS tube N1 or a pull-down path composed among the fifth NMOS tube N5, the fourth NMOS tube N4 and the first NMOS tube N1 according to the values of the differential input signals D and DB, thereby placing the level of the full swing signal SB or RB output by the main stage of the trigger at a low level;

the second NMOS transistor N2 and the fourth NMOS transistor N4 respectively read external differential input signals D and DB and serve as the input of the main stage of the trigger;

when the clock signal CLK is equal to 1, the first inverter inv1 and the second inverter inv2 selectively pull down the full-swing signal SB or RB output by the master of the flip-flop through the first inverter inv1 or the second inverter inv2, pull up the other full-swing signal RB or SB output by the master of the flip-flop through the second inverter inv2 or the first inverter inv1, and output the full-swing signals SB and RB to the slave of the flip-flop, according to the higher signal level in the differential input signals D and DB;

the short-circuit tube is always in a conducting state and discharges the false overturning of full swing signal signals SB and RB output by the main stage of the trigger caused by the leakage of a third PMOS tube P3 or a fourth PMOS tube P4;

the third inverter inv3 inverts the full swing signal SB output by the main stage of the flip-flop and generates the input signal S of the C unit;

the C unit receives the input signal S and a full swing signal RB output by a trigger main stage and generates an output signal QB;

when the clock signal CLK is equal to 0, the seventh NMOS transistor N7 or the eighth NMOS transistor N8 is turned on; the fifth PMOS tube P5 or the sixth PMOS tube P6 is conducted, and the output signal QB of the C unit keeps a high-impedance state;

when the clock signal CLK is 1, the C unit generates an output signal QB of the C unit according to the received output signals RB and S;

the fourth inverter inv4 inverts the output signal QB of the C-cell and generates the output signal Q of the flip-flop.

2. The sense amplifier based low power consumption high performance flip-flop of claim 1, wherein:

the first input end of the main stage of the trigger is the grid electrode of a second NMOS tube N2 and is connected with an external input signal D;

the second input end of the main stage of the trigger is the grid electrode of a fourth NMOS tube N4 and is connected to an external input signal DB;

the first output end of the main stage of the trigger is the drains of a first PMOS tube P1 and a third PMOS tube P3, and outputs a full swing signal SB;

the second output end of the main stage of the trigger is the drains of a second PMOS tube P2 and a fourth PMOS tube P4, and outputs a full swing signal RB;

the source electrodes of the first PMOS tube P1 and the second PMOS tube P2 are connected with a power supply VDD, the grid electrodes of the first PMOS tube P1 and the second PMOS tube P2 are connected with a clock signal CLK, the drain electrode of the first PMOS tube P1 generates a full swing signal SB output by the master stage of the trigger, and the drain electrode of the second PMOS tube P2 generates a full swing signal RB output by the master stage of the trigger;

a third PMOS tube P3 and a first PMOS tube P1 are connected in parallel, the source electrode of the third PMOS tube P3 is connected with the source electrode of the first PMOS tube P1, the drain electrode of the third PMOS tube P3 is connected with the drain electrode of the first PMOS tube P1, and the grid electrode of the third PMOS tube P3 is connected with the drain electrode of the fourth PMOS tube P4; a fourth PMOS transistor P4 and the second PMOS transistor P2 are connected in parallel, the source of the fourth PMOS transistor P4 is connected to the source of the second PMOS transistor P2, the drain of the fourth PMOS transistor P4 is connected to the drain of the second PMOS transistor P2, and the gate of the fourth PMOS transistor P4 is connected to the drain of the third PMOS transistor P3;

the source electrode of the third NMOS transistor N3 is connected to the drain electrode of the second NMOS transistor N2, the drain electrode of the third NMOS transistor N3 is connected to the drain electrode of the third PMOS transistor P3, and the gate electrode of the third NMOS transistor N3 is connected to the gate electrode of the third PMOS transistor P3; the source electrode of a fifth NMOS transistor N5 is connected to the drain electrode of a fourth NMOS transistor N4, the drain electrode of a fifth NMOS transistor N5 is connected to the drain electrode of a fourth PMOS transistor P4, and the gate electrode of a fifth NMOS transistor N5 is connected to the gate electrode of a fourth PMOS transistor P4;

in the data input part, the source electrode of a second NMOS transistor N2 and the source electrode of a fourth NMOS transistor N4 are connected to the drain electrode of a first NMOS transistor N1 together, the drain electrode of the second NMOS transistor N2 is connected to the source electrode of a third NMOS transistor N3, the grid electrode of a second NMOS transistor N2 is used as a first output end of a main stage of the trigger and is connected with an external input signal D, the drain electrode of the fourth NMOS transistor N4 is connected to the source electrode of a fifth NMOS transistor N5, and the grid electrode of the fourth NMOS transistor N4 is used as a second output end of the main stage of the trigger and is connected with an external input signal DB;

the source or the drain of the sixth NMOS transistor N6 is connected to the source of the third NMOS transistor N3; the drain or source of the sixth NMOS transistor N6 is connected to the source of the fifth NMOS transistor N5; the source electrode and the grid electrode of the fifth NMOS tube N5 are connected with a power supply VDD and are kept in an on state;

the source of the first NMOS transistor N1 is grounded GND, the drain is connected to the sources of the second NMOS transistor N2 and the fourth NMOS transistor N4, and the gate of the first NMOS transistor N1 is connected to the clock signal CLK.

3. The sense amplifier based low power consumption high performance flip-flop of claim 1, wherein:

the first input end of the slave stage of the trigger is the grids of an eighth NMOS transistor N8 and a fifth PMOS transistor P5, and is connected with a full swing signal RB output by the master stage of the trigger;

the second input end of the slave stage of the trigger is the grid of a ninth NMOS (N-channel metal oxide semiconductor) tube N9 and is connected to a full swing signal SB output by the master stage of the trigger;

the output end of the flip-flop slave stage is the drains of an eighth PMOS transistor P8 and a tenth NMOS transistor N10, and generates an output signal Q of the flip-flop slave stage;

in the third inverter inv3, a seventh PMOS transistor P7 and a ninth NMOS transistor N9 are connected in series, the gate of the seventh PMOS transistor P7 is connected to the drains of the first PMOS transistor P1 and the third PMOS transistor P3, the source of the seventh PMOS transistor P7 is connected to the power supply VDD, the source of the ninth NMOS transistor N9 is connected to the GND, and after the drains of the seventh PMOS transistor P7 and the ninth NMOS transistor N9 are shorted, a signal S generated by the drain is connected to the gates of the sixth PMOS transistor P6 and the seventh NMOS transistor N7;

in the unit C, a fifth PMOS tube P5, a sixth PMOS tube P6, a seventh NMOS tube N7 and an eighth NMOS tube N8 are sequentially connected in series, the source of the fifth PMOS tube P5 is connected to a power supply VDD, the drain of the fifth PMOS tube P5 is connected with the source of the sixth PMOS tube P6, the drain of the sixth PMOS tube P6 is connected with the drain of the seventh NMOS tube N7, the source of the seventh NMOS tube N7 is connected with the drain of the eighth NMOS tube N8, the drain of the eighth NMOS tube N8 is connected to the ground GND, and the gate of the fifth PMOS tube P5 and the gate of the eighth NMOS tube N8 are connected to the drains of the second PMOS tube P2 and the fourth PMOS tube P4 after being short-circuited;

in the inverter inv4, an eighth PMOS transistor P8 and a tenth NMOS transistor N10 are connected in series, the source of the eighth PMOS transistor P8 is connected to the power supply VDD, and the source of the tenth NMOS transistor N10 is connected to the ground GND; after the gates of the eighth PMOS transistor P8 and the tenth NMOS transistor N10 are shorted, the drains of the sixth PMOS transistor P6 and the seventh NMOS transistor N7 are connected, and the drains of the eighth PMOS transistor P8 and the tenth NMOS transistor N10 are shorted.

4. A working method of a trigger with low power consumption and high performance of a sensitive amplifier is characterized in that the trigger is applied to a trigger consisting of a trigger main stage and a trigger slave stage; wherein the flip-flop primary comprises: the device comprises a data input part, a pre-charging part, a RAM-like structure, a short-circuit tube and a switching tube;

the data input section includes: a second NMOS transistor N2 and a fourth NMOS transistor N4;

the precharge section includes: a first PMOS transistor P1 and a second PMOS transistor P2;

the RAM-like structure is composed of two cross-coupled inverters and includes: a third PMOS transistor P3, a fourth PMOS transistor P4, a third NMOS transistor N3 and a fifth NMOS transistor N5; a first inverter inv1 is formed by the third PMOS transistor P3 and a third NMOS transistor N3; a second inverter inv2 is formed by the fourth PMOS transistor P4 and a fifth NMOS transistor N5;

the short-circuit tube is a sixth NMOS tube N6;

the switch tube is a first NMOS tube N1;

the flip-flop slave stage includes: a third inverter inv3 and a fourth inverter inv4 and 1C cell;

the third inverter inv3 is composed of a seventh PMOS transistor P7 and a ninth NMOS transistor N9;

the fourth inverter inv4 is composed of an eighth PMOS transistor P8 and a tenth NMOS transistor N10;

the C unit includes: a fifth PMOS transistor P5, a sixth PMOS transistor P6, a seventh NMOS transistor N7 and an eighth NMOS transistor N8; the working method comprises the following steps:

step 1, when the flip-flop is in a precharge stage, a clock signal CLK is 0, the first PMOS transistor P1 and the second PMOS transistor P2 are turned on, the first NMOS transistor N1 is turned off, so that the full swing signals SB and RB output by the master stage of the flip-flop are both 1, the full swing signal SB output by the master stage of the flip-flop passes through the third inverter inv3 and then outputs a signal S of 0, meanwhile, the input signal RB of the C unit is 1, S is 0, so that the sixth PMOS transistor P6 and the eighth NMOS transistor N8 are turned on, the fifth PMOS transistor P5 and the seventh NMOS transistor N7 are turned off, so that a conductive path cannot be formed, at this time, the C unit is in a high impedance state, the output signal QB of the C unit remains unchanged, and the output signal Q of the slave stage of the flip-flop remains unchanged;

step 2, when the flip-flop is in a data sampling stage, a clock signal CLK is 1, the first PMOS transistor P1 and the second PMOS transistor P2 are turned off, the first NMOS transistor N1 is turned on, and after a precharge process, full swing signals SB and RB output by a master stage of the flip-flop are both at a high level, the third NMOS transistor N3 and the fifth NMOS transistor N5 are both in a conductive state, the second NMOS transistor N2 and the fourth NMOS transistor N4 sample input differential signals D and DB, and according to a higher level signal in the input differential signals D and DB, the second NMOS transistor N2 or the fourth NMOS transistor N4 is turned on to form a discharge path on one side, so that the full swing signal SB or RB output by the master stage of the flip-flop is pulled down, the fourth PMOS transistor P4 or the third PMOS transistor P3 is turned on, and the full swing signal RB or SB output by the master stage of the flip-flop is charged to a high level; one signal of full swing signals SB and RB output by the main stage of the trigger is high level, and the other signal is low level;

when SB is 0 and RB is 1, the input signal S of the unit C is 1, RB is 1, the seventh NMOS transistor N7 and the eighth NMOS transistor N8 are turned on, the fifth PMOS transistor P5 and the sixth PMOS transistor P6 are turned off, and the output signal QB of the unit C is 0 and generates the output signal Q of the slave stage of the flip-flop by the fourth inverter inv4, which is 1;

when SB is 1 and RB is 0, the input signal S of the unit C is 0, RB is 0, the seventh NMOS transistor N7 and the eighth NMOS transistor N8 are turned off, the fifth PMOS transistor P5 and the sixth PMOS transistor P6 are turned on, and the output signal QB of the unit C is 1, which is passed through the fourth inverter inv4, to generate the output signal Q of the slave stage of the flip-flop, which is 0.

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