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CN114783961A - Plastic package structure and processing method thereof - Google Patents

Plastic package structure and processing method thereof Download PDF

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Publication number
CN114783961A
CN114783961A CN202210545092.6A CN202210545092A CN114783961A CN 114783961 A CN114783961 A CN 114783961A CN 202210545092 A CN202210545092 A CN 202210545092A CN 114783961 A CN114783961 A CN 114783961A
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CN
China
Prior art keywords
silicon chip
substrate
plastic package
package structure
bonding
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202210545092.6A
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Chinese (zh)
Inventor
李轶楠
李小波
李明
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Wuxi Zhongwei High Tech Electronic Co ltd
Original Assignee
Wuxi Zhongwei High Tech Electronic Co ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by Wuxi Zhongwei High Tech Electronic Co ltd filed Critical Wuxi Zhongwei High Tech Electronic Co ltd
Priority to CN202210545092.6A priority Critical patent/CN114783961A/en
Publication of CN114783961A publication Critical patent/CN114783961A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Geometry (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

The invention relates to the technical field of semiconductor plastic package, and particularly discloses a plastic package structure, which comprises: the silicon chip is bonded with the substrate through a bonding wire, one end of the bonding wire is located in the drainage groove, the other end of the bonding wire is located on the substrate, and the drainage groove can drain plastic package materials to the periphery of the silicon chip to form a plastic package material layer arranged around the silicon chip. The invention also discloses a processing method of the plastic package structure. The plastic package structure provided by the invention can effectively prevent the silicon chip from displacing due to the impact of the plastic package material.

Description

Plastic package structure and processing method thereof
Technical Field
The invention relates to the technical field of semiconductor plastic package, in particular to a plastic package structure and a processing method of the plastic package structure.
Background
The plastic package device has the advantages of low cost, small size, light weight, batch production and the like. However, during the plastic package process, the plastic package material may impact and extrude the chip and the bonding wires on the edge of the substrate, so that the positioning chip and the bonding wires may displace to some extent, and the bonding wires may be broken.
Disclosure of Invention
The invention provides a plastic package structure and a processing method thereof, which solve the problem that a welding wire is broken in the related technology.
As a first aspect of the present invention, there is provided a plastic package structure, including: the silicon chip is arranged on the substrate, a drainage groove is formed in the surface, deviating from the substrate, of the silicon chip, the silicon chip is bonded with the substrate through a bonding wire, one end of the bonding wire is located in the drainage groove, the other end of the bonding wire is located on the substrate, and the drainage groove can drain a plastic package material to the periphery of the silicon chip to form a plastic package material layer surrounding the silicon chip.
Further, the drainage groove comprises a slotted structure arranged in a crisscross manner.
Further, the drainage grooves comprise slotted structures which are arranged along the diagonal line of the silicon chip in a crisscross manner.
Furthermore, the bonding wire comprises lead segments arranged at each diagonal position of the silicon chip, one end of each lead segment is positioned in the drainage groove, and the other end of each lead segment is connected with the substrate.
Furthermore, the diameter of each lead segment is between 5 and 50 micrometers, and the length of each lead segment is between 1 and 10 mm.
Further, the bonding wire includes any one of a gold wire, a copper wire, an alloy wire, and a polymer conductive wire.
Further, the substrate includes any one of a multi-layer substrate, a buried substrate, and a flexible substrate.
As another aspect of the present invention, a processing method of a plastic package structure is provided, which is used for processing the plastic package structure described above, wherein the processing method includes:
providing a substrate and a silicon chip, wherein the substrate comprises a plurality of pins, a top solder mask layer of the substrate is a chip bonding area, and a bottom solder mask layer of the substrate is a BGA pad area;
treating the upper surface of the silicon chip to form a drainage groove;
thinning the lower surface of the silicon chip to reach a preset thickness;
carrying out metal coating on the lower surface of the silicon chip to form back gold;
welding the back gold of the silicon chip with the surface of the substrate;
scribing the silicon chip to obtain an independent packaging structure with independent electrical performance;
bonding the silicon chip on the single packaging structure with the substrate;
and plastically packaging the bonded independent packaging structure, and draining the plastic packaging material to the periphery of the silicon chip through the drainage groove to form a plastic packaging material layer arranged around the silicon chip.
As another aspect of the present invention, a processing method of a plastic package structure is provided, which is used for processing the plastic package structure described above, wherein the processing method includes:
providing a substrate and a silicon chip, wherein the substrate comprises a plurality of pins, a top solder mask layer of the substrate is a chip bonding area, and a bottom solder mask layer of the substrate is a BGA pad area;
thinning the lower surface of the silicon chip to reach a preset thickness, and performing metal coating on the lower surface of the silicon chip to form a back metal;
welding the back gold of the silicon chip with the surface of the substrate;
scribing the silicon chip to obtain an independent packaging structure with independent electrical performance;
treating the upper surface of the silicon chip on the single packaging structure to form a drainage groove;
bonding the silicon chip on the independent packaging structure with the substrate;
and plastically packaging the bonded independent packaging structure, and draining the plastic packaging material to the periphery of the silicon chip through the drainage groove to form a plastic packaging material layer arranged around the silicon chip.
According to the packaging structure provided by the invention, the drainage grooves are formed, so that the plastic package material can be drained to the periphery of the silicon chip when the plastic package material is injected in the plastic package process, and the silicon chip is effectively prevented from being displaced due to the impact of the plastic package material. In addition, according to the viscosity change characteristic of the plastic package material, the time for wrapping the silicon chip and other factors, the stress of the bonding wire for chip bonding is the minimum when the plastic package material is guided, so that the bonding wire is effectively prevented from being broken by the plastic package material, and the reliability of a plastic package product is improved.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention and not to limit the invention. In the drawings:
fig. 1A is a structural plan view of a plastic package structure according to an embodiment of the present invention.
Fig. 1B is a structural cross-sectional view of the plastic package structure provided in the present invention.
Fig. 1C is a top view of a plastic package structure according to another embodiment of the present invention.
Fig. 2A is a top view of the substrate of one embodiment of fig. 1A.
FIG. 2B is a top view of a silicon chip forming a flow-directing groove according to one embodiment of FIG. 1A.
Fig. 2C is a top view of the silicon chip and substrate of one embodiment of fig. 1A after bonding.
Fig. 2D is a top view of the silicon chip and substrate of one embodiment of fig. 1A after bonding.
FIG. 2E is a top view of one embodiment of FIG. 1A forming a plastic encapsulant layer.
FIG. 3A is a top view of the substrate of FIG. 1A in accordance with another embodiment.
FIG. 3B is a top view of another embodiment of FIG. 1A with a silicon chip formed on a substrate.
FIG. 3C is a top view of another embodiment of the silicon chip of FIG. 1A with drainage grooves formed therein.
FIG. 3D is a top view of another embodiment of the silicon die of FIG. 1A bonded to a substrate.
FIG. 3E is a top view of another embodiment of FIG. 1A forming a plastic encapsulant layer.
Detailed Description
It should be noted that the embodiments and features of the embodiments may be combined with each other without conflict. The present invention will be described in detail below with reference to the embodiments with reference to the attached drawings.
In order to make those skilled in the art better understand the technical solutions of the embodiments of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that the terms "first," "second," and the like in the description and claims of the present invention and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged under appropriate circumstances in order to facilitate the description of the embodiments of the invention herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
In this embodiment, a plastic package structure is provided, where fig. 1A is a top view of the plastic package structure provided in an embodiment of the present invention, and fig. 1B is a cross-sectional view of the plastic package structure provided in an embodiment of the present invention, as shown in fig. 1A and fig. 1B, the plastic package structure includes:
the silicon chip 101 is bonded with the substrate 103 through a bonding wire 104, one end of the bonding wire 104 is located in the drainage groove 102, the other end of the bonding wire 104 is located on the substrate 103, and the drainage groove 102 can drain the plastic package material to the periphery of the silicon chip 101 to form a plastic package material layer 105 arranged around the silicon chip 101.
Specifically, in order to solve the problem that the bonding wire is broken by the plastic package material when the plastic package material is subjected to plastic package, the drainage groove 102 is formed in the upper surface of the silicon chip 101, so that the plastic package material can be drained to the periphery of the silicon chip 101, and the bonding wire is prevented from being broken by the plastic package material.
Specifically, a BGA pad and a solder Ball are disposed on the substrate 103, a chip is connected to the substrate in the slot through a conductive adhesive, a solder joint on the chip is connected to a BGA (Ball Grid Array ) pad on the substrate/lead frame through a bonding wire, the chip, the bonding wire, the solder Ball, and the substrate form a power supply and a signal channel of the circuit, and the substrate, the chip, and the bonding wire are encapsulated by a plastic package material.
Therefore, the packaging structure provided by the embodiment of the invention can drain the plastic package material to the periphery of the silicon chip when the plastic package material is injected in the plastic package process by arranging the drainage groove, so that the silicon chip is effectively prevented from displacing due to the impact of the plastic package material. In addition, according to the viscosity change characteristic of the plastic package material, the time for wrapping the silicon chip and other factors, the stress of the bonding wire for chip bonding is the minimum when the plastic package material is guided, so that the bonding wire is effectively prevented from being broken by the plastic package material, and the reliability of a plastic package product is improved.
It should be noted that, when the drainage groove 102 is manufactured, any one of laser grooving, wet etching and deep silicon etching may be specifically used, and of course, other manners capable of manufacturing the drainage groove 102 may also be used, which is not limited herein.
The specific processing method can be summarized as follows: forming a drainage groove on the upper surface of the silicon chip → thinning the lower surface of the silicon chip → metalizing the lower surface of the silicon chip → scribing and sorting → pasting the silicon chip → bonding → plastic packaging. Or thinning the silicon chip → metalizing the lower surface of the silicon chip → scribing and sorting → pasting the silicon chip → forming a drainage groove on the upper surface of the silicon chip → bonding → plastic packaging.
Specifically, in the embodiment of the present invention, in order to improve the drainage effect, the drainage groove 102 includes a slotted structure arranged in a crisscross manner.
Further specifically, as shown in FIG. 1A, the flow-guiding grooves 102 comprise a grooved structure arranged along the diagonal of the silicon chip 101 in a criss-cross pattern.
More particularly, as shown in FIG. 1C, the drainage slots 102 comprise a slotted structure arranged in a criss-cross pattern.
It should be understood that, with the structure of the drainage groove 102 shown in fig. 1A and 1C, when plastic package is performed, the plastic package can be effectively guided to four corners along the channel, so that displacement of the silicon chip 101 due to impact of the plastic package can be effectively prevented, and the wire bonding can be effectively prevented from being broken.
Specifically, the bonding wires 104 include lead segments disposed at each diagonal position of the silicon chip 101, one end of each lead segment is located in the current-guiding groove 102, and the other end is connected to the substrate 103.
In the embodiment of the present invention, as shown in fig. 1A and fig. 1C, the silicon chip may specifically include 4 lead segments located at four corners of the silicon chip 101, and each lead segment can implement bonding between the silicon chip 101 and the substrate 103.
More specifically, the diameter of each lead segment is between 5 and 50 micrometers, and the length of each lead segment is between 1 and 10 mm.
In the embodiment of the present invention, the bonding wire 104 includes any one of a gold wire, a copper wire, an alloy wire, and a polymer conductive wire.
In the embodiment of the present invention, the substrate 103 includes any one of a multilayer substrate, a buried substrate, and a flexible substrate.
It should be noted that, in the embodiment of the present invention, the multilayer substrate specifically refers to a substrate having 1 to 30 layers, a line width greater than or equal to 5 μm, a line pitch greater than or equal to 5 μm, and a pin count of 1 to 10000.
As another embodiment of the present invention, a processing method of a plastic package structure is provided, which is used for processing the plastic package structure shown in fig. 1A, where as shown in fig. 2A to 2E, the processing method includes:
step S110, as shown in fig. 2A, providing a substrate 103 and a silicon chip 101, where the substrate 103 includes multiple pins, a Top Solder Mask (TSM) of the substrate 103 is a chip bonding region, and a Bottom Solder Mask (BSM) of the substrate is a BGA pad region; it should be understood that the substrate 103 may be a high-density substrate, and both the substrate and the silicon chip are subjected to nipd-au treatment.
Step S120, as shown in fig. 2B, processing the upper surface of the silicon chip 101 to form a flow guide groove 102; for example, the top surface of the silicon chip may be processed by high precision laser or etching to form a trench structure with a certain width and depth along the diagonal direction, so as to form the flow guide trench 102.
Step S130, thinning the lower surface of the silicon chip 101 to reach a preset thickness; in the embodiment of the invention, the silicon chip 101 is thinned by using a full-automatic thinning machine to reach the required thickness.
Step S140, performing metal coating on the lower surface of the silicon chip 101 to form back gold; it should be understood that the stress among the chip, the solder and the pedestal can be matched in this way, and meanwhile, the bonding strength between the silicon chip and the pedestal is improved, and the contact resistance and the contact heat resistance are reduced.
Step S150, as shown in fig. 2C, soldering the back gold of the silicon chip 101 and the surface of the substrate 103;
step S160, scribing the silicon chip 101 to obtain an independent packaging structure with independent electrical performance;
it should be understood that each die having independent electrical properties is separated along the scribe line one by one.
Step S170, as shown in fig. 2D, bonding the silicon chip 101 on the single package structure with the substrate 103; specifically, gold wires can be welded on the surfaces of the silicon chip 101 and the substrate 103 through the action of thermal ultrasonic, so that the electrical connection between the silicon chip and an external circuit and between the silicon chip and the silicon chip can be realized
Step S180, as shown in fig. 2E, performing plastic packaging on the bonded individual package structure, and draining the plastic packaging material to the periphery of the silicon chip 101 through the drainage groove 102 to form a plastic packaging material layer 105 surrounding the silicon chip 101.
It should be understood that, finally, plastic packaging is performed, and the grooved silicon chip or the grooved silicon chip and the gold wire are sealed by using a molten plastic packaging material so as to be free from failure due to external influence, thereby obtaining a plastic packaged device with high reliability.
As another embodiment of the present invention, a processing method of a plastic package structure is provided, which is used for processing the plastic package structure, and as shown in fig. 3A to 3E, the processing method includes:
step S210, as shown in fig. 3A, providing a substrate 103 and a silicon chip 101, where the substrate 103 includes multiple pins, a TSM layer of the substrate is a chip bonding region, and a BSM layer of the substrate is a BGA pad region; it should be understood that the substrate 103 may be a high-density substrate, and both the substrate and the silicon chip are subjected to nipd-au treatment.
Step S220, thinning the lower surface of the silicon chip 101 to reach a preset thickness, and performing metal coating on the lower surface of the silicon chip 101 to form a back metal;
in the embodiment of the invention, the back surface of the silicon chip is thinned by using a full-automatic thinning machine to reach the required thickness, and vacuum metal coating is carried out on the thinned surface to form the back metal, so that the stress among the chip, the solder and the base is matched, the bonding strength between the chip and the base is improved, and the contact resistance and the contact thermal resistance are reduced.
Step S230, welding the back metal of the silicon chip 101 and the surface of the substrate 103;
step S240, scribing the silicon chip 101 to obtain an independent packaging structure with independent electrical performance;
specifically, the silicon chip 101 is diced, and each chip having independent electrical performance is separated along the dicing streets one by one.
Step S250, processing the upper surface of the silicon chip 101 on the single packaging structure to form a drainage groove 102;
a grooving structure with a certain width and depth is prepared on the upper surface of the silicon chip along the diagonal direction by a high-precision laser or etching method, so as to form the drainage groove 102.
Step S260, bonding the silicon chip 101 on the single packaging structure with the substrate 103;
specifically, gold wires are soldered on the surfaces of the silicon chip 101 and the substrate 103 by a thermal ultrasonic action, thereby realizing electrical connection between the silicon chip 101 and an external circuit, and between the silicon chip 101 and the silicon chip 101.
Step S270, carrying out plastic package on the bonded single packaging structure, and draining the plastic package material to the periphery of the silicon chip 101 through the drainage groove 102 to form a plastic package material layer 105 surrounding the silicon chip 101.
Specifically, during plastic packaging, a molten plastic packaging material is used for sealing the grooved silicon chip and the gold wire, so that the silicon chip and the gold wire are not affected by the outside and lose effectiveness, and a plastic packaging device with high reliability is obtained.
In summary, the processing method of the plastic package structure provided by the embodiment of the invention can drain the plastic package material to the periphery of the silicon chip by arranging the drainage grooves when the plastic package material is injected in the plastic package process, thereby effectively preventing the silicon chip from generating displacement due to the impact of the plastic package material. In addition, according to the viscosity change characteristic of the plastic package material, the time for wrapping the silicon chip and other factors, the stress of the bonding wire for chip bonding is the minimum when the plastic package material is guided, so that the bonding wire is effectively prevented from being broken by the plastic package material, and the reliability of a plastic package product is improved.
It will be understood that the above embodiments are merely exemplary embodiments taken to illustrate the principles of the present invention, which is not limited thereto. It will be apparent to those skilled in the art that various modifications and improvements can be made without departing from the spirit and scope of the invention, and such modifications and improvements are also considered to be within the scope of the invention.

Claims (9)

1. A plastic package structure, comprising: the silicon chip is bonded with the substrate through a bonding wire, one end of the bonding wire is located in the drainage groove, the other end of the bonding wire is located on the substrate, and the drainage groove can drain plastic package materials to the periphery of the silicon chip to form a plastic package material layer arranged around the silicon chip.
2. The plastic package structure according to claim 1, wherein the drainage grooves comprise slotted structures arranged crosswise.
3. The plastic package structure according to claim 2, wherein the flow guide grooves comprise slotted structures arranged along diagonal lines of the silicon chip in a crisscross manner.
4. The plastic package structure according to claim 3, wherein the bonding wires comprise lead segments disposed at each diagonal position of the silicon chip, one end of each lead segment is located in the drainage groove, and the other end of each lead segment is connected to the substrate.
5. The plastic package structure according to claim 4, wherein the diameter of each lead segment is between 5 μm and 50 μm, and the length of each lead segment is between 1mm and 10 mm.
6. The plastic package structure according to claim 1, wherein the bonding wire comprises any one of a gold wire, a copper wire, an alloy wire and a polymer conductive wire.
7. The plastic package structure according to claim 1, wherein the substrate comprises any one of a multi-layer substrate, a buried substrate, and a flexible substrate.
8. A method for processing a plastic package structure according to any one of claims 1 to 7, the method comprising:
providing a substrate and a silicon chip, wherein the substrate comprises multiple pins, a top solder mask layer of the substrate is a chip bonding region, and a bottom solder mask layer of the substrate is a BGA pad region;
treating the upper surface of the silicon chip to form a drainage groove;
thinning the lower surface of the silicon chip to reach a preset thickness;
carrying out metal coating on the lower surface of the silicon chip to form back gold;
welding the back gold of the silicon chip with the surface of the substrate;
scribing the silicon chip to obtain an independent packaging structure with independent electrical performance;
bonding the silicon chip on the independent packaging structure with the substrate;
and plastically packaging the bonded independent packaging structure, and draining the plastic packaging material to the periphery of the silicon chip through the drainage grooves to form a plastic packaging material layer arranged around the silicon chip.
9. A method for processing a plastic package structure, which is used for processing the plastic package structure of any one of claims 1 to 7, wherein the method comprises the following steps:
providing a substrate and a silicon chip, wherein the substrate comprises multiple pins, a top solder mask layer of the substrate is a chip bonding region, and a bottom solder mask layer of the substrate is a BGA pad region;
thinning the lower surface of the silicon chip to reach a preset thickness, and performing metal coating on the lower surface of the silicon chip to form a back metal;
welding the back gold of the silicon chip and the surface of the substrate;
scribing the silicon chip to obtain an independent packaging structure with independent electrical performance;
treating the upper surface of the silicon chip on the single packaging structure to form a drainage groove;
bonding the silicon chip on the single packaging structure with the substrate;
and plastically packaging the bonded independent packaging structure, and draining the plastic packaging material to the periphery of the silicon chip through the drainage grooves to form a plastic packaging material layer arranged around the silicon chip.
CN202210545092.6A 2022-05-19 2022-05-19 Plastic package structure and processing method thereof Pending CN114783961A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202210545092.6A CN114783961A (en) 2022-05-19 2022-05-19 Plastic package structure and processing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202210545092.6A CN114783961A (en) 2022-05-19 2022-05-19 Plastic package structure and processing method thereof

Publications (1)

Publication Number Publication Date
CN114783961A true CN114783961A (en) 2022-07-22

Family

ID=82408197

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202210545092.6A Pending CN114783961A (en) 2022-05-19 2022-05-19 Plastic package structure and processing method thereof

Country Status (1)

Country Link
CN (1) CN114783961A (en)

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