CN114785295B - Ultra-wideband power amplifier and phased array transmitter - Google Patents
Ultra-wideband power amplifier and phased array transmitter Download PDFInfo
- Publication number
- CN114785295B CN114785295B CN202210708248.8A CN202210708248A CN114785295B CN 114785295 B CN114785295 B CN 114785295B CN 202210708248 A CN202210708248 A CN 202210708248A CN 114785295 B CN114785295 B CN 114785295B
- Authority
- CN
- China
- Prior art keywords
- transistor
- circuit
- capacitor
- ultra
- power amplifier
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 230000003321 amplification Effects 0.000 claims abstract description 49
- 238000003199 nucleic acid amplification method Methods 0.000 claims abstract description 49
- 239000003990 capacitor Substances 0.000 claims description 90
- 230000000903 blocking effect Effects 0.000 claims description 4
- 230000006641 stabilisation Effects 0.000 claims 1
- 238000011105 stabilization Methods 0.000 claims 1
- 230000006835 compression Effects 0.000 description 12
- 238000007906 compression Methods 0.000 description 12
- 238000004891 communication Methods 0.000 description 8
- 230000000087 stabilizing effect Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 229920006395 saturated elastomer Polymers 0.000 description 3
- 101100365516 Mus musculus Psat1 gene Proteins 0.000 description 2
- 230000008878 coupling Effects 0.000 description 2
- 238000010168 coupling process Methods 0.000 description 2
- 238000005859 coupling reaction Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000002708 enhancing effect Effects 0.000 description 2
- 238000010295 mobile communication Methods 0.000 description 2
- 102100036285 25-hydroxyvitamin D-1 alpha hydroxylase, mitochondrial Human genes 0.000 description 1
- 101000875403 Homo sapiens 25-hydroxyvitamin D-1 alpha hydroxylase, mitochondrial Proteins 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
- 230000003595 spectral effect Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/42—Modifications of amplifiers to extend the bandwidth
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/32—Modifications of amplifiers to reduce non-linear distortion
- H03F1/3211—Modifications of amplifiers to reduce non-linear distortion in differential amplifiers
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/56—Modifications of input or output impedances, not otherwise provided for
- H03F1/565—Modifications of input or output impedances, not otherwise provided for using inductive elements
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/189—High-frequency amplifiers, e.g. radio frequency amplifiers
- H03F3/19—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only
- H03F3/193—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only with field-effect devices
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
- H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
- H03F3/211—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only using a combination of several amplifiers
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/45—Differential amplifiers
- H03F3/45071—Differential amplifiers with semiconductor devices only
- H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
- H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/02—Transmitters
- H04B1/04—Circuits
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/02—Transmitters
- H04B1/04—Circuits
- H04B1/0458—Arrangements for matching and coupling between power amplifier and antenna or between amplifying stages
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2200/00—Indexing scheme relating to amplifiers
- H03F2200/36—Indexing scheme relating to amplifiers the amplifier comprising means for increasing the bandwidth
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2200/00—Indexing scheme relating to amplifiers
- H03F2200/451—Indexing scheme relating to amplifiers the amplifier being a radio frequency amplifier
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2200/00—Indexing scheme relating to amplifiers
- H03F2200/534—Transformer coupled at the input of an amplifier
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2200/00—Indexing scheme relating to amplifiers
- H03F2200/537—A transformer being used as coupling element between two amplifying stages
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
- H03F2203/45—Indexing scheme relating to differential amplifiers
- H03F2203/45051—Two or more differential amplifiers cascade coupled
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
- H03F2203/45—Indexing scheme relating to differential amplifiers
- H03F2203/45172—A transformer being added at the input of the dif amp
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
- H03F2203/45—Indexing scheme relating to differential amplifiers
- H03F2203/45228—A transformer being added at the output or the load circuit of the dif amp
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/02—Transmitters
- H04B1/04—Circuits
- H04B2001/0408—Circuits with power amplifiers
- H04B2001/0416—Circuits with power amplifiers having gain or transmission power control
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Amplifiers (AREA)
Abstract
The invention discloses an ultra-wideband power amplifier and a phased array transmitter, wherein the ultra-wideband power amplifier comprises an input matching circuit, a first-stage amplifying circuit, an interelectrode matching circuit, a second-stage amplifying circuit, an output matching circuit, a first negative feedback circuit and a second negative feedback circuit; the input matching circuit, the first-stage amplification circuit, the interelectrode matching circuit, the second-stage amplification circuit and the output matching circuit are sequentially connected; the first negative feedback circuit is bridged between the input end of the first-stage amplification circuit and the output end of the interelectrode matching circuit; the second negative feedback circuit is an active negative feedback circuit and is bridged at the input end and the output end of the second-stage amplification circuit, wherein the second-stage amplification circuit is a multi-gate pseudo-differential cascode amplification circuit, and the gain and linearity performance of the ultra-wideband power amplifier in the working bandwidth are improved; the phased array transmitter comprises the ultra-wideband power amplifier. The invention can expand the working bandwidth and has higher gain and better linearity.
Description
Technical Field
The invention relates to an ultra-wideband power amplifier and a phased array transmitter, and belongs to the technical field of radio frequency integrated circuits.
Background
The power amplifier is an important component in a mobile communication system, and plays a role in amplifying communication signal power to increase a signal transmission distance and improve communication quality.
With the rapid development of the fifth generation mobile communication (5G) technology, the communication frequency is increased to the millimeter wave band, and the global main 5G millimeter wave communication band comprises n257 (26.5-29.5 GHz), n258 (24.25-27.5 GHz), n259 (39.5-43.5 GHz), n260 (37-40 GHz) and n261 (27.5-28.35 GHz), and the total bandwidth is up to 11.75GHz. In addition, atmospheric attenuation of wireless signals in the millimeter wave frequency band is severe. To overcome the spatial path loss in the millimeter wave band, the 5G millimeter wave system output signal needs to have sufficient power, and the communication link will rely on directional communication and be implemented by phased array technology. The 5G millimeter wave system puts higher requirements on the working frequency band and bandwidth of the power amplifier and the phased array transmitter. The ultra-wideband millimeter wave power amplifier and the phased array transmitter capable of covering the frequency bands can support a 5G millimeter wave system of a global main frequency band, realize international roaming, and have huge commercial value and wide development prospect.
It is expected that a 5G millimeter wave system will support broadband efficient spectral modulation (e.g., 64-QAM and 256-QAM) to achieve Gb/s link throughput. These complex modulation schemes require high linearity of the power amplifier.
Therefore, designing a power amplifier that can provide sufficient output power, wide band, and high linearity has important engineering application value.
Disclosure of Invention
Based on this, the present invention provides a power amplifier and a phased array transmitter capable of realizing ultra wide band and high linearity, which not only can meet the requirements of the millimeter wave communication system, but also is applicable to other communication frequency bands such as microwave.
A first object of the present invention is to provide a power amplifier.
A second object of the present invention is to provide a phased array transmitter.
The first purpose of the invention can be achieved by adopting the following technical scheme:
an ultra-wideband power amplifier comprises an input matching circuit, a first-stage amplification circuit, an interelectrode matching circuit, a second-stage amplification circuit, an output matching circuit, a first negative feedback circuit and a second negative feedback circuit; the input matching circuit, the first-stage amplification circuit, the interelectrode matching circuit, the second-stage amplification circuit and the output matching circuit are sequentially connected;
the first negative feedback circuit is bridged between the input end of the first-stage amplification circuit and the output end of the interelectrode matching circuit and is used for expanding the working bandwidth of the amplifier and improving the input matching performance;
the second negative feedback circuit is an active negative feedback circuit and is bridged at the input end and the output end of the second-stage amplification circuit, wherein the second-stage amplification circuit is a multi-gate pseudo-differential cascode amplification circuit and is used for realizing the gain and linearity performance improvement of the ultra-wideband power amplifier in the working bandwidth;
the input matching circuit is used for realizing broadband impedance matching between a signal input end and the first-stage amplifying circuit, and a first end of the input matching circuit is used as an input end of the ultra-wideband power amplifier;
the interelectrode matching circuit is used for realizing broadband impedance matching between the first-stage amplification circuit and the second-stage amplification circuit;
the output matching circuit is used for realizing broadband impedance matching between the second-stage amplifying circuit and the signal output end, and the second end of the output matching circuit is used as the output end of the ultra-wideband power amplifier.
Further, the first-stage amplifying circuit comprises a pseudo-differential structure amplifying circuit, the pseudo-differential structure amplifying circuit comprises a first transistor and a second transistor, source electrodes of the first transistor and the second transistor are grounded, grid electrodes of the first transistor and the second transistor are connected with the input matching circuit, and drain electrodes of the first transistor and the second transistor are connected with the interelectrode matching circuit.
Further, the first-stage amplifying circuit further comprises a gain enhancing network, wherein the gain enhancing network comprises a first capacitor and a second capacitor;
the first ends of the first capacitor and the second capacitor are respectively connected with the drains of the first transistor and the second transistor, the second end of the first capacitor is connected with the grid of the second transistor, and the second end of the second capacitor is connected with the grid of the first transistor.
Further, the multi-gate pseudo-differential cascode amplifying circuit comprises two pairs of cascode transistors and a pair of cascode transistors.
Further, the cascode transistors include a third transistor, a fourth transistor, a fifth transistor and a sixth transistor, and the common-gate transistor includes a seventh transistor and an eighth transistor;
the drains of the third transistor and the fifth transistor are connected with the source electrode of the seventh transistor, and the source electrodes of the third transistor and the fifth transistor are grounded;
the drains of the fourth transistor and the sixth transistor are connected with the source of the eighth transistor, and the sources of the fourth transistor and the sixth transistor are grounded;
the grid electrodes of the third transistor and the fourth transistor are connected with the inter-electrode matching circuit after being connected with the blocking capacitor in series, and the grid electrodes of the fifth transistor and the sixth transistor are directly connected with the inter-electrode matching circuit;
in the multi-gate pseudo-differential cascode amplification circuit, the third transistor and the fourth transistor use a first bias voltage, and the fifth transistor and the sixth transistor use a second bias voltage.
Further, the second-stage amplification circuit further comprises a gain enhancement network, and the gain enhancement network comprises a third capacitor and a fourth capacitor;
first ends of the third capacitor and the fourth capacitor are respectively connected with drains of the fifth transistor and the sixth transistor, a second end of the third capacitor is connected with a grid of the sixth transistor, and a second end of the fourth capacitor is connected with a grid of the fifth transistor.
Further, the second-stage amplifying circuit further comprises a stabilizing circuit, and the stabilizing circuit comprises a fifth capacitor and a sixth capacitor;
first ends of the fifth capacitor and the sixth capacitor are respectively connected with drain electrodes of the seventh transistor and the eighth transistor, a second end of the fifth capacitor is connected with a source electrode of the eighth transistor, and a second end of the sixth capacitor is connected with a source electrode of the seventh transistor.
Further, the second negative feedback circuit comprises a first feedback branch and a second feedback branch;
the first end of the first feedback branch circuit is connected with the input end of the second-stage amplifying circuit, and the second end of the first feedback branch circuit is connected with the output end of the second-stage amplifying circuit;
and the first end of the second feedback branch circuit is connected with the input end of the second-stage amplifying circuit, and the second end of the second feedback branch circuit is connected with the output end of the second-stage amplifying circuit.
Further, the first feedback branch and the second feedback branch have the same structure and include a ninth transistor, a tenth transistor, an eleventh transistor, a first resistor, a second resistor, a third resistor, a fourth resistor, and a seventh capacitor, where a first end of the fourth resistor is used as a first end of the first feedback branch and the second feedback branch, and a drain of the ninth transistor is used as a second end of the first feedback branch and the second feedback branch;
the grid electrode of the ninth transistor is connected with the first end of the first resistor, the source electrode of the ninth transistor is connected with the first end of the seventh capacitor, and the second end of the first resistor is connected with bias voltage;
the grid electrode of the tenth transistor is connected with the second end of the seventh capacitor and the first end of the second resistor, the drain electrode of the tenth transistor is connected with the power supply voltage, the source electrode of the tenth transistor is connected with the drain electrode of the eleventh transistor, and the second end of the second resistor is connected with the bias voltage;
the grid electrode of the eleventh transistor is connected with the drain electrode of the eleventh transistor, the source electrode of the eleventh transistor is connected with the first end of the third resistor, the second end of the third resistor is connected with the first end of the fourth resistor, and the second end of the fourth resistor is grounded.
The second purpose of the invention can be achieved by adopting the following technical scheme:
a phased array transmitter comprises the ultra-wideband power amplifier.
Compared with the prior art, the invention has the following beneficial effects:
the ultra-wideband power amplifier comprises an input matching circuit, a first-stage amplifying circuit, an interelectrode matching circuit, a second-stage amplifying circuit, an output matching circuit, a first negative feedback circuit and a second negative feedback circuit, wherein the input matching circuit can realize wideband impedance matching between a signal input end and the first-stage amplifying circuit, the interelectrode matching circuit can realize wideband impedance matching between the first-stage amplifying circuit and the second-stage amplifying circuit, the gain of the ultra-wideband power amplifier can be improved through the second-stage amplifying circuit, and the linearity of the ultra-wideband power amplifier is improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a block diagram of an ultra-wideband power amplifier according to an embodiment of the present invention.
Fig. 2 is a schematic circuit diagram of an ultra-wideband power amplifier according to an embodiment of the present invention.
Fig. 3 is a graph of experimental results of the variation of gain and return loss with frequency of the ultra-wideband power amplifier according to the embodiment of the present invention.
Fig. 4 is a graph of experimental results of variations with frequency of a saturated output power (Psat), an output 1dB compression point (OP 1 dB), and an input 1dB compression point (IP 1 dB) of an ultra-wideband power amplifier according to an embodiment of the present invention.
Fig. 5 is a graph of experimental results of Peak Additional Efficiency (PAE), additional efficiency at a 1dB compression point (PAE @ p1db), and direct current power consumption at the 1dB compression point (pdc @ p1db) varying with frequency of the ultra-wideband power amplifier according to the embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Example (b):
as shown in fig. 1, the present embodiment provides an ultra-wideband power amplifier that may be applied in a phased array transmitter, and includes an input matching circuit 101, a first-stage amplification circuit 102, an inter-pole matching circuit 103, a second-stage amplification circuit 104, an output matching circuit 105, a first negative feedback circuit 106, and a second negative feedback circuit 107.
The input matching circuit 101 is configured to implement wideband impedance matching between a signal input end and the first-stage amplifying circuit 102, and a first end of the input matching circuit 101 is used as an input end of the ultra-wideband power amplifier.
The input terminal of the first-stage amplifier circuit 102 is connected to the second terminal of the input matching circuit 101, and the output terminal of the first-stage amplifier circuit 102 is connected to the first terminal of the inter-pole matching circuit 103.
The second stage amplification circuit 104 can increase the gain of the ultra-wideband power amplifier and improve the linearity thereof; the input terminal of the second-stage amplification circuit 104 is connected to the second terminal of the inter-electrode matching circuit 103, and the output terminal of the second-stage amplification circuit 104 is connected to the first terminal of the output matching circuit 105.
And the inter-electrode matching circuit 103 is configured to implement broadband impedance matching between the first-stage amplification circuit 102 and the second-stage amplification circuit 104.
And the output matching circuit 105 is used for realizing the broadband impedance matching between the second-stage amplifying circuit 104 and the signal output end, and a second end of the output matching circuit 105 is used as the output end of the ultra-wideband power amplifier.
The first end of the first negative feedback circuit 106 is connected to the input end of the first stage amplifier circuit 102, the second end of the first negative feedback circuit 106 is connected to the input end of the second stage amplifier circuit 104, and the first negative feedback circuit 106 can extend the working bandwidth and improve the input matching.
The first end of the second negative feedback circuit 107 is connected with the input end of the second-stage amplification circuit 104, the second end of the second negative feedback circuit 107 is connected with the output end of the second-stage amplification circuit 104, and the second negative feedback circuit 107 can improve the OP1dB under the condition that the gain of the ultra-wideband power amplifier is not changed, and provide a path of bias voltage for the second-stage amplification circuit 104.
As shown in fig. 2, which is a schematic diagram of the circuit structure of the ultra-wideband power amplifier of this embodiment, the signal input terminal is represented by Vin + and Vin-in fig. 2, and the signal output terminal is represented by Vout in fig. 2.
In this embodiment, the first-stage amplifying circuit includes a pseudo-differential structure amplifying circuit, the pseudo-differential structure amplifying circuit includes a first transistor M1 and a second transistor M2, sources of the first transistor M1 and the second transistor M2 are grounded, gates of the first transistor M1 and the second transistor M2 are connected to the input matching circuit, and drains of the first transistor M1 and the second transistor M2 are connected to the inter-electrode matching circuit.
Further, the first-stage amplifying circuit further comprises a gain enhancement network, wherein the gain enhancement network comprises a first capacitor C4 and a second capacitor C5; first ends of the first capacitor C4 and the second capacitor C5 are respectively connected to drains of the first transistor M1 and the second transistor M2, a second end of the first capacitor C4 is connected to a gate of the second transistor M2, and a second end of the second capacitor C5 is connected to a gate of the first transistor M1.
In this embodiment, the second-stage amplifying circuit is a multi-gate pseudo-differential cascode amplifying circuit, and is configured to improve the gain and linearity performance of the ultra-wideband power amplifier within a working bandwidth.
Further, the cascode transistor includes a third transistor M3, a fourth transistor M4, a fifth transistor M5, and a sixth transistor M6, and the common-gate transistor includes a seventh transistor M7 and an eighth transistor M8; the drains of the third transistor M3 and the fifth transistor M5 are connected with the source of the seventh transistor M7, and the sources of the third transistor M3 and the fifth transistor M5 are grounded; the drains of the fourth transistor M4 and the sixth transistor M6 are connected to the source of the eighth transistor M8, and the sources of the fourth transistor M4 and the sixth transistor M6 are grounded; the gates of the third transistor M3 and the fourth transistor M4 are connected in series with the dc blocking capacitor and then connected to the inter-electrode matching circuit, and the gates of the fifth transistor M5 and the sixth transistor M6 are directly connected to the inter-electrode matching circuit.
Further, the second-stage amplifying circuit further comprises a gain enhancement network, wherein the gain enhancement network comprises a third capacitor C9 and a fourth capacitor C10; first ends of the third capacitor C9 and the fourth capacitor C10 are respectively connected to drains of the fifth transistor M5 and the sixth transistor M6, a second end of the third capacitor C9 is connected to a gate of the sixth transistor M6, and a second end of the fourth capacitor C10 is connected to a gate of the fifth transistor M5.
In this embodiment, the second-stage amplifying circuit further includes a stabilizing circuit, and the stabilizing circuit includes a fifth capacitor C11 and a sixth capacitor C12; first ends of a fifth capacitor C11 and a sixth capacitor C12 are respectively connected with drains of the seventh transistor M7 and the eighth transistor M8, a second end of the fifth capacitor C11 is connected with a source of the eighth transistor M8, and a second end of the sixth capacitor C12 is connected with a source of the seventh transistor M7.
In this embodiment, the second negative feedback circuit is an active negative feedback circuit, which includes a first feedback branch and a second feedback branch; the first end of the first feedback branch circuit is connected with the input end of the second-stage amplification circuit, and the second end of the first feedback branch circuit is connected with the output end of the second-stage amplification circuit; the first end of the second feedback branch circuit is connected with the input end of the second-stage amplifying circuit, and the second end of the second feedback branch circuit is connected with the output end of the second-stage amplifying circuit.
Further, the first feedback branch and the second feedback branch have the same structure, and this embodiment is described with reference to the first feedback branch, which includes a ninth transistor M9, a tenth transistor M11, an eleventh transistor M13, a seventh resistor R11, a second resistor R9, a third resistor R7, a fourth resistor R5, and a seventh capacitor C13, where a first end of the fourth resistor R5 is used as a first end of the first feedback branch, and a drain of the ninth transistor M9 is used as a second end of the first feedback branch; a gate of the ninth transistor M9 is connected to a first end of the seventh resistor R11, a source of the ninth transistor M9 is connected to a first end of the seventh capacitor C13, and a second end of the seventh resistor R11 is connected to the bias voltage VL; a gate of the tenth transistor M11 is connected to the second end of the seventh capacitor C13 and to the first end of the second resistor R9, a drain of the tenth transistor M11 is connected to the power supply voltage VDD2, a source of the tenth transistor M11 is connected to a drain of the eleventh transistor M13, and a second end of the second resistor R9 is connected to the bias voltage VL; a gate of the eleventh transistor M13 is connected to a drain of the eleventh transistor M13, a source of the eleventh transistor M13 is connected to a first end of the third resistor R7, a second end of the third resistor R7 is connected to a first end of the fourth resistor R5, and a second end of the fourth resistor R5 is grounded; it is easily understood that the ninth transistor, the tenth transistor, the eleventh transistor, the first resistor, the second resistor, the third resistor, the fourth resistor, and the seventh capacitor of the second feedback branch are M10, M12, M14, R12, R10, R8, R6, and C14 in fig. 2, respectively, a first end of the fourth resistor R6 serves as a first end of the second feedback branch, and a drain of the ninth transistor M10 serves as a second end of the second feedback branch.
Further, the first end of the first feedback branch is connected with the input end of the second-stage amplification circuit, specifically, the drain of a seventh transistor M7 of the second-stage amplification circuit; the second end of the first feedback branch is connected with the output end of the second-stage amplification circuit, and is specifically connected with the gate of the fifth transistor M5 of the second-stage amplification circuit.
Further, a first end of the second feedback branch is connected to an input end of the second-stage amplification circuit, specifically, to a drain of an eighth transistor M8 of the second-stage amplification circuit; the second end of the second feedback branch is connected with the output end of the second-stage amplification circuit, and specifically connected with the gate of a sixth transistor M6 of the second-stage amplification circuit.
Further, the first feedback branch and the second feedback branch also have the function of providing a bias voltage Vb3 for the fifth transistor M5 and the sixth transistor M6 of the second-stage amplifying circuit.
Optionally, the input matching circuit includes an eighth capacitor C1, a ninth capacitor C2, a first inductor L1, a second inductor L2, and a first transformer TF1; the first transformer TF1 comprises a third inductor L3 and a fourth inductor L4, and there is a coupling between the third inductor L3 and the fourth inductor L4; a first end of the eighth capacitor C1 is connected with Vin +, and a second end of the eighth capacitor C1 is connected with Vin-; a first end of the first inductor L1 is connected to a first end of the eighth capacitor C1, and a second end of the first inductor L1 is connected to first ends of the ninth capacitor C2 and the third inductor L3; a first end of the second inductor L2 is connected to a second end of the eighth capacitor C1, and a second end of the second inductor L2 is connected to second ends of the ninth capacitor C2 and the third inductor L3.
Further, the gates of the first transistor M1 and the second transistor M2 are connected to the input matching circuit, specifically: the gates of the first transistor M1 and the second transistor M2 are connected to the first end and the second end of the fourth inductor L4, respectively; the bias voltage Vb1 of the gate of the first transistor M1 and the gate of the second transistor M2 is provided by the center tap of the fourth inductor L4; first ends of the first capacitor C4 and the second capacitor C5 are respectively connected to drains of the first transistor M1 and the second transistor M2, a second end of the first capacitor C4 is connected to a gate of the second transistor M2, and a second end of the second capacitor C5 is connected to a gate of the first transistor M1.
Optionally, the inter-electrode matching circuit includes a fifth inductor L5 and a sixth inductor L6, there is a coupling between the fifth inductor L5 and the sixth inductor L6, and the drains of the first transistor M1 and the second transistor M2 are connected to the inter-electrode matching circuit, specifically: the drains of the first transistor M1 and the second transistor M2 are respectively connected to the first end and the second end of the fifth inductor L5, and the middle tap of the fifth inductor L5 provides the power supply voltage VDD1 for the first stage of the amplifying circuit.
The gates of the third transistor M3 and the fourth transistor M4 are connected in series with the dc blocking capacitors (the third capacitor C9 and the fourth capacitor C10) and then connected to the inter-electrode matching circuit, and the gates of the fifth transistor M5 and the sixth transistor M6 are directly connected to the inter-electrode matching circuit, specifically: the gates of the fifth transistor M5 and the sixth transistor M6 are respectively connected to the first end and the second end of the sixth inductor L6, the gate of the third transistor M3 is connected to the first end of the third capacitor C9, the gate of the fourth transistor M4 is connected to the first end of the fourth capacitor C10, and the second ends of the third capacitor C9 and the fourth capacitor C10 are connected to the first end and the second end of the sixth inductor L6.
Optionally, the multi-gate pseudo-differential cascode amplifying circuit further includes a first bias circuit, where the first bias circuit includes a fifth resistor R3 and a sixth resistor R4; first ends of a fifth resistor R3 and a sixth resistor R4 are connected with the first bias voltage Vb2, a second end of the fifth resistor R3 is connected with a grid electrode of the third transistor M3, and a second end of the sixth resistor R4 is connected with a grid electrode of the fourth transistor M4; the third transistor M3 and the fourth transistor M4 use a first bias voltage Vb2, the fifth transistor M5 and the sixth transistor M6 use a second bias voltage Vb3, and the first bias voltage Vb2 and the second bias voltage Vb3 may be the same or different voltages.
Optionally, the first negative feedback circuit includes an eighth capacitor C3, a ninth capacitor C4, a seventh resistor R1, and an eighth resistor R2; a first end of the eighth capacitor C3 is connected to a first end of the fourth inductor L4 of the first transformer TF1, a second end of the eighth capacitor C3 is connected to a first end of the seventh resistor R1, and a second end of the seventh resistor R1 is connected to a second end of the sixth inductor L6; a first end of the ninth capacitor C4 is connected to the second end of the fourth inductor L4 of the first transformer TF1, a second end of the ninth capacitor C4 is connected to a first end of the eighth resistor R2, and a second end of the eighth resistor R2 is connected to a first end of the sixth inductor L6.
The ultra-wideband power amplifier can achieve larger bandwidth, higher gain and linearity, and can be specifically referred to fig. 3, fig. 4 and fig. 5.
As shown in fig. 3, it is a graph of experimental results of gain and return loss of the ultra-wideband power amplifier of this embodiment; it can be seen that in the frequency range of 22-44GHz, the small signal gain (S21) is 24.3dB, and the gain flatness is +/-0.9 dB; meanwhile, the input return loss (S11) is less than-7.7 dB in the frequency range of 22-44GHz, and the output return loss (S22) is less than-2 dB in the frequency range of 22-44 GHz.
As shown in fig. 4, which is a graph of experimental results of the saturated output power (Psat), the output 1dB compression point (OP 1 dB), and the input 1dB compression point (IP 1 dB) of the ultra-wideband power amplifier of the present embodiment, it can be seen that, in the frequency range of 22-44GHz, the saturated output power is 18.8 to 19.9dBm, the output 1dB compression point is 15.4 to 18.5dBm, and the input 1dB compression point is-6.7 to-3.7 dBm. The experimental result shows that the ultra-wideband power amplifier has larger saturation output power and higher linearity in the working frequency band.
As shown in fig. 5, it is a graph of experimental results of maximum Power Added Efficiency (PAE), power added efficiency at 1dB compression point (PAE @ p1db), and direct current power consumption at 1dB compression point (pdc @ p1db) of the ultra-wideband power amplifier of the present embodiment; it can be seen that in the frequency range of 22-44GHz, the maximum power added efficiencies are all greater than 23.9%, the power added efficiencies at the 1dB compression points are all greater than 15.8%, and the direct current power consumption at the 1dB compression points is less than 328mW. The experimental result shows that the ultra-wideband power amplifier has better efficiency in a wideband range.
In summary, the ultra-wideband power amplifier of the present invention includes an input matching circuit, a first stage amplifying circuit, an inter-electrode matching circuit, a second stage amplifying circuit, an output matching circuit, a first negative feedback circuit and a second negative feedback circuit, wherein the input matching circuit can implement wideband impedance matching between a signal input terminal and the first stage amplifying circuit, the inter-electrode matching circuit can implement wideband impedance matching between the first stage amplifying circuit and the second stage amplifying circuit, the gain of the ultra-wideband power amplifier can be increased and the linearity thereof can be improved by the second stage amplifying circuit, the first negative feedback circuit is bridged between the input terminal of the first stage amplifying circuit and the input terminal of the second stage amplifying circuit, the working bandwidth can be extended and the input matching can be improved, the second negative feedback circuit is bridged between the input terminal and the output terminal of the second stage amplifying circuit, the OP1dB can be increased under the condition that the gain of the ultra-wideband power amplifier is not changed, and a path of bias voltage can be provided for the multi-gate amplifying circuit, so that the present invention can extend the working bandwidth, has higher gain and better linearity of the wideband, and can implement linear amplification of the power and higher output power.
The technical features of the above embodiments can be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the above embodiments are not described in detail, but should be considered as the scope of the present description as long as there is no contradiction between the combinations of the technical features.
The above embodiments only show some embodiments of the present invention, which are described in detail and detail, but not to be understood as limiting the scope of the invention, it should be noted that, for those skilled in the art, various changes and modifications can be made without departing from the concept of the present invention, and these embodiments are all within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.
Claims (10)
1. An ultra-wideband power amplifier is characterized by comprising an input matching circuit, a first-stage amplifying circuit, an interelectrode matching circuit, a second-stage amplifying circuit, an output matching circuit, a first negative feedback circuit and a second negative feedback circuit; the input matching circuit, the first-stage amplifying circuit, the interelectrode matching circuit, the second-stage amplifying circuit and the output matching circuit are connected in sequence;
the first negative feedback circuit is bridged between the input end of the first-stage amplification circuit and the output end of the interelectrode matching circuit and is used for expanding the working bandwidth of the amplifier and improving the input matching performance;
the second negative feedback circuit is an active negative feedback circuit and is bridged at the input end and the output end of the second-stage amplification circuit, wherein the second-stage amplification circuit is a multi-gate pseudo-differential cascode amplification circuit and is used for realizing the improvement of the gain and linearity performance of the ultra-wideband power amplifier in the working bandwidth;
the input matching circuit is used for realizing broadband impedance matching between a signal input end and the first-stage amplifying circuit, and a first end of the input matching circuit is used as an input end of the ultra-wideband power amplifier;
the interelectrode matching circuit is used for realizing broadband impedance matching between the first-stage amplification circuit and the second-stage amplification circuit;
the output matching circuit is used for realizing broadband impedance matching between the second-stage amplifying circuit and the signal output end, and the second end of the output matching circuit is used as the output end of the ultra-wideband power amplifier.
2. The ultra-wideband power amplifier of claim 1, wherein the first stage amplifier circuit comprises a pseudo-differential amplifier circuit, the pseudo-differential amplifier circuit comprising a first transistor and a second transistor, sources of the first transistor and the second transistor being connected to ground, gates of the first transistor and the second transistor being connected to the input matching circuit, and drains of the first transistor and the second transistor being connected to the inter-pole matching circuit.
3. The ultra-wideband power amplifier of claim 2, wherein the first stage amplification circuit further comprises a gain enhancement network comprising a first capacitance and a second capacitance;
the first ends of the first capacitor and the second capacitor are respectively connected with the drains of the first transistor and the second transistor, the second end of the first capacitor is connected with the grid of the second transistor, and the second end of the second capacitor is connected with the grid of the first transistor.
4. The ultra-wideband power amplifier of claim 1, wherein the multi-gate pseudo-differential cascode amplification circuit comprises two pairs of cascode transistors and a pair of common-gate transistors.
5. The ultra-wideband power amplifier of claim 4, wherein the cascode transistors include a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor, and the common-gate transistors include a seventh transistor and an eighth transistor;
the drains of the third transistor and the fifth transistor are connected with the source electrode of the seventh transistor, and the source electrodes of the third transistor and the fifth transistor are grounded;
the drains of the fourth transistor and the sixth transistor are connected with the source of the eighth transistor, and the sources of the fourth transistor and the sixth transistor are grounded;
the grid electrodes of the third transistor and the fourth transistor are connected with the inter-electrode matching circuit after being connected with the blocking capacitor in series, and the grid electrodes of the fifth transistor and the sixth transistor are directly connected with the inter-electrode matching circuit;
in the multi-gate pseudo-differential cascode amplifying circuit, the third transistor and the fourth transistor use a first bias voltage, and the fifth transistor and the sixth transistor use a second bias voltage.
6. The ultra-wideband power amplifier of claim 5, wherein the second stage amplification circuit further comprises a gain enhancement network comprising a third capacitor and a fourth capacitor;
first ends of the third capacitor and the fourth capacitor are respectively connected with drains of the fifth transistor and the sixth transistor, a second end of the third capacitor is connected with a grid of the sixth transistor, and a second end of the fourth capacitor is connected with a grid of the fifth transistor.
7. The ultra-wideband power amplifier of claim 5, wherein the second stage amplification circuit further comprises a stabilization circuit comprising a fifth capacitor and a sixth capacitor;
first ends of the fifth capacitor and the sixth capacitor are respectively connected with drain electrodes of the seventh transistor and the eighth transistor, a second end of the fifth capacitor is connected with a source electrode of the eighth transistor, and a second end of the sixth capacitor is connected with a source electrode of the seventh transistor.
8. The ultra-wideband power amplifier according to any of claims 1-7, wherein the second negative feedback circuit comprises a first feedback branch and a second feedback branch;
the first end of the first feedback branch circuit is connected with the input end of the second-stage amplifying circuit, and the second end of the first feedback branch circuit is connected with the output end of the second-stage amplifying circuit;
and the first end of the second feedback branch circuit is connected with the input end of the second-stage amplifying circuit, and the second end of the second feedback branch circuit is connected with the output end of the second-stage amplifying circuit.
9. The ultra-wideband power amplifier according to claim 8, wherein the first feedback branch and the second feedback branch have the same structure, and include a ninth transistor, a tenth transistor, an eleventh transistor, a first resistor, a second resistor, a third resistor, a fourth resistor, and a seventh capacitor, a first end of the fourth resistor serves as a first end of the first feedback branch and the second feedback branch, and a drain of the ninth transistor serves as a second end of the first feedback branch and the second feedback branch;
the grid electrode of the ninth transistor is connected with the first end of the first resistor, the source electrode of the ninth transistor is connected with the first end of the seventh capacitor, and the second end of the first resistor is connected with the bias voltage;
a grid electrode of the tenth transistor is connected with a second end of the seventh capacitor and a first end of the second resistor, a drain electrode of the tenth transistor is connected with a power supply voltage, a source electrode of the tenth transistor is connected with a drain electrode of the eleventh transistor, and a second end of the second resistor is connected with a bias voltage;
the grid electrode of the eleventh transistor is connected with the drain electrode of the eleventh transistor, the source electrode of the eleventh transistor is connected with the first end of the third resistor, the second end of the third resistor is connected with the first end of the fourth resistor, and the second end of the fourth resistor is grounded.
10. A phased array transmitter comprising an ultra-wideband power amplifier as claimed in any one of claims 1 to 9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210708248.8A CN114785295B (en) | 2022-06-22 | 2022-06-22 | Ultra-wideband power amplifier and phased array transmitter |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210708248.8A CN114785295B (en) | 2022-06-22 | 2022-06-22 | Ultra-wideband power amplifier and phased array transmitter |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN114785295A CN114785295A (en) | 2022-07-22 |
| CN114785295B true CN114785295B (en) | 2022-10-25 |
Family
ID=82422467
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210708248.8A Active CN114785295B (en) | 2022-06-22 | 2022-06-22 | Ultra-wideband power amplifier and phased array transmitter |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN114785295B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115567016A (en) * | 2022-10-26 | 2023-01-03 | 深圳飞骧科技股份有限公司 | Two-stage differential power amplifier and radio frequency power amplifier module |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN204425279U (en) * | 2015-03-26 | 2015-06-24 | 成都爱洁隆信息技术有限公司 | A kind of high-gain low-noise amplifier |
| CN211209671U (en) * | 2019-12-20 | 2020-08-07 | 成都嘉纳海威科技有限责任公司 | Millimeter wave ultra-wideband high-gain low-power-consumption low-noise amplifier chip circuit |
| CN113872533A (en) * | 2021-12-02 | 2021-12-31 | 华南理工大学 | Power amplifier and transmitter |
| CN114244295A (en) * | 2021-11-09 | 2022-03-25 | 中电国基南方集团有限公司 | Ultra-wideband high-voltage high-power amplifier circuit |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE10135113B4 (en) * | 2001-07-19 | 2009-04-09 | Infineon Technologies Ag | Pseudo-differential power driver for amplifying a differential input current |
| KR100667303B1 (en) * | 2005-02-01 | 2007-01-12 | 삼성전자주식회사 | Low noise amplifier for ultra-wide band |
| EP2313970B1 (en) * | 2008-07-17 | 2013-09-04 | Stichting IMEC Nederland | Dual-loop feedback amplifying circuit |
| DE102019205114B4 (en) * | 2019-04-10 | 2022-02-10 | Siemens Healthcare Gmbh | Single-stage amplifier with active feedback compensation |
-
2022
- 2022-06-22 CN CN202210708248.8A patent/CN114785295B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN204425279U (en) * | 2015-03-26 | 2015-06-24 | 成都爱洁隆信息技术有限公司 | A kind of high-gain low-noise amplifier |
| CN211209671U (en) * | 2019-12-20 | 2020-08-07 | 成都嘉纳海威科技有限责任公司 | Millimeter wave ultra-wideband high-gain low-power-consumption low-noise amplifier chip circuit |
| CN114244295A (en) * | 2021-11-09 | 2022-03-25 | 中电国基南方集团有限公司 | Ultra-wideband high-voltage high-power amplifier circuit |
| CN113872533A (en) * | 2021-12-02 | 2021-12-31 | 华南理工大学 | Power amplifier and transmitter |
Non-Patent Citations (2)
| Title |
|---|
| A 2–10GHz ultra-wideband high gain negative feedback low-noise amplifier;Peigen Zhou 等;《IEEE》;20161201;第1-3页 * |
| 一种3_5GHz超宽带单端输入差分输出LNA;郑羽等;《微电子学与计算机》;20140630;第31卷(第6期);第103-106页 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN114785295A (en) | 2022-07-22 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPWO2007015462A1 (en) | High efficiency amplifier | |
| CN111510076B (en) | class-AB driven Doherty power amplifier, base station and mobile terminal | |
| CN215990714U (en) | Radio frequency power amplifier and radio frequency front end architecture applied to 5G communication system | |
| CN114793094B (en) | Adjustable gain low noise amplifier and receiver | |
| CN113938102A (en) | Broadband high-efficiency power amplifier and implementation method | |
| CN102111113A (en) | Cascaded multistage radio frequency power amplifier and front-end transmitter in series | |
| CN111277232B (en) | Ultra-wideband amplifier unit circuit based on improved TIA | |
| US6122532A (en) | RF amplifier with reduced power consumption | |
| CN112260654B (en) | Power amplifier system | |
| CN114785295B (en) | Ultra-wideband power amplifier and phased array transmitter | |
| CN102111112A (en) | Radio frequency power amplifier and front-end transmitter | |
| CN112019169A (en) | Broadband high-gain Doherty power amplifier and implementation method thereof | |
| Gu et al. | A 23-30 GHz 4-Path Series-Parallel-Combined Class-AB Power Amplifier with 23 dBm P sat, 38.5% Peak PAE and 1.3° AM-PM Distortion in 40nm Bulk CMOS | |
| CN117639683A (en) | Balun-based high-OIP 2 balance amplifier | |
| CN115913155B (en) | High-linearity power amplifier suitable for 5G system | |
| CN114759885B (en) | Ultra-wideband variable gain amplifier, wireless communication device and gain adjusting method | |
| CN113904635B (en) | High third-order intermodulation point field effect transistor radio frequency amplifier | |
| CN112087206B (en) | Ultra-low power consumption broadband low noise amplifier | |
| Tan et al. | 2–20 GHz ultra-wideband distributed low noise amplifier | |
| CN110719077B (en) | Power amplifier and electronic equipment | |
| US20120086511A1 (en) | Distributed power amplifier with active matching | |
| KR101517852B1 (en) | Mixer mmic with feedback circuit | |
| Singh et al. | Design and performance analysis of broadband Doherty power amplifier for 5G communication system | |
| CN217159562U (en) | Circuit with double topological structures | |
| CN115149911B (en) | Ultra-wideband front-end chip, control method and design method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |