CN114759879A

CN114759879A - Push-push based frequency doubler and frequency tripler

Info

Publication number: CN114759879A
Application number: CN202210549941.5A
Authority: CN
Inventors: 刘岗; 吴韵秋
Original assignee: Chengdu Tongliang Technology Co ltd
Current assignee: Chengdu Tongliang Technology Co ltd
Priority date: 2022-05-20
Filing date: 2022-05-20
Publication date: 2022-07-15
Anticipated expiration: 2042-05-20
Also published as: CN114759879B

Abstract

The invention provides a push-push based frequency doubler, which comprises an NMOS (N-channel metal oxide semiconductor) transistor M1, an NMOS transistor M2, a neutralization capacitor Cp1, a neutralization capacitor Cp2 and a transformer TR 2; one end of a primary coil of the transformer TR1 is connected with a Port _ I N end, the other end is grounded, one end of a secondary coil of the transformer TR1 is connected with the grid of the NMOS transistor M1 and one end of the neutralization capacitor Cp1, the other end of the secondary coil of the transformer TR1 is connected with the grid of the NMOS transistor M2 and one end of the neutralization capacitor Cp 2. The invention is based on a push-push structure, and adds a neutralization capacitor, thereby improving the conversion gain of the frequency multiplier. Meanwhile, the secondary signal and the tertiary signal are distinguished and extracted by using a transformer. For the third harmonic signal, I LB is adopted for buffer amplification, and the fundamental wave suppression degree of the third harmonic signal is improved. And secondary and tertiary signals are output simultaneously, so that the output bandwidth of the circuit is improved, and the whole layout area and power consumption are reduced by the structure.

Description

Push-push based frequency doubler and frequency tripler

Technical Field

The invention belongs to the technical field of wireless communication, and particularly relates to a push-push based frequency two-three multiplier.

Background

With the continuous development of wireless communication technology, the working frequency of the current communication system has already moved forward to the radio frequency setting terahertz frequency band. Meanwhile, the requirements of lower power consumption, higher frequency, larger bandwidth, lower cost and the like are also put forward for the wireless communication system. For one of the core circuits of the transceiver module, the Frequency synthesizer (Frequency multiplier) can simply and directly increase the output signal Frequency of the Frequency synthesizer module. In addition, in the transmitter, when the local oscillator signal and the output signal of the power amplifier have similar frequencies, the output signal of the power amplifier may cause interference to the local oscillator signal, which affects the accuracy of the local oscillator signal. To avoid this, it is necessary to make the frequency of the local oscillator signal significantly different from the frequency of the signal transmitted by the power amplifier. The frequency multiplier can well realize the function. Therefore, the performance of the frequency multiplier directly affects the accuracy of the high-frequency communication system, and faces huge demands and challenges. When the frequency multiplier frequency N is continuously increased, the conversion efficiency is sharply reduced, and the working bandwidth is narrowed.

In order to solve the problem of low conversion gain in the frequency doubler, related researchers have proposed an improved frequency doubler circuit, whose schematic diagram is shown in fig. 1, wherein a differential pair of NMOS transistors generates a second harmonic signal at its output terminal. The capacitors C1 and C2 can transmit the fundamental harmonic signal of the drain terminal to the grid electrode, frequency multiplication is carried out again, and a second harmonic component is generated to improve conversion gain. The transmission lines TL1 and TL2 may extract filtering of the second harmonic. The inductor L will match the output of the circuit.

For the scheme of generating the cubic signal by utilizing the nonlinearity of the device, the circuit diagram is shown in fig. 2 as follows. The circuit structure for generating the cubic signal by using the method can be extremely simple. The third harmonic signal can be generated using only one NMOS transistor M1 operating in Class-a Class. When the MOS tube is completely conducted and a large signal is input, the output current of the drain end of the MOS tube is close to a square wave, the square wave contains rich odd harmonic current, a third harmonic component is extracted through the LC parallel resonant cavity and shaped into a sine wave signal.

Meanwhile, researchers have proposed a structure of the second/third frequency multiplier of fig. 3 as follows. Transistors M1, M2 form a push-push pair, generating a second harmonic signal. The transistors M3 and M4 form a single balanced mixer, and the second harmonic and fundamental wave signals generated by the transistors M1 and M2 are mixed to obtain a third harmonic signal. R1 and R2 are load resistors.

The technical route of the above-mentioned two/three frequency multiplier is as follows: firstly, a differential input signal is added to a push-push structure to generate a second harmonic signal, and a part of the second harmonic signal is directly extracted and output through a buffer; and directly injecting the other part of the second harmonic and the differential input signal into a single balanced mixer, filtering to obtain a third harmonic signal and outputting the third harmonic signal. The frequency doubler and the frequency tripler with the structure have the advantages of complex structure, low conversion gain and large circuit occupation area. The specific disadvantages are as follows:

(1) this configuration requires the injection of the second order signal and the differential input signal into a single balanced mixer when generating the third harmonic signal. For a single-balanced mixer, the conversion gain is low, which causes large loss, and since the push-push structure is an active structure, the mixer is also an active structure, which consumes extra power.

(2) In the structure, an LC parallel resonant cavity is required to be added at the position where the second harmonic wave is generated, and when the frequency is lower, the area occupied by the inductor is large, so that the area is wasted, and the circuit cost is greatly improved.

Disclosure of Invention

The invention aims to solve the defects in the prior art and provides a push-based two/three frequency multiplier circuit, which adopts an improved push-push circuit for neutralizing a capacitor, extracts different harmonic components for different modes and realizes the function of two/three frequency multiplication. The structure can effectively improve the output bandwidth of the single frequency multiplier, reduce the occupied area and save the cost.

The invention mainly aims to solve the problems of insufficient bandwidth, large occupied area of a chip and high power consumption of the traditional frequency multiplier. For a traditional frequency doubler, a push-push structure MOS tube pair is mainly adopted, the phase difference of odd harmonic components in the current of an output end of the MOS tube pair is 180 degrees, the odd harmonic components are differential signals and can be counteracted, only even harmonics exist, and then a required second harmonic signal is extracted through a resonant cavity of a drain electrode. This method is very common, but its operating bandwidth is difficult to make very large. For a traditional frequency tripler, a device can be adopted to directly generate and extract third harmonic components in a nonlinear way, so that the function of frequency tripled is realized. However, the conversion efficiency of this method is very low, and a large amount of power consumption is caused to achieve the function; but also has a poor Harmonic Rejection Ratio (HRR) and causes significant interference to subsequent circuits, such as mixers. Meanwhile, the bandwidth of the frequency tripling is difficult to be very large. The invention provides a circuit combining a frequency doubler and a frequency tripler to solve the bandwidth problem. And respectively carrying out odd modulus extraction and even modulus extraction on the drain end current of the push-push pair, and extracting a secondary signal and a tertiary signal. The structure can realize secondary frequency multiplication and tertiary frequency multiplication simultaneously, improves the bandwidth of output signals, and simultaneously combines a frequency doubling circuit and a frequency tripling circuit to reduce the area of a chip.

The invention adopts the following technical scheme:

disclosed is a push-push based frequency doubler and frequency tripler. The three-phase inverter comprises three parts, namely an NMOS transistor M1, an NMOS transistor M2, a neutralization capacitor Cp1, a push-push core consisting of a neutralization capacitor Cp2 and a transformer TR 2.

One end of a primary coil of the transformer TR1 is connected with a Port _ IN terminal, the other end is grounded, one end of a secondary coil of the transformer TR1 is connected with a gate of the NMOS transistor M1 and one end of the neutralization capacitor Cp1, the other end of the secondary coil of the transformer TR1 is connected with a gate of the NMOS transistor M2 and one end of the neutralization capacitor Cp 2. The center tap of the transformer TR1 is connected to Vb 1. The source of the NMOS transistor M1 is connected with the source of the NMOS transistor and is grounded, the drain of the NMOS transistor M1 is connected with the other end of the neutralization capacitor Cp2 and one end of the microwave transmission line TL1, the other end of the microwave transmission line TL1 is connected with one end of the primary winding of the transformer TR2, the drain of the NMOS transistor M5 is connected with the other end of the neutralization capacitor Cp1 and one end of the microwave transmission line TL2, and the other end of the microwave transmission line TL2 is connected with the other end of the primary winding of the transformer TR 2;

the center tap of the primary coil of the transformer TR2 is connected with one end of an inductor L1 and one end of a capacitor C2, the other end of the capacitor C2 is connected with a Vb2, the grid of an NMOS transistor M5, the source of the NMOS transistor M5 is grounded, the drain of the NMOS transistor M5 is connected with one end of the inductor L2 and one end of a capacitor C3, and the other end of the capacitor C3 is connected with a Port _ OUT 1.

One end of the secondary coil of the transformer TR2 is connected to the drain of the NMOS transistor M3, the gate of the NMOS transistor M4, one end of the capacitor C1, and one end of the secondary coil of the transformer TR 3. The other end of the secondary coil of the transformer TR2 is connected to the gate of the NMOS transistor M3, the drain of the NMOS transistor M4, the other end of the capacitor C1 and the other end of the transformer TR 3.

The source of NMOS transistor M3 is connected to the source of NMOS transistor M4 and to ground. The primary coil of the transformer TR3 has one end connected to Port _ OUT2 and the other end grounded.

The invention has the beneficial effects that:

the invention is based on a push-push structure, and adds a neutralization capacitor, thereby improving the conversion gain of the frequency multiplier. And simultaneously, distinguishing and extracting the secondary signal and the tertiary signal by using a transformer. And for the third-order signal, ILB is adopted for buffering and amplification, so that the fundamental wave suppression system of the third-order harmonic signal is improved. And secondary and tertiary signals are output simultaneously, so that the output bandwidth of the circuit is improved. This structure reduces the overall layout area and power consumption.

Drawings

FIG. 1 is a diagram of a modified push-push architecture frequency doubler;

FIG. 2 is a frequency tripler using the nonlinear characteristics of the device;

FIG. 3 is a schematic diagram of a two/three frequency multiplier based on self-mixing principle;

fig. 4 is a two/three frequency multiplier based on a push-push structure.

Detailed Description

To make the objects, technical solutions and advantages of the present invention clearer and more complete, the technical solutions of the present invention are described below clearly, and it is obvious that the described embodiments are some, not all, embodiments of the present invention. All other embodiments, which can be obtained by a person skilled in the art without inventive step based on the embodiments of the present invention, are within the scope of protection of the present invention.

As shown in fig. 4, a push-push based frequency doubler and its circuit are disclosed. The three-phase inverter comprises three parts, namely an NMOS transistor M1, an NMOS transistor M2, a neutralization capacitor Cp1, a push-push core consisting of a neutralization capacitor Cp2 and a transformer TR 2.

The invention can be briefly described as three parts, and the core part is a push-push consisting of an NMOS transistor M1, an NMOS transistor M2, a neutralization capacitor Cp1 and a neutralization capacitor Cp 2.

The core part generates a second harmonic signal and a third harmonic signal, and the second harmonic signal and the third harmonic signal can be extracted by a transformer TR 2.

The second part is a buffer for amplifying the common mode secondary signal extracted from the center tap of the primary winding of the transformer TR 2.

The third part is ILB that amplifies the differential third harmonic signal extracted from the secondary winding of transformer TR 2. In addition, a transformer TR1 performs input matching for the circuit; the transformer TR3 performs output matching on the ILB, and also provides a resonant cavity for the ILB, and the inductor L2 and the capacitor C3 perform output matching on the common source buffer.

This structure can output the secondary frequency signal and the tertiary frequency signal at the same time. Meanwhile, the extracted third harmonic signal is amplified by adopting an Injection-locked buffer (Injection-locked buffer), and the suppression of a fundamental wave signal can be improved. And directly accessing the secondary frequency signal into a common source buffer, amplifying and outputting. The structure has the advantages of higher output bandwidth, smaller area, lower power consumption and the like.

The improved technical characteristics of the invention are as follows:

(1) push-push pair sum transformer TR2 with added neutralization capacitor

The push-push pair with the neutralizing capacitor is added into the device as a core structure, the structure can generate required second harmonic signals and third harmonic signals, and the efficiency of the device is greatly improved compared with that of the traditional push-push pair. The transformer TR2 is a structure for extracting and distinguishing a second harmonic signal and a third harmonic signal, and a common mode second signal and a differential mode third signal are respectively extracted by using the characteristics of the transformer.

(2) Injection locking buffer

For the third harmonic signal, an injection locking buffer is adopted, and the third harmonic signal is improved, and simultaneously, the larger fundamental wave signal is subjected to filtering suppression through a resonant cavity, so that the fundamental wave suppression degree is improved.

(3) Common source stage buffer

And the common-source buffer amplifies the output second harmonic signal.

Finally, it should be noted that: the above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.

Claims

1. A push-push based frequency doubler is characterized by comprising an NMOS transistor M1, an NMOS transistor M2, a neutralization capacitor Cp1, a neutralization capacitor Cp2 and a transformer TR 2;

one end of a primary coil of the transformer TR1 is connected with a Port _ IN end, the other end of the primary coil is grounded, one end of a secondary coil of the transformer TR1 is connected with a grid of an NMOS transistor M1 and one end of a neutralization capacitor Cp1, the other end of the secondary coil of the transformer TR1 is connected with the grid of an NMOS transistor M2, one end of the neutralization capacitor Cp2 is connected, a center tap of the transformer TR1 is connected with a Vb1, a source of the NMOS transistor M1 is connected with a source of the NMOS transistor and grounded, a drain of the NMOS transistor M1 is connected with the other end of the neutralization capacitor Cp2 and one end of a microwave transmission line TL1, the other end of the microwave transmission line TL1 is connected with one end of a primary winding of the transformer TR2, the drain of the NMOS transistor M5 is connected with the other end of the neutralization capacitor Cp1 and one end of the microwave transmission line TL2, and the other end of the microwave transmission line 2 is connected with the other end of the primary coil of the transformer TR 2;

The center tap of the primary coil of the transformer TR2 is connected with one end of an inductor L1 and one end of a capacitor C2, the other end of the capacitor C2 is connected with a Vb2, the grid of an NMOS transistor M5, the source of the NMOS transistor M5 is grounded, the drain of the NMOS transistor M5 is connected with one end of the inductor L2 and one end of a capacitor C3, and the other end of the capacitor C3 is connected with a Port _ OUT 1;

one end of a secondary coil of the transformer TR2 is connected with the drain electrode of the NMOS transistor M3, the grid electrode of the NMOS transistor M4, one end of the capacitor C1 and one end of a secondary coil of the transformer TR 3; the other end of the secondary coil of the transformer TR2 is connected with the grid of the NMOS transistor M3, the drain of the NMOS transistor M4, the other end of the capacitor C1, the other end of the transformer TR3, the source of the NMOS transistor M3 is connected with the source of the NMOS transistor M4, the primary coil of the transformer TR3 is connected with the Port _ OUT2 in a terminating mode, and the other end of the primary coil of the transformer TR3 is grounded.