CN114743972A - Deposition method of polycrystalline silicon contact film - Google Patents
Deposition method of polycrystalline silicon contact film Download PDFInfo
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- CN114743972A CN114743972A CN202110020454.5A CN202110020454A CN114743972A CN 114743972 A CN114743972 A CN 114743972A CN 202110020454 A CN202110020454 A CN 202110020454A CN 114743972 A CN114743972 A CN 114743972A
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- deposition method
- polysilicon
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 title claims abstract description 48
- 238000000151 deposition Methods 0.000 title claims abstract description 39
- 229920005591 polysilicon Polymers 0.000 claims abstract description 33
- 239000004065 semiconductor Substances 0.000 claims abstract description 19
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims abstract description 18
- 238000000034 method Methods 0.000 claims abstract description 18
- 239000001257 hydrogen Substances 0.000 claims abstract description 17
- 229910052739 hydrogen Inorganic materials 0.000 claims abstract description 17
- 239000010408 film Substances 0.000 claims description 18
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 9
- 229910052710 silicon Inorganic materials 0.000 claims description 9
- 239000010703 silicon Substances 0.000 claims description 9
- 238000003860 storage Methods 0.000 claims description 9
- 239000010409 thin film Substances 0.000 claims description 7
- 229910052757 nitrogen Inorganic materials 0.000 claims description 5
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 4
- 239000007789 gas Substances 0.000 claims description 3
- 238000010926 purge Methods 0.000 claims description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical group [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 2
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical group [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 claims description 2
- PZPGRFITIJYNEJ-UHFFFAOYSA-N disilane Chemical compound [SiH3][SiH3] PZPGRFITIJYNEJ-UHFFFAOYSA-N 0.000 claims description 2
- 229910052698 phosphorus Inorganic materials 0.000 claims description 2
- 239000011574 phosphorus Substances 0.000 claims description 2
- 239000000758 substrate Substances 0.000 abstract description 14
- 239000012535 impurity Substances 0.000 abstract description 6
- 230000000694 effects Effects 0.000 abstract description 3
- 230000002411 adverse Effects 0.000 abstract description 2
- 230000008021 deposition Effects 0.000 description 15
- 238000004519 manufacturing process Methods 0.000 description 6
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 3
- 238000006243 chemical reaction Methods 0.000 description 3
- 238000004140 cleaning Methods 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 239000001301 oxygen Substances 0.000 description 3
- 229910052760 oxygen Inorganic materials 0.000 description 3
- 238000002360 preparation method Methods 0.000 description 3
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical group [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 2
- 229910021417 amorphous silicon Inorganic materials 0.000 description 2
- 238000000231 atomic layer deposition Methods 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 238000005137 deposition process Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000011737 fluorine Chemical group 0.000 description 2
- 229910052731 fluorine Inorganic materials 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910021645 metal ion Inorganic materials 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 125000004429 atom Chemical group 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000007664 blowing Methods 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 125000005842 heteroatom Chemical group 0.000 description 1
- 150000002431 hydrogen Chemical class 0.000 description 1
- 229910000040 hydrogen fluoride Inorganic materials 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 239000011261 inert gas Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 230000000116 mitigating effect Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02587—Structure
- H01L21/0259—Microstructure
- H01L21/02595—Microstructure polycrystalline
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/485—Bit line contacts
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Electrodes Of Semiconductors (AREA)
- Semiconductor Memories (AREA)
Abstract
The invention relates to a deposition method of a polycrystalline silicon contact film. A method for depositing a polysilicon contact film comprises the following steps: providing a semiconductor structure of which the polycrystalline silicon contact film is to be deposited; introducing hydrogen into the semiconductor structure for baking, wherein the baking temperature is 400-600 ℃, and the pressure is 0.1-10 torr; a polysilicon film is then deposited over the semiconductor structure. The method can efficiently remove the impurities of the oxide layer on the substrate, avoid the adverse effect of the impurities of the oxide layer on the resistance of the polycrystalline silicon contact film, realize good ohmic contact and improve the electrical property.
Description
Technical Field
The invention relates to the field of semiconductor production processes, in particular to a deposition method of a polycrystalline silicon contact film.
Background
In a manufacturing process of a DRAM (Dynamic Random Access Memory) device, a polysilicon (poly) is deposited to form contact films such as a Bit line contact (Bit line contact) conductive structure and a Storage node contact (Storage node contact) conductive structure. As integrated circuits shrink in size, the demand for contact resistance of polysilicon increases.
In the waiting time before the polysilicon is deposited in the furnace tube machine, the exposed part of the front layer polysilicon or the silicon substrate can form a natural oxidation layer due to oxidation, and the natural oxidation layer can influence the contact resistance and reduce the conductive capability. In the prior art, a natural oxide layer is removed by a wet cleaning method before polysilicon deposition, but the method needs to strictly control the waiting time from the wet cleaning to the polysilicon deposition, so that the control is difficult, and the contact resistance fluctuates greatly due to different waiting times; yet another way is to do nitrogen (N) at a waiting time2) The blowing reduces the oxygen concentration in the environment, thereby mitigating the formation of a native oxide layer, which has a low clearance rate, and this requires extended waiting times. It can be seen that the existing methods for removing oxides are inefficient and of unstable quality.
Therefore, the invention is especially provided.
Disclosure of Invention
The invention mainly aims to provide a deposition method of a polycrystalline silicon contact film, which can efficiently remove impurities of an oxide layer on a substrate, avoid the adverse effect of the impurities of the oxide layer on the resistance of the polycrystalline silicon contact film, realize good ohmic contact and improve the electrical property.
In order to achieve the above object, the present invention provides the following technical solutions.
A method for depositing a polysilicon contact film comprises the following steps:
providing a semiconductor structure of a polycrystalline silicon contact film to be deposited;
introducing hydrogen into the semiconductor structure for baking, wherein the baking temperature is 400-600 ℃, and the pressure is 0.1-10 torr;
a polysilicon film is then deposited over the semiconductor structure.
By utilizing the high-temperature baking of the semiconductor structure in the hydrogen atmosphere, chemical bonds of the oxide (such as silicon oxide) can be destroyed, so that heteroatoms such as oxygen, fluorine and the like are removed, and meanwhile, the silicon on the surface of the substrate is reduced, so that on one hand, the silicon loss of the substrate is avoided, the oxide is removed, and meanwhile, the polycrystalline silicon deposition process can be carried out without waiting time. It can be seen that the present invention has high oxide removal efficiency and high removal rate.
The deposition method can be used for depositing polysilicon in the DRAM bit line contact hole, or depositing polysilicon in the DRAM storage node contact groove, or depositing polysilicon on other interfaces which are easy to generate natural oxide.
Compared with the prior art, the invention achieves the following technical effects:
(1) the clearance rate of oxide is improved;
(2) the clearance rate of oxide is improved;
(3) the resistance of the polycrystalline silicon contact film is reduced, and the electrical characteristics of the device are improved;
(4) the method has wide application range and can be used for deposition on any interface which is easy to generate natural oxide.
Drawings
Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the invention.
FIG. 1 is a schematic diagram of the structure of the DRAM bit line contact according to the present invention
FIG. 2 is a schematic diagram of the mechanism of reaction of hydrogen with an oxide;
FIG. 3 is a flow chart of the preparation of a polysilicon contact film according to the present invention;
FIG. 4 is a flow chart of another process for forming a polysilicon contact film according to the present invention.
Detailed Description
Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood that the description is illustrative only and is not intended to limit the scope of the present disclosure. Moreover, in the following description, descriptions of well-known structures and techniques are omitted so as to not unnecessarily obscure the concepts of the present disclosure.
Various structural schematics according to embodiments of the present disclosure are shown in the figures. The figures are not drawn to scale, wherein certain details are exaggerated and some details may be omitted for clarity of presentation. The shapes of various regions, layers, and relative sizes and positional relationships therebetween shown in the drawings are merely exemplary, and deviations may occur in practice due to manufacturing tolerances or technical limitations, and a person skilled in the art may additionally design regions/layers having different shapes, sizes, relative positions, as actually required.
In the context of the present disclosure, when a layer/element is referred to as being "on" another layer/element, it can be directly on the other layer/element or intervening layers/elements may be present. In addition, if a layer/element is "on" another layer/element in one orientation, then that layer/element may be "under" the other layer/element when the orientation is reversed.
Taking the bit line contact hole of the DRAM as an example, as shown in fig. 1, polysilicon 102 needs to be deposited on a substrate 101 having the contact hole to form the bit line contact, as shown in fig. 1.
First, the manufacturing process of the bit line contact hole is performed.
A device isolation structure STI and a transistor may be formed on the semiconductor substrate 101, where the transistor includes an active region and a buried gate, and the active region is isolated by the isolation structure. The semiconductor substrate may be any substrate known to those skilled in the art for supporting components of a semiconductor integrated circuit, such as silicon-on-insulator (SOI), bulk silicon (bulk silicon), germanium, silicon germanium, gallium arsenide, or germanium-on-insulator (ge), etc. The method for forming the buried gate may include etching the substrate using a patterned photolithography method to form a buried gate trench; then forming a grid oxide layer; the partially filled metal layer then forms a word line. Next, an insulating layer is formed on the semiconductor substrate, and the insulating layer is etched by a patterning method until the active region is exposed, thereby forming a bit line contact hole in the insulating layer. Then, the substrate with the bit line contact hole is cleaned.
The semiconductor structure with the bit line contact holes formed therein may then be placed in a deposition furnace (typically a tube deposition furnace) into which hydrogen H is introduced2The temperature is raised to 400-600 ℃, the pressure is controlled within the range of 0.1-10 torr, preferably within the range of 0.5-10 torr, and the surface to be deposited is baked under the condition. During baking, hydrogen combines with atoms of oxygen O, fluorine F, etc. in the oxide, thereby reducing oxidized silicon, and oxyhydrogen, a product of hydrogen fluoride, etc. escape from the apparatus. In order to ensure the sufficient reaction of the hydrogen and the oxide, the flow rate of the hydrogen and the introduction time period need to be controlled, and the flow rate is usually kept above 10L. The reaction process of hydrogen with the oxide is shown in figure 2. In addition, impurities such as metal ions may exist in natural oxides on the interface, and before the hydrogen is introduced for baking, HCl gas is introduced into the deposition furnace for baking to remove the metal ions and improve the resistance. The conditions for baking by introducing HCl gas can be as follows: the temperature is 400-600 ℃, and the pressure is 0.1-10 torr.
The substrate may be purged by conventional means, such as with an inert gas such as nitrogen, to physically remove impurities prior to removing the oxide film.
The polysilicon deposition stage can be performed after the oxide is removed by any of the above-mentioned methods. The material of the polycrystalline silicon contact film can be amorphous silicon (amorphous silicon) or crystalline silicon, and the mode of depositing the polycrystalline silicon contact film can be a low-pressure chemical vapor deposition (LPCVD) mode or an Atomic Layer Deposition (ALD) mode or a composite mode of atomic layer Seed (Seed) deposition and LPCVD mode or a Plasma Enhanced Chemical Vapor Deposition (PECVD) mode. The polysilicon contact film may be an in-situ phosphorus (P) -doped polysilicon and the silicon source may be monosilane or disilane, or other typical silicon sources.
After the polysilicon deposition is completed, the bit line body may be formed continuously, for example, a stack of a barrier layer, a metal layer, and an insulating cap layer may be deposited, the stack and the contact portion may be etched, thereby forming a bit line body structure, and finally, sidewalls may be formed on both sides of the bit line body structure.
After the bit lines are formed, a process method in which the embodiments of the present application are applied to the storage node contacts is described below.
After the bit line is manufactured, the isolation layer above the semiconductor substrate is etched by taking the bit line main body and the side wall as masks until the active region is exposed, and a groove is formed. A dielectric layer may be formed in the trench and then photolithography may be performed to form a storage node contact hole exposing the active region. The structure is then fed into a deposition furnace and processed using the same cleaning method as described above for the bit line contact holes, followed by deposition of polysilicon to form storage node contacts.
Fabrication of the contact pads and capacitors may then be performed to complete the fabrication of the DRAM cell.
Based on the deposition scheme of the polycrystalline silicon, at least the following two embodiments are provided:
example 1
As shown in fig. 3, after a structure (for example, the structure with the bit line contact hole or the storage node contact hole formed therein) of the polysilicon thin film to be deposited is sent into a deposition furnace, nitrogen purging, hydrogen baking, and polysilicon deposition are sequentially performed to complete the preparation of the polysilicon contact thin film, wherein the hydrogen baking conditions are as follows: the temperature is 400-600 ℃, and the pressure is 0.1-10 torr.
Example 2
As shown in fig. 4, after the structure (for example, the structure with the bit line contact hole or the storage node contact hole) of the polysilicon thin film to be deposited is sent into the deposition furnace, the preparation of the polysilicon contact thin film is completed through the nitrogen purging, the HCl baking, the hydrogen baking, and the polysilicon deposition process in sequence. Wherein the baking conditions of HCl are as follows: the temperature is 400-600 ℃, and the pressure is 0.1-10 torr; the hydrogen baking conditions were: the temperature is 400-600 ℃, and the pressure is 0.1-10 torr.
The embodiments of the present disclosure are described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the disclosure is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be devised by those skilled in the art without departing from the scope of the present disclosure, and such alternatives and modifications are intended to be within the scope of the present disclosure.
Claims (10)
1. A method for depositing a polysilicon contact film, comprising:
providing a semiconductor structure of a polycrystalline silicon contact film to be deposited;
introducing hydrogen into the semiconductor structure for baking, wherein the baking temperature is 400-600 ℃, and the pressure is 0.1-10 torr;
a polysilicon film is then deposited over the semiconductor structure.
2. The deposition method according to claim 1, wherein a flow rate of hydrogen at the baking is 10L or more.
3. The deposition method according to claim 1, further comprising introducing HCl gas for baking before introducing the hydrogen gas, wherein the baking temperature is 400-600 ℃ and the pressure is 0.1-10 torr.
4. The deposition method according to claim 1, wherein the baking pressure for introducing the hydrogen gas is 0.5 to 10 torr.
5. The deposition method of claim 1, wherein the method of depositing the polysilicon thin film is LPCVD, ALD, or PEALD.
6. The deposition method according to any one of claims 1 to 5, wherein the polysilicon thin film is phosphorus doped polysilicon.
7. The deposition method according to claim 1, wherein the silicon source for depositing the polysilicon thin film is monosilane or disilane.
8. The deposition method of claim 1, wherein the semiconductor structure is a DRAM bit line contact hole.
9. The deposition method of claim 1, wherein the semiconductor structure is a DRAM storage node contact hole.
10. The deposition method of claim 1, wherein a nitrogen purge is also introduced prior to the introduction of hydrogen.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110020454.5A CN114743972A (en) | 2021-01-07 | 2021-01-07 | Deposition method of polycrystalline silicon contact film |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110020454.5A CN114743972A (en) | 2021-01-07 | 2021-01-07 | Deposition method of polycrystalline silicon contact film |
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| Publication Number | Publication Date |
|---|---|
| CN114743972A true CN114743972A (en) | 2022-07-12 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110020454.5A Pending CN114743972A (en) | 2021-01-07 | 2021-01-07 | Deposition method of polycrystalline silicon contact film |
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| CN (1) | CN114743972A (en) |
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2021
- 2021-01-07 CN CN202110020454.5A patent/CN114743972A/en active Pending
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