CN114725175A - Display panel, spliced screen and display device - Google Patents
Display panel, spliced screen and display device Download PDFInfo
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- CN114725175A CN114725175A CN202210355492.0A CN202210355492A CN114725175A CN 114725175 A CN114725175 A CN 114725175A CN 202210355492 A CN202210355492 A CN 202210355492A CN 114725175 A CN114725175 A CN 114725175A
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/131—Interconnections, e.g. wiring lines or terminals
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
- G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
- G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
- G09F9/302—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements characterised by the form or geometrical disposition of the individual elements
- G09F9/3026—Video wall, i.e. stackable semiconductor matrix display modules
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/18—Tiled displays
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Abstract
The utility model provides a display panel, concatenation screen and display device belongs to and shows technical field, and it can solve the great problem of frame of binding district one side among the current display panel. The display panel of the present disclosure has a display area and a non-display area adjacent to the display area, the non-display area including: a binding region and a non-binding region; the display panel includes: the display device comprises a substrate, a first electrode layer and a power signal line, wherein the first electrode layer is positioned on the substrate and extends from a display area to at least one non-binding area; the first electrode layer and the power signal line are electrically connected through the lap via at least one unbonded area.
Description
Technical Field
The disclosure belongs to the technical field of display, and particularly relates to a display panel, a spliced screen and a display device.
Background
An Organic Light-Emitting Diode (OLED) is a Light-Emitting device using an Organic solid semiconductor as a Light-Emitting material, and has a wide application prospect because of its advantages of simple preparation process, low cost, low power consumption, high luminance, wide working temperature application range, and the like. As the demand for oversized displays increases, for example: an OLED display panel. The smaller size of the OLED display panel has not been able to meet the user's demand, thus increasing the size of the display screen, for example: the spliced screen product is produced at the same time.
The OLED display panel design generally requires that the smaller the frame of a single display panel, the better, so as to improve the overall display effect. For example: the requirements for tiled screens also dictate that the smaller the bezel of an individual display panel, the better. However, the OLED display panel needs to be connected to a bonding area side of the driver chip, and generally needs to include a frame of the fan-out area, a frame of the high-level power signal line, a frame of the low-level power signal line, and a frame occupied by the package.
Disclosure of Invention
The present disclosure is directed to at least one of the technical problems in the prior art, and provides a display panel, a tiled display and a display device.
In a first aspect, an embodiment of the present disclosure provides a display panel, where the display panel has a display area and a non-display area adjacent to the display area, and the non-display area includes: a binding region and a non-binding region;
the display panel includes: the display device comprises a substrate, a first electrode layer and a power signal line, wherein the first electrode layer is positioned on the substrate and extends from the display area to at least one unbound area, and the power signal line is positioned on the substrate and is arranged in at least one unbound area;
the first electrode layer and the power signal line are electrically connected by a lap via at least one of the unbonded regions.
Optionally, the unbound region includes: a first unbound region, a second unbound region, and a third unbound region; the first non-binding area is arranged on one side of the display area and is adjacent to the binding area; the second unbound area is arranged on one side of the display area and is opposite to the first unbound area; the third non-binding area is arranged on one side of the display area and is arranged opposite to the binding area;
the lap via is disposed at least one side of the first unbound region, the second unbound region, and the third unbound region.
Optionally, a distance from the first electrode layer to an edge of the display panel corresponding to the first non-binding region is smaller than a distance from the first electrode layer to an edge of the display panel corresponding to the third non-binding region;
and/or the distance from the first electrode layer to the edge of the display panel corresponding to the second unbound region is less than the distance from the first electrode layer to the edge of the display panel corresponding to the third unbound region.
Optionally, a distance from the overlapping via hole of the first non-binding region to the edge of the corresponding display panel is smaller than a distance from the overlapping via hole of the third non-binding region to the edge of the corresponding display panel;
and/or the distance from the overlapping via hole of the second non-binding region to the edge of the corresponding display panel is less than the distance from the overlapping via hole of the third non-binding region to the edge of the corresponding display panel.
Optionally, the display panel has a folding axis parallel to the display panel edge corresponding to the third unbound region;
the distribution density of the overlapping vias at a position near the folding axis is less than the distribution density of the overlapping vias at a position away from the folding axis.
Optionally, the display panel further comprises: the grid driving circuit is positioned on the substrate and is arranged in the display area;
the distance from the edge of the first electrode layer to the gate driving circuit is greater than the distance from the edge of the first electrode layer to the display area.
Optionally, in at least one of the non-binding regions, a distance from the landing via to the gate driving circuit is greater than a distance from the landing via to the display region.
Optionally, the display panel further comprises: the driving circuit layer is positioned between the substrate and the first electrode layer and is arranged in the display area, and the scanning lines and the data lines are arranged in a crossed manner; the driving circuit layer includes: a plurality of thin film transistors;
the scanning line is electrically connected with the grid electrodes of partial thin film transistors in the plurality of thin film transistors;
the data line is electrically connected to the sources of some of the plurality of thin film transistors.
Optionally, the display panel further comprises: a first conductive layer and a second conductive layer;
the first conductive layer includes: the scanning line and the grid electrode of the thin film transistor;
the second conductive layer includes: the data line, the power signal line, and the source and drain electrodes of the thin film transistor.
Optionally, the display panel further comprises: the first bonding pad and the second bonding pad are positioned on the substrate and are arranged in the binding region;
the data line extends from the display area to the binding area and is electrically connected with the first bonding pad;
the power signal line extends from the unbound region to the bound region and is electrically connected to the second pad.
Optionally, the second conductive layer further comprises: the first pad and the second pad.
Optionally, the display panel further comprises: a chip on film; the chip on film includes: the driving circuit comprises a base film and a driving chip positioned on the base film;
the driving chip is electrically connected with the first bonding pad and the second bonding pad.
In a second aspect, embodiments of the present disclosure provide a tiled screen including a plurality of display panels as provided above.
Optionally, in two adjacent display panels in the tiled screen, the distribution density of the overlapping via holes in the non-binding region corresponding to the tiled position is less than the distribution density of the overlapping via holes in the non-binding region corresponding to another position.
In a third aspect, embodiments of the present disclosure provide a display device including a tiled screen as provided above.
Drawings
FIG. 1 is a schematic diagram of an exemplary display panel;
FIG. 2 is a schematic cross-sectional view of the display panel shown in FIG. 1 along the direction A-A';
fig. 3 is a schematic structural diagram of a display panel according to an embodiment of the disclosure;
fig. 4 is a schematic cross-sectional view of the display panel shown in fig. 3 along the direction B-B'.
Detailed Description
For a better understanding of the technical aspects of the present disclosure, reference is made to the following detailed description taken in conjunction with the accompanying drawings.
Unless defined otherwise, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. The use of "first," "second," and the like in this disclosure is not intended to indicate any order, quantity, or importance, but rather is used to distinguish one element from another. Also, the use of the terms "a," "an," or "the" and similar referents do not denote a limitation of quantity, but rather denote the presence of at least one. The word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", and the like are used merely to indicate relative positional relationships, and when the absolute position of the object being described is changed, the relative positional relationships may also be changed accordingly.
Fig. 1 is a schematic structural diagram of an exemplary display panel, as shown in fig. 1, the display panel has a display area 10 and a non-display area 20 surrounding the display area 10, the non-display area 20 includes: a bonding area 201 disposed at one side of the display area 10. Fig. 2 is a schematic cross-sectional structure view of the display panel shown in fig. 1 along a direction a-a', and as shown in fig. 2, the display panel includes: a substrate 101, a first electrode layer 102 located on the substrate 101 and extending from the display region 10 to the bonding region 201, and a power signal line 103 located on the substrate 101 and disposed in the bonding region 201; the first electrode layer 102 and the power signal line 103 are electrically connected through the lap via 104 at the bonding region 201.
It should be noted that the bonding area 201 may be disposed at the lower side of the display area 10, and the power signal line 103 may specifically be a low-level power signal line VSS, which may provide a low-level signal for a cathode of the light emitting device to form a current loop in cooperation with a high-level power signal, so that the light emitting device emits light, thereby implementing a display function. Accordingly, the first electrode layer 102 may be specifically a cathode layer, of course, the type of the power signal line 103 corresponds to the type of the first electrode layer 102, and the two may also be other types of electrode layers and power lines, which are not listed here. The cathode of each light emitting device in the display panel may be provided over the entire surface thereof with the first electrode layer 102 formed in a planar shape. Generally, the first electrode layer 102 and the power signal line 104 are disposed in different film layers, at least one insulating layer structure (not shown) such as a planarization layer, a pixel defining layer, etc. is disposed therebetween, the landing via 104 is formed in the insulating layer structure in the bonding region 201, and the first electrode layer 102 and the power signal line 103 are electrically connected through the landing via 104.
Alternatively, the low-level power signal line VSS is generally disposed in the bonding region 201 on the lower side of the display region 10, which increases the width of the frame on one side of the bonding region 201 and affects the display effect. Meanwhile, the routing wire is required to be routed by bypassing the lap joint via hole 104 when the wiring wire is fanned out in the binding area 201, the routing mode is complex, and the process difficulty is increased.
In order to solve at least one of the above technical problems, embodiments of the present disclosure provide a display panel, a tiled display and a display device, which will be described in detail with reference to the accompanying drawings and specific embodiments.
In a first aspect, an embodiment of the present disclosure provides a display panel, and fig. 3 is a schematic structural diagram of a display panel provided in an embodiment of the present disclosure, as shown in fig. 3, the display panel has a display area 10 and a non-display area 20 adjacent to the display area 10, for example: a non-display area 20 surrounding the display area 10; the non-display area 20 includes: a bound region 201 and an unbound region 202; the bound region 201 and the unbound region 202 are respectively disposed on different sides of the display region 10. Fig. 4 is a schematic cross-sectional structure view of the display panel shown in fig. 3 along a direction B-B', and as shown in fig. 4, the display panel includes: a substrate 101, a first electrode layer 102 located on the substrate 101 and extending from the display region 10 to at least one non-binding region 202, and a power signal line 103 located on the substrate 101 and disposed in the at least one non-binding region 202; the first electrode layer 102 and the power signal line 103 are electrically connected in at least one unbonded area 202 by the lap via 104.
In the display panel provided by the embodiment of the disclosure, the bonding region 201 may be disposed at a lower side of the display region 10, the non-bonding region 202 may be disposed at a left side, a right side and/or an upper side of the display region 10, and the lap joint hole 104 electrically connected between the first electrode layer 102 and the power signal line 103 is disposed in the non-bonding region 202, so that the lap joint hole 104 may only occupy a package frame where a blocking structure (not shown in the figure) of the display panel is located, and a frame at one side of the non-bonding region 202 in the display panel is not increased. Meanwhile, the binding region 201 and the non-binding region 202 where the overlapping via hole 104 is located are respectively disposed at different sides of the display region 10, and the overlapping via hole 104 does not occupy a frame at one side of the binding region 201, so that the frame at one side of the binding region 201 of the display panel can be reduced, and the display effect of the display panel can be improved. On the other hand, since the lap via 104 is disposed in the non-binding region 202, it does not affect the routing manner of the fan-out wires in the binding region 201 or reduces the routing manner of the fan-out wires in the binding region 201, so that the complexity of routing in the binding region 201 can be reduced to save the manufacturing cost.
In some embodiments, the size and distribution density of the landing vias 104 may gradually increase along a direction away from the bonding region 201. The larger the size and the arrangement distribution density of the lap via holes 104 are, the larger the contact area between the first electrode layer 102 and the power signal line 103 is, and thus the smaller the contact resistance between the first electrode layer 102 and the power signal line 103 is, in the embodiment of the present disclosure, the size and the arrangement density of the lap via holes 104 are gradually increased along the direction away from the binding region 201, so that the effective connection between the first electrode layer 102 and the power signal line 103 can be ensured, and the contact resistance between the first electrode layer 102 and the power signal line 103 is reduced, thereby ensuring the stability of the power signal provided by the power signal line 103, and further ensuring the display effect of the display panel.
In some embodiments, as shown in fig. 3 and 4, the unbundling zone 202 includes: a first unbundled region 2021, a second unbundled region 2022, and a third unbundled region 2023; the first unbounded area 2021 is disposed on one side of the display area 201 and is disposed adjacent to the bound area 201; the second unbounded region 2022 is disposed at one side of the display region 201 and is opposite to the first unbounded region 2021; the third unbounded region 2023 is disposed on one side of the display region 201 and is disposed opposite to the bound region 201; the lap via 104 is disposed at least one side of the first, second, and third unbounded regions 2021, 2022, and 2023.
The first unbundling region 2021 may be disposed at the left side of the display region 10, the via hole 104 for electrical connection between the first electrode layer 102 and the power signal line 103 is disposed in the first unbundling region 2021, and the display panel may display in a single-side driving manner. Since the lap joint hole 104 electrically connected between the first electrode layer 102 and the power signal line 103 is disposed in the first non-bonding region 2021, the lap joint hole 104 may only occupy a package frame where a blocking structure (not shown) of the display panel is located, without increasing a frame on one side of the first non-bonding region 2021 in the display panel. Meanwhile, the first non-binding region 2021 where the overlapping via hole 104 is located is disposed on the left side of the display region 10, the binding region 201 is disposed on the lower side of the display region 10, and the overlapping via hole 104 does not occupy a frame on one side of the binding region 201, so that the frame on one side of the binding region 201 of the display panel can be reduced, and the display effect of the display panel can be improved. On the other hand, since the lap via 104 is disposed in the first non-binding region 2021, it does not affect the routing manner of the fan-out routing in the binding region 201, so that the complexity of routing in the binding region 201 can be reduced, and the manufacturing cost can be saved. It is understood that the first unbounded area 2021 may also be disposed on the right side or the upper side of the display area 10, and the implementation principle thereof is the same as that described above and is not described herein again.
The second unbounded region 2022 may be disposed on the right side of the display region 10, and the lap joint hole 104 electrically connected between the first electrode layer 102 and the power signal line 103 is disposed in the first unbounded region 2021 and the second unbounded region 2022, so that the display panel may display in a bilateral driving manner, and at the same time, the lap joint area between the first electrode layer 102 and the power signal line 103 may be increased to ensure the transmission effect of the power signal. Since the lap joint holes 104 electrically connected between the first electrode layer 102 and the power signal lines 103 are disposed in the first unbound area 2021 and the second unbound area 2022, the lap joint holes 104 may only occupy a package frame where a blocking structure (not shown) of the display panel is located, and frames on two sides of the first unbound area 2021 and the second unbound area 2022 in the display panel are not increased. Meanwhile, the first non-binding region 2021 where the overlapping via hole 104 is located is arranged on the left side of the display region 10, the second non-binding region 2022 where the overlapping via hole 104 is located is arranged on the right side of the display region 10, the binding region 201 is arranged on the lower side of the display region 10, and the overlapping via hole 104 does not occupy a frame on one side of the binding region 201, so that the frame on one side of the binding region 201 of the display panel can be reduced, and the display effect of the display panel can be improved. On the other hand, since the lap via 104 is disposed in the first non-binding region 2021 and the second non-binding region 2022, it does not affect the routing manner of the fan-out routing in the binding region 201, so that the complexity of routing in the binding region 201 can be reduced, and the manufacturing cost can be saved.
The third unbounded region 2023 may be disposed on the upper side of the display region 10, and the lap joint hole 104 electrically connected between the first electrode layer 102 and the power signal line 103 is disposed in the first unbounded region 2021, the second unbounded region 2022, and the third unbounded region 2023, so that the display panel may display in a dual-side driving manner, and simultaneously, the lap joint area between the first electrode layer 102 and the power signal line 103 may be further increased to ensure the transmission effect of the power signal. Since the lap joint holes 104 electrically connected between the first electrode layer 102 and the power signal lines 103 are disposed in the first unbounded region 2021, the second unbounded region 2022, and the third unbounded region 2023, the lap joint holes 104 may only occupy a package frame where a blocking structure (not shown) of the display panel is located, without increasing frames of the first unbounded region 2021, the second unbounded region 2022, and the third unbounded region 2023 of the display panel. Meanwhile, the first non-binding region 2021 where the overlapping via hole 104 is located is disposed on the left side of the display region 10, the second non-binding region 2022 where the overlapping via hole 104 is located is disposed on the right side of the display region 10, the third non-binding region 2023 where the overlapping via hole 104 is located is disposed on the upper side of the display region 10, the binding region 201 is disposed on the lower side of the display region 10, and the overlapping via hole 104 does not need to occupy a frame on one side of the binding region 201, so that the frame on one side of the binding region 201 of the display panel can be reduced, and the display effect of the display panel can be improved. On the other hand, since the lap via 104 is disposed in the first unbonded area 2021, the second unbonded area 2022, and the third unbonded area 2023, it does not affect the routing manner of the fan-out routing in the bonded area 201, so that the complexity of routing in the bonded area 201 can be reduced, and the manufacturing cost can be saved.
Optionally, as shown in fig. 3, since the lap via 104 may be disposed at least one side of the first unbonded area 2021, the second unbonded area 2022, and the third unbonded area 2023, the first electrode layer 102 may extend toward the unbonded area along the gate line 106, and the coverage of the first electrode layer 102 in the bonded area 201 may be reduced (usually, the first electrode layer 102 is electrically connected to the power signal line 103 in the bonded area 201, so that the coverage of the first electrode layer 102 in the bonded area 201 is larger or the routing of the data line 107 is longer), and thus, the distance from the first electrode layer 102 to the corresponding display panel edge of the unbonded area is smaller than the distance from the first electrode layer 102 to the display panel edge of the bonded area.
Optionally, in order to facilitate left and right side splicing or left and right side narrower frames, a distance from the first electrode layer 102 to the corresponding display panel edge of the first unbound region 2021 and the second unbound region 2022 is smaller than a distance from the first electrode layer 102 to the display panel edge of the third unbound region 2023; and/or the distance from the landing via 104 of the first unbound region 2021 and the second unbound region 2022 to the corresponding edge of the display panel is less than the distance from the landing via 104 of the third unbound region 2023 to the edge of the display panel of the third unbound region 2023. For example, the distance from the first electrode layer 102 to the edge of the display panel corresponding to the first unbundling region 2021 is smaller than the distance from the first electrode layer 102 to the edge of the display panel corresponding to the third unbundling region 2023; and/or the distance from the first electrode layer 102 to the edge of the second unbound region 2023 corresponding to the display panel is less than the distance from the first electrode layer 102 to the edge of the third unbound region 2023 corresponding to the display panel.
Optionally, when the display panel is a folding screen, for example, folded in the direction of B-B', the distribution density of the overlapping vias 104 near the folding axis (i.e., at least one side of the folding axis) is less than that of the positions far away from the folding axis, so as to avoid the influence on the contact of the overlapping vias 104 during folding and prevent disconnection; in particular, the lap vias 104 are not disposed in the areas of the first unbounded area 2021 and the second unbounded area 2022 corresponding to the folding axis.
Alternatively, as shown in fig. 3 and 4, the display panel may adopt a Gate driving circuit 105 Integrated in a Gate Driver Integrated Active Array (GIA) technology to avoid occupying a display frame, and only the frame occupied by packaging needs to be reserved. Therefore, at least one side of the first unbonded area 2021, the second unbonded area 2022 and the third unbonded area 2023, the distance from the edge of the first electrode layer 102 (which means the outer side close to the display panel) to the gate driving circuit 105 is greater than the distance from the edge of the first electrode layer 102 to the display area; and/or, on at least one side of the first non-binding region 2021 and the second non-binding region 2022, a distance from the landing via 104 of the first non-binding region 2021 and the second non-binding region 2022 to the gate driving circuit 105 is greater than a distance from the landing via 104 to the display region. For example: the distance from the landing via 104 of the first non-binding region 2021 to the gate driving circuit 105 is greater than the distance from the landing via 104 to the display region.
In some embodiments, as shown in fig. 3 and 4, the display panel further includes: a driving circuit layer disposed between the substrate 101 and the first electrode layer 102, and a scan line 106 and a data line 107 disposed in a crossing manner; the driving circuit layer includes: a plurality of thin film transistors 108; the scan line 106 is electrically connected to the gate electrode 1081 of some of the plurality of thin film transistors 108; the data line 107 is electrically connected to the sources 1082 of some of the plurality of thin film transistors 108.
The driving circuit layer may be provided with a pixel driving circuit, and the pixel driving circuit may have a commonly used circuit structure such as 7T1C (7 thin film transistors and 1 storage capacitor), 8T1C, 9T1C, and the like, wherein the common circuit structure at least includes a data writing transistor, a driving transistor, and the like, and specific structures will not be described again. The thin film transistor 108 includes: a gate electrode 1081, a gate insulating layer, an active layer, an interlayer insulating layer, a source electrode 1082 and a drain electrode 1083 sequentially on the substrate 101. The scan line 106 may control the data writing transistor to be turned on, so that a data signal provided by the data line 107 is input to the light emitting device through the driving transistor to drive the light emitting device to emit light, thereby implementing a display function.
In some embodiments, as shown in fig. 4, the display panel further includes: a first conductive layer 109 and a second conductive layer 110; the first conductive layer 109 includes: the scan line 106 and the gate 1081 of the thin film transistor 108; the second conductive layer 110 includes: the data line 107, the power supply signal line 103, and the source electrode 1082 and the drain electrode 1083 of the thin film transistor 108.
The scan line 106 and the gate 1081 of the tft 108 can be made of the same material and by the same process, so as to save the manufacturing cost. Similarly, the data line 107, the power signal line 103, and the source electrode 1082 and the drain electrode 1083 of the thin film transistor 108 may be formed by the same process using the same material, so as to save the manufacturing cost.
In some embodiments, as shown in fig. 3, the display panel further includes: a first pad 2011 and a second pad 2012 disposed on the substrate 101 and disposed in the bonding region 201; the data line 107 extends from the display area 10 to the bonding area 201 and is electrically connected with the first pad 2011; the power signal line 103 extends from the unbonded area 202 to the bonded area 201 to be electrically connected to the second pad 2022.
The first pad 2011 may be connected to the data line 107, and may be bond-connected to a driving chip (not shown) through the first pad 2011, so that the driving chip provides a data signal to the data line 107. The second pad 2012 can be connected to the power signal line 103, and can be bonded to a driver chip (not shown) through the second pad 2012, so that the driver chip provides the power signal line 103 with a power signal.
In some embodiments, the second conductive layer 110 further comprises: a first pad 2011 and a second pad 2012.
The first pad 2011, the second pad 2012, the data line 107, the power signal line 103, and the source 1082 and the drain 1083 of the thin film transistor 108 may also be made of the same material by the same process, so as to save the manufacturing cost.
In some embodiments, the display panel further comprises: a second electrode layer 111 and an organic light emitting layer 112 on the side of the driving circuit layer away from the substrate 101; the second electrode layer 111 is disposed opposite to the first electrode layer 102; the organic light emitting layer 112 is located between the second electrode layer 111 and the first electrode layer 102.
An electric field may be formed between the second electrode layer 111 and the first electrode layer 102, and the organic light emitting layer 112 may emit light under the driving of the electric field to realize a display function.
In some embodiments, the display panel further comprises: a flip-chip film (not shown); the chip on film includes: a base film and a driving chip (not shown) on the base film; the driving chip is electrically connected to the first pad 2011 and the second pad 2022.
The driving chip may supply a data signal to the data line 107 through the first pad 2011, and simultaneously supply a power signal to the power signal line 102 through the second pad 2022, so that the organic light emitting layer 112 in the light emitting device emits light, thereby implementing a display function.
In a second aspect, embodiments of the present disclosure provide a tiled screen including a plurality of display panels as provided in any of the above embodiments.
In the display panel of the tiled display screen provided by the embodiment of the disclosure, the bonding region 201 can be disposed at the lower side of the display region 10, the non-bonding region 202 can be disposed at the left side, the right side and/or the upper side of the display region 10, the lap joint hole 104 electrically connected between the first electrode layer 102 and the power signal line 103 is disposed in the non-bonding region 202, and since there are fewer signal lines and electrical devices in the non-bonding region 202, the lap joint hole 104 can be disposed in a frame occupied by the package, so that the frame at one side of the non-bonding region 202 in the display panel is not increased. Meanwhile, the non-binding area 202 and the binding area 201 where the overlapping via hole 104 is located are respectively arranged on different sides of the display area 10, and the overlapping via hole 104 does not need to occupy a frame on one side of the binding area 201, so that the frame on one side of the binding area 201 of the display panel can be reduced, a splicing gap between the display panels in the spliced screen is easily reduced, and the display effect of the spliced screen can be improved.
Optionally, since the landing via 104 may be disposed at least one side of the first unbundling region 2021, the second unbundling region 2022, and the third unbundling region 2023; when the spliced screen exists, the distribution density of the lap joint through holes 104 corresponding to the non-binding areas of the spliced screen is smaller than that of the lap joint through holes 104 of other non-binding areas, so that the damage to the through holes possibly caused in the assembling process of the spliced screen is favorably prevented. For example: the first unbounded area 2021 is assembled to form a tiled screen, and the distribution density of the overlapping vias 104 on at least one side of the second unbounded area 2022 and the third unbounded area 2023 is greater than that of the overlapping vias 104 in the first unbounded area 2021.
In a third aspect, an embodiment of the present disclosure provides a display device, where the display device includes the tiled screen provided in any of the above embodiments, and the display device may be applied to a meeting room, a movie theater, a multifunctional room, and other scenes that need large screen display, and its implementation principle is similar to that of the tiled screen provided in the above embodiments, and is not described herein again.
It is to be understood that the above embodiments are merely exemplary embodiments that are employed to illustrate the principles of the present disclosure, and that the present disclosure is not limited thereto. It will be apparent to those skilled in the art that various changes and modifications can be made therein without departing from the spirit and scope of the disclosure, and these are to be considered as the scope of the disclosure.
Claims (15)
1. A display panel, the display panel having a display area and a non-display area adjacent to the display area, the non-display area comprising: a binding region and a non-binding region;
the display panel includes: the display device comprises a substrate, a first electrode layer and a power signal line, wherein the first electrode layer is positioned on the substrate and extends from the display area to at least one non-binding area;
the first electrode layer and the power signal line are electrically connected by a lap via at least one of the unbonded regions.
2. The display panel of claim 1, wherein the unbound region comprises: a first unbound region, a second unbound region, and a third unbound region; the first non-binding area is arranged on one side of the display area and is adjacent to the binding area; the second unbound area is arranged on one side of the display area and is opposite to the first unbound area; the third non-binding area is arranged on one side of the display area and is arranged opposite to the binding area;
the lap via is disposed on at least one side of the first unbonded area, the second unbonded area, and the third unbonded area.
3. The display panel according to claim 2, wherein the distance from the first electrode layer to the edge of the display panel corresponding to the first unbound region is less than the distance from the first electrode layer to the edge of the display panel corresponding to the third unbound region;
and/or the distance from the first electrode layer to the edge of the display panel corresponding to the second unbound region is less than the distance from the first electrode layer to the edge of the display panel corresponding to the third unbound region.
4. The display panel according to claim 2, wherein the distance from the landing via of the first non-binding region to the edge of the corresponding display panel is less than the distance from the landing via of the third non-binding region to the edge of the corresponding display panel;
and/or the distance from the overlapping via hole of the second non-binding region to the edge of the corresponding display panel is less than the distance from the overlapping via hole of the third non-binding region to the edge of the corresponding display panel.
5. The display panel of claim 2, wherein the display panel has a folding axis parallel to an edge of the display panel corresponding to the third unbound region;
the distribution density of the landing vias at locations near the folding axis is less than the distribution density of the landing vias at locations away from the folding axis.
6. The display panel according to claim 2, characterized in that the display panel further comprises: the grid driving circuit is positioned on the substrate and is arranged in the display area;
the distance from the edge of the first electrode layer to the gate driving circuit is greater than the distance from the edge of the first electrode layer to the display region.
7. The display panel according to claim 6, wherein in at least one of the non-binding regions, a distance from the landing via to the gate driving circuit is greater than a distance from the landing via to the display region.
8. The display panel according to claim 1, characterized in that the display panel further comprises: the driving circuit layer is positioned between the substrate and the first electrode layer and is arranged in the display area, and the scanning lines and the data lines are arranged in a crossed manner; the driving circuit layer includes: a plurality of thin film transistors;
the scanning line is electrically connected with the grid electrodes of partial thin film transistors in the plurality of thin film transistors;
the data line is electrically connected to sources of some of the plurality of thin film transistors.
9. The display panel according to claim 8, wherein the display panel further comprises: a first conductive layer and a second conductive layer;
the first conductive layer includes: the scanning line and the grid electrode of the thin film transistor;
the second conductive layer includes: the data line, the power signal line, and the source and drain electrodes of the thin film transistor.
10. The display panel according to claim 9, characterized in that the display panel further comprises: the first bonding pad and the second bonding pad are positioned on the substrate and are arranged in the binding region;
the data line extends from the display area to the binding area and is electrically connected with the first bonding pad;
the power signal line extends from the unbonded area to the bonding area and is electrically connected with the second bonding pad.
11. The display panel according to claim 10, wherein the second conductive layer further comprises: the first pad and the second pad.
12. The display panel according to claim 10, characterized in that the display panel further comprises: a chip on film; the chip on film includes: the driving circuit comprises a base film and a driving chip positioned on the base film;
the driving chip is electrically connected with the first bonding pad and the second bonding pad.
13. A tiled screen comprising a plurality of display panels according to any of claims 1 to 12.
14. The spliced screen of claim 13, wherein in two adjacent display panels in the spliced screen, the distribution density of the overlapping vias in the unbound area corresponding to the spliced position is less than the distribution density of the overlapping vias in the unbound area corresponding to other positions.
15. A display device, characterized in that the display device comprises a tiled screen according to claim 14.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210355492.0A CN114725175A (en) | 2022-04-06 | 2022-04-06 | Display panel, spliced screen and display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210355492.0A CN114725175A (en) | 2022-04-06 | 2022-04-06 | Display panel, spliced screen and display device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN114725175A true CN114725175A (en) | 2022-07-08 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210355492.0A Pending CN114725175A (en) | 2022-04-06 | 2022-04-06 | Display panel, spliced screen and display device |
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| Country | Link |
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| CN (1) | CN114725175A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2024065412A1 (en) * | 2022-09-29 | 2024-04-04 | 京东方科技集团股份有限公司 | Chip on film and display device |
-
2022
- 2022-04-06 CN CN202210355492.0A patent/CN114725175A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2024065412A1 (en) * | 2022-09-29 | 2024-04-04 | 京东方科技集团股份有限公司 | Chip on film and display device |
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