CN114695145A

CN114695145A - Board-level system-in-package method and package structure

Info

Publication number: CN114695145A
Application number: CN202110130719.7A
Authority: CN
Inventors: 黄河; 向阳辉; 刘孟彬
Original assignee: Ningbo Semiconductor International Corp
Current assignee: Ningbo Semiconductor International Corp
Priority date: 2020-12-30
Filing date: 2021-01-29
Publication date: 2022-07-01
Also published as: CN114695143A; CN114695142A; CN114695146A; CN114695144A; CN114684780A; CN114695400A

Abstract

A board-level system-level packaging method and a packaging structure are provided, wherein the packaging method comprises the following steps: providing a circuit board, wherein a cavity is formed in the circuit board, a plurality of first welding pads are formed on the surface of the circuit board outside the cavity, and the first welding pads are sunken on the surface of the circuit board; providing a plurality of first chips, wherein a second welding pad is formed on one surface of each first chip and is sunken on the surface of each chip; bonding a first chip on the circuit board, wherein a first gap is defined by the first welding pad and the second welding pad, and the first chip at least covers part of the cavity; and forming a first conductive bump in the first gap by an electroplating process, wherein the first conductive bump is electrically connected with the first welding pad and the second welding pad. The invention improves the packaging efficiency of the board-level system-level packaging process and the compatibility with the chip forming process of the front section.

Description

Board-level system-in-package method and package structure

The present application claims priority from the application entitled "a board level system in package method, structure, circuit board, and method of forming" filed by the national intellectual property office at 30.12.2020, application number 202011624142.7, the entire contents of which are incorporated herein by reference.

Technical Field

The embodiment of the invention relates to the field of semiconductor device manufacturing, in particular to a board-level system-in-package method and a package structure.

Background

The system-in-package is formed by integrally assembling a plurality of active elements/devices, passive elements/devices, MEMS devices, discrete KGD (Known Good chips) such as a photo chip, a biochip, etc., having different functions and prepared by different processes, into a single standard package having a multi-layered device structure in three dimensions (X direction, Y direction, and Z direction) in any combination, and can provide a plurality of functions, forming one system or subsystem.

Flip-Chip (FC) bonding is a common system-level packaging method. The system-in-package method comprises the following steps: providing a PCB (printed circuit board), wherein solder balls (formed by a ball-planting process) arranged according to a certain requirement are formed on the PCB; dipping the circuit board with the soldering flux, and then inversely mounting and mounting the chip on the circuit board; soldering pads (pad) on the chip and solder balls on the circuit board by using a reflow soldering process and then electrically connecting the pads and the solder balls; and filling glue between the bottom of the chip and the circuit board to increase the mechanical strength of the whole structure.

However, the existing system-in-package process still has a large challenge.

Disclosure of Invention

The embodiment of the invention provides a board-level system-level packaging method and a packaging structure, which can improve the packaging efficiency of a board-level system-level packaging process and the compatibility with a front-stage chip forming process.

In order to solve the above problem, an embodiment of the present invention provides a board-level system-in-package method, including: providing a circuit board, wherein a cavity is formed in the circuit board, a plurality of first welding pads are formed on the surface of the circuit board outside the cavity, and the first welding pads are sunken on the surface of the circuit board; providing a plurality of first chips, wherein a second welding pad is formed on one surface of each first chip and is sunken on the surface of each chip; bonding the first chip on the circuit board, wherein a first gap is defined by the first welding pad and the second welding pad, and the first chip at least covers part of the cavity; and forming a first conductive bump in the gap through an electroplating process, wherein the first conductive bump is electrically connected with the first welding pad and the second welding pad.

Correspondingly, an embodiment of the present invention further provides a board-level system-in-package structure, including: the circuit board is provided with a cavity, a plurality of first welding pads are formed on the surface of the circuit board outside the cavity, and the first welding pads are sunken on the surface of the circuit board; the circuit board comprises a plurality of first chips, a plurality of second chips and a plurality of first bonding pads, wherein the plurality of first chips are bonded on the circuit board, one surfaces of the first chips are provided with second bonding pads, the second bonding pads are sunken on the surfaces of the first chips, first gaps are formed by the second bonding pads and the first bonding pads in an opposite surrounding mode, and at least part of the cavities are covered by the first chips; and the electroplated first conductive bump is positioned in the first gap, and the first conductive bump is electrically connected with the first welding pad and the second welding pad. .

Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:

in the board-level system-in-package method provided by the embodiment of the invention, the cavity is formed in the circuit board, the first chip is bonded on the circuit board, the first welding pad of the circuit board and the second welding pad of the first chip are relatively encircled to form the first gap, and then the first conductive bump electrically connected with the first welding pad and the second welding pad is formed in the first gap through the electroplating process, so that the first chip is electrically connected with the circuit board. Compared with the scheme of realizing the electric connection between the chip and the circuit board by welding, firstly, the embodiment of the invention realizes the electric connection between the chip and the circuit board by using the electroplating process, and has simple process flow and high packaging efficiency; secondly, after all the chips are bonded on the circuit board, the conductive bumps for electrically connecting each chip and the circuit board are formed through an electroplating process, and compared with the method of independently welding each chip to be electrically connected with the circuit board, the packaging efficiency is greatly improved; moreover, the electroplating process has high compatibility with the process of the packaging front section, and the traditional chip manufacturing process or the wafer level packaging process is convenient to realize the board level system level packaging process; in addition, the cavity can be used as the working cavity of the first chip, so that when the first chip is prepared, the preparation process of all the working cavities is not required to be completed, the process complexity of preparing the chip is favorably reduced, the chip manufacturing efficiency is improved, and in addition, the cavity (namely the working cavity of the first chip) is arranged in the circuit board, so that the whole thickness of the packaging structure is reduced, and the requirements of thinning and miniaturization of the size of a device are favorably met.

In the board-level system-in-package structure provided by the embodiment of the invention, a cavity is formed in a circuit board, a first chip is bonded on the circuit board, the first chip covers at least part of the cavity, a first welding pad of the circuit board and a second welding pad of the first chip are oppositely enclosed to form a first gap, the first chip and the cavity enclose a working cavity of the first chip, an electroplated first conductive bump is located in the first gap, and the first conductive bump is electrically connected with the first welding pad and the second welding pad so as to realize the electrical connection between the first chip and the circuit board. Compared with the scheme of electrically connecting the chip and the circuit board by welding, the electroplated first conductive bump is formed by correspondingly adopting an electroplating process, and firstly, the process flow for forming the board-level system-level packaging structure provided by the embodiment of the invention is simple, and the packaging efficiency is high; secondly, in the packaging process of forming the board-level system-in-package structure of the embodiment of the invention, after all chips are bonded with the circuit board, the conductive bumps for electrically connecting each chip with the circuit board are formed by an electroplating process, so that compared with the scheme that each chip is individually welded to be electrically connected with the circuit board, the packaging efficiency is greatly improved; moreover, the electroplating process has high process compatibility with the packaging front section, and the board-level system-level packaging process is convenient to realize by utilizing the traditional chip manufacturing process or the wafer-level packaging process in the packaging process of the board-level system-level packaging structure; in addition, the cavity can be used as the working cavity of the first chip, so that when the first chip is prepared, the preparation process of all the working cavities is not required to be completed, the process complexity of preparing the chip is favorably reduced, the chip manufacturing efficiency is improved, and the cavity (namely the working cavity of the first chip) is arranged in the circuit board, so that the whole thickness of the packaging structure is reduced, and the requirements of thinning and miniaturization of the size of a device are favorably met.

Drawings

Fig. 1 to fig. 6 are schematic structural diagrams corresponding to steps of the board-level system-in-package method according to the first embodiment of the invention;

fig. 7 to fig. 8 are schematic structural diagrams corresponding to steps in a second embodiment of the board-level system-in-package method of the invention;

fig. 9 to fig. 10 are schematic structural diagrams corresponding to steps in a third embodiment of the board-level system-in-package method according to the present invention;

fig. 11 is a schematic structural diagram of a board-level system-in-package method according to a fourth embodiment of the invention;

fig. 12 to fig. 13 are schematic structural diagrams corresponding to steps in a fifth embodiment of a board-level system-in-package method according to the invention;

fig. 14 is a schematic structural diagram of a sixth embodiment of the board-level system-in-package method according to the present invention.

Detailed Description

As can be seen from the background, the existing system-in-package method still has a large challenge.

Specifically, taking a flip chip as an example, the conventional system-in-package method has the following disadvantages: 1. the process is complex, so that the packaging efficiency is low; 2. all chips need to be welded on the solder balls in sequence, and the packaging efficiency is low; 3. the chip and the circuit board need to be electrically connected by using a welding process, and the process cannot be compatible with the process of packaging a front section; 4. when larger pressure is applied carelessly in the process of dipping the soldering flux, the circuit board is easy to be fractured.

In order to solve the above problem, an embodiment of the present invention provides a board-level system-in-package method, including: providing a circuit board, wherein a cavity is formed in the circuit board, a plurality of first welding pads are formed on the surface of the circuit board outside the cavity, and the first welding pads are sunken on the surface of the circuit board; providing a plurality of first chips, wherein a second welding pad is formed on one surface of each first chip and is sunken on the surface of each chip; bonding the first chip on the circuit board, wherein the first welding pad and the second welding pad oppositely enclose a first gap, and the first chip at least covers part of the cavity; and forming a first conductive bump in the gap through an electroplating process, wherein the first conductive bump is electrically connected with the first welding pad and the second welding pad.

Compared with the scheme of realizing the electric connection between the chip and the circuit board by welding, firstly, the embodiment of the invention realizes the electric connection between the chip and the circuit board by using the electroplating process, and has simple process flow and high packaging efficiency; secondly, after all the chips are bonded on the circuit board, the conductive bumps for electrically connecting each chip and the circuit board are formed through an electroplating process, and compared with the method of independently welding each chip to be electrically connected with the circuit board, the packaging efficiency is greatly improved; moreover, the electroplating process has high compatibility with the process of the packaging front section, and the traditional chip manufacturing process or the wafer level packaging process is convenient to realize the board level system level packaging process; in addition, the cavity can be used as the working cavity of the first chip, so that when the first chip is prepared, the preparation process of all the working cavities is not required to be completed, the process complexity of preparing the chip is favorably reduced, the chip manufacturing efficiency is improved, and in addition, the cavity (namely the working cavity of the first chip) is arranged in the circuit board, so that the whole thickness of the packaging structure is reduced, and the requirements of thinning and miniaturization of the size of a device are favorably met.

In order to make the aforementioned objects, features and advantages of the embodiments of the present invention comprehensible, specific embodiments accompanied with figures are described in detail below.

Fig. 1 to fig. 6 are schematic structural diagrams corresponding to steps in the first embodiment of the board-level system-in-package method of the present invention.

Referring to fig. 1 and 2 in combination, a circuit board 10 is provided, a cavity 18 is formed in the circuit board 10, a plurality of first pads 11 are formed on the surface of the circuit board 10 outside the cavity 18, and the first pads 11 are recessed on the surface of the circuit board.

The circuit board 10 is used to support and secure a plurality of different circuit components and also to make electrical connections between the circuit components. In this embodiment, the circuit board 10 has a first surface 101 and a second surface 102 opposite to each other. Either one of the first surface 101 and the second surface 102 is a front surface of the circuit board 10, and the other is a back surface of the circuit board 10.

In this embodiment, the Circuit Board 10 may be a Printed Circuit Board (PCB). The circuit board 10 is not limited to a PCB board, but may be other types of circuit boards such as a ceramic circuit board. In the present embodiment, the circuit board 10 includes a Multi layer board (Multi layer board). The multilayer board includes a non-wiring area 10a for forming a cavity 18. The non-wiring region 10a is used to form a cavity 18. In this embodiment, each layer includes at least a substrate 12 and an interconnect structure 14 on a surface of the substrate 12. The interconnect structure 14 may include interconnect lines, and interconnect pads on the interconnect lines. In this embodiment, each laminate further includes: and an interconnection plug 15 penetrating the substrate 12, the interconnection plug connecting the interconnection structures 14 on both sides of the substrate 12. The interconnection plug 15 may include a via hole and a conductive layer plated on a surface of the via hole, and the via hole is filled with an insulating resin. Or, the through hole can be filled with conductive resin, so that the process for forming the conductive layer is saved.

The number of layers of the circuit board 10 may be determined according to actual requirements. The present embodiment is described by taking the circuit board 10 as an example of a three-layer board. In other embodiments, the circuit board may be a single-layer board, a double-layer board, or a four-layer board.

It should be noted that the cavity 18 is formed in the non-wiring region 10a of the circuit board 10, and therefore, in the manufacturing process of the circuit board 10, a circuit structure may not be manufactured in a part of the layer number board or the whole layer number board of the non-wiring region 10a, so that in the process of removing the part of the layer number board or the whole layer number board of the non-wiring region 10a, only the insulating material may be removed without removing the conductive material, and accordingly, the difficulty of the process for forming the cavity 18 is reduced. In other embodiments, when the cavity is formed in a circuit board with partial thickness, a circuit structure can be manufactured in the remaining layer number board at the bottom of the cavity.

In this embodiment, the first chip is bonded on the circuit board 10 subsequently, and the cavity 18 serves as a working cavity of the chip to be bonded, so that when the first chip is prepared, it is not necessary to complete the preparation process of all the working cavities, which is beneficial to reducing the process complexity of preparing the chip and improving the chip manufacturing efficiency.

Specifically, the step of forming the cavity 18 in the circuit board 10 includes: the cavity 18 is formed by removing a part or all of the number of layers of the non-wiring region 10 a. In this embodiment, taking the case where the cavity 18 is located in the circuit board 10 with a partial thickness as an example, a part of the number of layers of the non-wiring region 10a is removed to form the cavity 18. In other embodiments, the cavity may also extend through the circuit board, i.e. the board with the total number of layers of said non-wiring area removed, depending on the functional type of the first chip to be bonded. Correspondingly, in order to reduce the difficulty of the process for forming the cavity, in the manufacturing process of the circuit board, a circuit structure is not formed in all the layers of the non-wiring area. In this embodiment, a laser cutting process is adopted to remove a part of or all of the layers of the non-wiring region 10a, and a cavity 18 is formed in the circuit board 10.

In this embodiment, the cavity 18 is used as a working cavity of the first chip, and the first chip is bonded on the circuit board 10 by a bonding layer, so that, in the step of forming the cavity 18, the bottom area and the depth of the cavity 18 are determined according to the performance of the first chip.

The first bonding pad 11 is used for corresponding electrical connection with a second bonding pad of a subsequent first chip. Specifically, the first bonding pad 11 is recessed on the surface of the circuit board 10, so that after the first chip is bonded on the circuit board 10 subsequently, the first bonding pad 11 and the second bonding pad of the first chip can enclose a first gap, so that the first gap can provide a space for forming the first conductive bump. In this embodiment, the first pads 11 are located on the top layer of the interconnect structures 14 and electrically connected to the corresponding interconnect structures 14.

The first Pad 11 may be a Pad (Pad), but is not limited to a Pad, and may be another conductive block having an electrical connection function. The material of the first pad 11 is a conductive material. In this embodiment, the material of the first pad 11 includes: any one or more of copper, titanium, aluminium, gold, nickel, iron, tin, silver, zinc or chromium.

In this embodiment, a first organic dielectric layer 13 or a first inorganic dielectric layer is formed on the surface (i.e., the first surface 101) of the circuit board 10 on one side of the first pad 11, and the first pad 11 is embedded in the first organic dielectric layer 13 or the first inorganic dielectric layer and partially exposed. In this embodiment, since the electrical connection between the first chip and the circuit board 10 is not required to be realized by using a soldering process, and the solder resist and the flux are not required to be formed on the circuit board 10, the first organic dielectric layer 13 or the first inorganic dielectric layer having the photolithographic bonding property can be formed, thereby improving the forming efficiency of the circuit board 10 and saving the process flow. When the top layer of the circuit board 10 is the first organic medium layer 13 with the photoetching bonding characteristic, the first organic medium layer 13 with a certain thickness can be selected according to requirements, so that the first chip can be conveniently bonded to the circuit board 10 in the subsequent process without additionally forming a bonding layer, the process can be saved, and the forming efficiency of the circuit board can be improved; when the top layer of the circuit board 10 is the first inorganic dielectric layer, the electroplating solution can more easily enter the first gap due to the small surface tension of the electroplating solution on the inorganic dielectric layer, thereby being beneficial to improving the formation yield and efficiency of the first conductive bump; in addition, as the welding assisting layer and the solder mask layer are not required to be formed, the process can be saved, and the forming efficiency of the circuit board is improved.

For better plating and formation of a better first conductive bump, the first pad 11 needs to be disposed to satisfy certain requirements, such as: the area of the first pad 11 exposed is 5 to 200 square micrometers. When the area of the exposed first bonding pad 11 is within the above range, the first bonding pad 11 can be in sufficient contact with the plating solution in the subsequent plating process, so as to avoid the first bonding pad 11 from being in insufficient contact with the plating solution to affect the contact performance of the first conductive bump and the first bonding pad 11, for example, the contact resistance is affected by too small contact area, or the first conductive bump and the first bonding pad cannot be in contact with each other to cause poor electrical contact, and further, the contact area can be ensured not to be too large to reduce the plating efficiency, and meanwhile, the excessive area can not be occupied.

Referring to fig. 3, a plurality of first chips 30 are provided, wherein a second pad 31 is formed on one surface of each first chip 30, and the second pad 31 is recessed in the surface of the first chip 30.

The first chip 30 is used to bond with the circuit board 10. In particular, the first chip 30 is intended to be bonded to the circuit board 10, at least a portion of the first chip 30 being located above the cavity 18, thereby enabling the cavity 18 to function as a working cavity. In this embodiment, the first chip 30 has a third surface 301 and a fourth surface 302 opposite to each other, and the second pad 31 is located on one side of the third surface 301 and recessed in the third surface 301. As an example, the third surface 301 is a chip front surface of the first chip 30, and the fourth surface 302 is a chip back surface of the first chip 30. Wherein the back side of the chip refers to the bottom side of the substrate in the chip. In other embodiments, according to the function type of the first chip, the following may also be: the fourth surface is a front surface of the chip, and the third surface is a back surface of the chip.

In this embodiment, the number of the first chips 30 is plural, and the plural first chips 30 are chips with the same function; alternatively, the plurality of first chips 30 includes at least two chips with different functions, and the chips with different functions are integrated together to realize a certain function. Wherein, the first chip 30 includes: the first chip is at least one of a bare chip, a plastic package layer wrapped on the surface, a shielding layer arranged on the top surface and an interconnection through hole structure penetrating through the chip formed in the first chip. In this embodiment, the surface of the first chip 30 includes an active region 30a and an interconnection region 30b surrounding the active region 30a, and the second pad 31 is located in the interconnection region 30 b.

The first chip 30 includes at least one of a CIS chip, a sensor module chip, a MEMS chip, and a filter chip. The sensor module chip comprises at least one of a biosensor chip, a radio frequency sensing module chip, an infrared radiation sensing module chip, a visible light signal sensing module chip, a sound wave signal sensing module chip and an electromagnetic wave signal sensing module chip. The module chip for sensing the radio frequency signal may be a radio frequency module chip applied in a 5G device, but is not limited to a 5G radio frequency sensor module chip, and may also be other types of radio frequency module chips. The module chip for receiving the infrared radiation signal may be an infrared sensor module chip using an infrared radiation signal for temperature measurement or imaging in a thermal imager, a forehead temperature gun, other types, or the like. The sensor module chip can also be a camera module chip, such as a module chip including a photosensitive chip and an optical filter, which can receive visible light for imaging. The sensor module chip can also be a microphone module chip which can receive sound waves for transmitting sound signals. The sensor module chip is not limited to the type listed here, and may be various types of sensor module chips that can perform a certain function in the art. The MEMS chip comprises a thermopile sensor chip, and the thermopile sensor chip and the logic chip are integrated together to realize an infrared sensing function, such as temperature measurement. The MEMS chip can also be a microphone sensor chip, and the microphone sensor chip and the logic chip are integrated together to realize the sound wave sensing function. The filter chip includes: one or both of a Surface Acoustic Wave (SAW) resonator and a bulk acoustic wave (bulk acoustic wave) resonator. For example, the bulk acoustic wave resonator may be a reflection array type bulk acoustic wave resonator (BAW-SMR), a diaphragm type film bulk acoustic wave (FBAR) resonator, or an air gap type film bulk acoustic wave resonator. The biosensor chip comprises one or two of a fingerprint identification chip and an ultrasonic fingerprint sensor chip.

It should be noted that, according to the functional type of the first chip 30, the first chip 30 may be a chip that requires a cavity at both top and bottom, such as a bulk acoustic wave thin film resonator; the first chip 30 may also be a chip that requires only an upper cavity or a lower cavity, such as a surface acoustic wave resonator.

In this embodiment, taking the first chip 30 as a chip requiring cavities at both the top and bottom (as shown in fig. 3 (a)), the first chip 30 may include a first cavity 3011 as an upper cavity and a cavity 18 in the circuit board 10 as a lower cavity. Specifically, the first chip 30 may be an FBAR filter in a bulk acoustic wave filter, which includes a resonant structure 3013 (including upper and lower electrodes and a piezoelectric film between the upper and lower electrodes), and first cavities 3011 on both sides of the resonant structure 3013 and the cavity 18 in the circuit board.

In other embodiments, the first chip may not include a cavity therein. For example, the first chip is an SMR bulk acoustic wave filter including a resonant structure (including upper and lower electrodes and a piezoelectric film between the upper and lower electrodes) and a bragg reflective layer on one side of the resonant structure, or a saw filter including a resonant structure (including interdigital electrodes and a piezoelectric film). In this case, since the first cavity is formed in the circuit board, it is not necessary to form the third cavity in the first chip when the first chip is manufactured, and thus the process flow can be saved, the cost can be saved, and the process efficiency can be improved. In other embodiments, the first chip may be other chips having a cavity, such as an infrared thermopile sensor.

The second bonding pad 31 is recessed in the third surface 301, so that after the first chip 30 is subsequently bonded to the circuit board 10, the second bonding pad 31 and the first bonding pad 11 enclose a first gap, and the height of the first gap is increased. The second pad 31 may be a pad, but is not limited to a pad, and may also be another conductive block having an electrical connection function. The material of the second pad 31 is a conductive material. In this embodiment, the material of the second pad 31 includes: any one or more of copper, titanium, aluminium, gold, nickel, iron, tin, silver, zinc or chromium. In the present embodiment, the area of the exposed second pad 31 is 5 to 200 square micrometers for similar reasons as the first pad 11.

Referring to fig. 4, a first chip 30 is bonded on the circuit board 10, the first bonding pads 11 and the second bonding pads 31 surround a first gap 32, and the first chip 30 covers at least a portion of the cavity 18.

The first voids 32 are used to provide spatial locations for forming the first conductive bumps. The first gap 32 exposes the first pad 11 and the second pad 31, and the first pad 11 and the second pad 31 are made of conductive materials, so that in the process of a subsequent electroplating process, a first conductive bump is formed only on the exposed first pad 11 and the exposed second pad 31 by electroplating, and the first chip 30 covers at least a portion of the cavity 18 to form a working cavity of the first chip 30.

In this embodiment, the first chip 30 is bonded to the circuit board 10 through the bonding layer 20, and the bonding layer 20 is disposed to avoid the first pad 11 and the second pad 31.

The first chip 30 is physically connected with the circuit board 10 through the bonding layer 20, the bonding layer 20 is arranged to avoid the first welding pad 11 and the second welding pad 31, the bonding layer 20 not only realizes the physical connection between the first chip 30 and the circuit board 10, but also the bonding layer 20 is used for defining the forming position of the first conductive bump, so that the first conductive bump is prevented from transversely overflowing in the electroplating process, and the control of the electroplating process is facilitated.

In the present embodiment, the first chip 30 is bonded to the circuit board 10 through a lithographically bondable layer. The bonding manner between the first chip 30 and the circuit board 10 is not limited to this, for example: in other embodiments, the Bonding between the first chip and the circuit board may also be achieved by Fusion Bonding (Fusion Bonding).

In this embodiment, the first chip 30 completely covers the cavity 18, thereby facilitating packaging.

Specifically, the step of bonding the first chip 30 to the circuit board 10 through the bonding layer 20 includes: forming a bonding layer 20 on either or both of the first chip 30 and the surface of the circuit board 10, the bonding layer 20 exposing corresponding pads; the first chip 30 is bonded to the circuit board 10 using a bonding layer 20.

As an example, the bonding layer 20 is formed on the first chip 30. The circuit board 10 has the cavity 18 formed therein, and therefore, the surface flatness of the first chip 30 is higher than that of the circuit board 10, and it is easier to form the bonding layer 20 on the first chip 30.

Specifically, a bonding material is formed on the first chip 30 surface; patterning the bonding material to expose the second pad 31, and using the remaining bonding material as a bonding layer 20; the first chip 30 is placed over the cavity 18 and the first chip 30 is bonded to the circuit board 10 by the bonding layer 20. In other embodiments, a bonding layer may also be formed on the circuit board, specifically, the circuit board has a bonding region, where the bonding region refers to a region for bonding with the first chip, and after a lithographically bondable material is formed on the circuit board, the lithographically bondable material is patterned to expose the first pad and the cavity, and the lithographically bondable material remaining outside the bonding region is also removed, and the remaining patterned bonding material serves as the bonding layer. By forming the bonding layer on the circuit board, the bonding layer can be formed outside each cavity in the same step, and the packaging efficiency is improved.

In the present embodiment, the material of the bonding layer 20 includes: a film-like dry film or a liquid dry film. The elastic modulus of the dry film material is relatively small, and the dry film material is easily deformed and not damaged when subjected to thermal stress, which is beneficial to reducing the bonding stress between the first chip 30 and the circuit board 10. It should be noted that the material of the first organic medium layer 13 may be a bonding material, in which case the bonding layer 20 does not need to be separately formed, which can save the process.

In other embodiments, the bonding layer may also be one or more of a die attach film, a dielectric material, glass, and a polymer material, the dielectric material including: silicon oxide or silicon nitride.

In other embodiments, the dielectric material comprises: silicon oxide. The third surface is made of silicon oxide, the first inorganic medium layer is made of silicon oxide, correspondingly, the first device wafer and the circuit board are bonded together through a fusion bonding process, silicon oxide-silicon oxide covalent bonds are formed between the bonding layer and the first device wafer and between the bonding layer and the circuit board, and the bonding layer and the first device wafer and between the bonding layer and the circuit board have high bonding strength, so that the packaging yield of the board-level system packaging is improved.

The bonding layer can also be made of glass, the first device wafer and the circuit board are correspondingly bonded by adopting glass medium bonding, the glass medium bonding refers to that glass solder is printed on the first device wafer or the circuit board, then the first device wafer and the circuit board are placed in a reflow furnace for pre-sintering, the first device wafer after pre-sintering is aligned with the circuit board, the first chip is located right below the bonding layer, and then the first device wafer and the circuit board are placed in a bonding machine for sintering. The glass medium bonding process is simple, the bonding strength is high, the sealing effect is good, and the glass medium bonding process is particularly suitable for mass production.

In this embodiment, the bonding layer 20 covers the remaining area outside the first gap 32 between the first chip 30 and the circuit board 10 outside the cavity 18, and the bonding layer 20 is used to define the forming position of the first conductive bump, that is, the bonding layer 20 encloses the boundary of the first gap 32, so as to prevent the subsequent first conductive bump from exceeding the boundary, thereby facilitating the control of the electroplating process and preventing the first conductive bump from laterally overflowing during the electroplating process. In addition, since the physical connection between the first chip 30 and the circuit board 10 is realized through the bonding layer 20, the bonding layer 20 covers the remaining area outside the first gap 32 between the first chip 30 and the circuit board 10 outside the cavity 18, and the mechanical strength of the package structure is enhanced.

In the present embodiment, the thickness of the bonding layer 20 is 5 μm to 200 μm, and the bonding layer 20 covers at least 10% of the area of the first chip 30, so as to ensure the bonding strength between the first chip 30 and the circuit board 10. In the present embodiment, the height of the first voids 32 is 5 μm to 200 μm. When the height of the first gap 32 is 5 μm to 200 μm, the electroplating solution can easily enter the first gap 32 to perform the electroplating process in the subsequent electroplating process, and the problem of overlong electroplating time due to too large height of the first gap 32 can be avoided, so that the electroplating efficiency and the electroplating yield can be considered.

In this embodiment, in order to better perform the plating process, the first pad 11 and the second pad 31 are designed to include a facing portion and a staggered portion. The first pad 11 and the second pad 31 include opposite portions to ensure that the first conductive bump formed subsequently can be in good contact with both the first pad 11 and the second pad 31, so as to ensure that the first pad 11 and the second pad 31 can be electrically connected with each other. On the other hand, the first bonding pad 11 and the second bonding pad 31 further include a staggered portion, and the staggered portion is more easily contacted with the electroplating solution, so that the electroplating solution is easily flowed into the first gap 32 under the condition that the first gap 32 is smaller, and further, a relatively intact first conductive bump is formed.

In this embodiment, the area of the facing portion of the first pad 11 and the second pad 31 is larger than one half of the area of the first pad 11 or the second pad 31. When the area of the facing portion of the first bonding pad 11 and the second bonding pad 31 is greater than one half of the area of the first bonding pad 11 or the second bonding pad 31, the electroplating process can be better realized, which is beneficial to completely filling the formed first conductive bump in the first gap 32 as much as possible, thereby ensuring that the first conductive bump and the first bonding pad 11 and the second bonding pad 31 have enough contact area, and correspondingly being beneficial to realizing lower contact resistance.

Referring to fig. 5, a first conductive bump 40 is formed in the first gap 32 through an electroplating process, and the first conductive bump 40 electrically connects the first pad 11 and the second pad 31.

The first conductive bump 40 is used to electrically connect the first pad 11 and the second pad 31, and accordingly, the first chip 30 and the circuit board 10 are electrically connected. Wherein the bonding layer 20 covers a region of the periphery of the first conductive bump 40 between the first chip 30 and the surface of the circuit board 10 outside the cavity 18.

Compared with the scheme of realizing the electrical connection between the chip and the circuit board by welding, the embodiment realizes the electrical connection between the chip and the circuit board 10 by using the electroplating process, and has simple process flow and high packaging efficiency; secondly, in the embodiment, after all the chips are bonded with the circuit board 10, the conductive bumps for electrically connecting each chip with the circuit board 10 are formed through an electroplating process, so that the packaging efficiency is greatly improved compared with a scheme of individually welding each chip to be electrically connected with the circuit board; moreover, the electroplating process has high process compatibility with the packaging front section, and the board-level system-level packaging process is convenient to realize by utilizing the traditional chip manufacturing process or the wafer-level packaging process.

In this embodiment, the materials of the first pad 11 and the second pad 31 include: any one or more of copper, titanium, aluminum, gold, nickel, iron, tin, silver, zinc, and chromium, and the material of the first conductive bump 40 accordingly includes: any one or more of copper, titanium, aluminium, gold, nickel, iron, tin, silver, zinc and chromium. In the present embodiment, the material of the first conductive bump 40 is the same as the material of the second pad 11 and the first pad 31, so that the first conductive bump 40 is easier to form in the first gap 32. The material of the first conductive bump 40 may be different from the material of the first pad 11 or the second pad 31, and in order to form the first conductive bump 40 more easily, a material layer may be formed on the first pad 11 or the second pad 31, and the material layer is the same as the material of the conductive bump 40.

In this embodiment, the electroplating process includes electroless plating. The plating solution used for the electroless plating is determined according to the material of the conductive bump to be formed and the materials of the first pad 11 and the second pad 31. In this embodiment, the electroless plating includes: electroless palladium plating immersion gold (ENEPIG), wherein the time of chemical nickel is 30 minutes to 50 minutes, the time of chemical gold is 4 minutes to 40 minutes, and the time of chemical palladium is 7 minutes to 32 minutes; or, chemical nickel gold, wherein the chemical nickel time is 30 minutes to 50 minutes, and the chemical gold time is 4 minutes to 40 minutes; or, chemical nickel, wherein the time of chemical nickel is 30 minutes to 50 minutes.

In this embodiment, when the plating process selects electroless palladium gold immersion (ENEPIG) or electroless nickel gold (ENIG), the process parameters may refer to table 1.

TABLE 1

In this embodiment, before the chemical plating, in order to better complete the electroplating process, the surfaces of the first pad 11 and the second pad 31 may be cleaned first, so as to remove the natural oxide layer on the surfaces of the first pad 11 and the second pad 31 and improve the surface wettability (wettability) of the first pad 11 and the second pad 31; an activation process may then be performed to promote nucleation growth of the plating metal on the metal to be plated.

In this embodiment, the cross-sectional area of the first conductive bump 40 is greater than 10 square microns, so that the area occupied by the first conductive bump 40 is not too large, the bonding strength between the first conductive bump 40 and the first pad 11 or the second pad 31 is ensured, and the good electrical connection between the first pad 11 and the second pad 31 is ensured.

Referring to fig. 6, in the present embodiment, the board level system in package method further includes: after the first conductive bump 40 is formed, a molding compound layer 50 is formed to cover the first chip 30 and the circuit board 10.

The molding compound layer 50 is used for realizing the package integration of the first chip 30 and the circuit board 10. The plastic package layer 50 can also play the roles of insulation, sealing and moisture protection, and is beneficial to improving the reliability of the packaging structure. The plastic package layer 50 is made of a plastic package (Molding) material, for example: and (3) epoxy resin. The epoxy resin has the advantages of low shrinkage, good cohesiveness, good corrosion resistance, excellent electrical property, lower cost and the like.

In this embodiment, the plastic package layer 50 is formed by a plastic package process. Specifically, the molding layer 50 may be formed through an injection molding process. The filling performance of the injection molding process is good, so that the injection molding agent can be well filled in the exposed residual space of the first conductive bump 40. In other embodiments, other processes may be used to form the molding layer. It should be noted that in other embodiments, the molding layer may not be formed based on the actual device function requirement. For example, when the bonded first chip is an image sensor chip module, the molding layer may not be formed. If the plastic package layer is formed, an opening is required to be formed on the image sensor chip module to expose the optical filter.

Fig. 7 to fig. 8 are schematic structural diagrams corresponding to steps in a second embodiment of the board-level system-in-package method of the invention.

The same parts of this embodiment as those of the previous embodiments are not described herein again. The present embodiment differs from the previous embodiments in that: in the process of forming the first conductive bump 40 in the first gap, a second conductive bump 80 is also formed on the second surface of the back of the circuit board 10.

Referring to fig. 7, a circuit board 10 is provided, a cavity 18 is formed in the circuit board 10, a plurality of first pads 11 are formed on the surface of the circuit board 10 outside the cavity 18, and the first pads 11 are recessed in the surface of the circuit board 10.

The circuit board 10 includes opposing first and

second surfaces

101 and 102. In this embodiment, a cavity 18 is formed in the first surface 101 of the circuit board 10. In this embodiment, the circuit board 10 comprises a plurality of boards, each of which includes at least a substrate 12 and an interconnect structure 14 on a surface of the substrate 12. The circuit board 10 further includes third pads 16, and the third pads 16 are located on the bottom layer of the interconnect structures 14 and electrically connected to the corresponding interconnect structures 14. Specifically, the third pads 16 are formed on the second surface 102 of the circuit board 10. A portion of the surface of the third bonding pad 16 is exposed at the second surface 102 for subsequent formation of a second conductive bump during the electroplating process. The third bonding pad 16 is recessed in the second surface 102 to facilitate the formation of the second conductive bump.

In this embodiment, a part of the surface of the interconnection structure 14 located at the bottom layer is exposed to the second surface 102, and the part of the interconnection structure 14 exposed by the second surface 102 is used as the third pad 16, so that it is not necessary to additionally form a pad on the second surface 102, which is beneficial to simplifying the process; alternatively, the third pad 16 is formed on the underlying interconnect structure 14 and exposed to the second surface 102.

In this embodiment, a second organic dielectric layer 17 or a second inorganic dielectric layer is formed on the surface (i.e., the second surface 102) of the circuit board 10 on the side of the third pad 16, and the third pad 16 is disposed in the second organic dielectric layer 17 or the second inorganic dielectric layer and partially exposed. For the specific description of the second organic dielectric layer 17 and the second inorganic dielectric layer, reference may be made to the description of the first organic dielectric layer and the first inorganic dielectric layer in the foregoing embodiments, and details are not repeated here.

For better subsequent electroplating to form a second conductive bump, the third pad 16 is also required to satisfy certain requirements, such as: the area of the third bonding pad 16 exposed is 5 to 200 square micrometers. When the exposed area of the third bonding pad 16 is within the above range, the third bonding pad 16 can be in sufficient contact with the plating solution in the subsequent plating process, so as to prevent the third bonding pad 16 from being in insufficient contact with the plating solution and affecting the contact performance between the second conductive bump and the third bonding pad 16, for example, if the contact area is too small, the contact resistance is affected, or the contact cannot be made, the poor electrical contact is caused, and it can be ensured that the contact area is not too large, the plating efficiency is not reduced, and meanwhile, too much area is not occupied.

The first chip 30 is bonded to the circuit board 10 through the bonding layer 20, the bonding layer 20 is disposed to avoid the first pad 11 and the second pad 31, and the first pad 11 and the second pad 31 relatively enclose a first gap 32.

Referring to fig. 8, a first conductive bump 40 is formed in the first void 32 and a second conductive bump 80 is formed on the third pad 16 through an electroplating process. The second conductive bump 80 is used to electrically connect the circuit board 10 with other chips or components.

In the present embodiment, the first conductive bump 40 for electrical connection of the first chip 30 and the circuit board 10 and the second conductive bump 80 for electrical connection of the circuit board 10 and other chips or components are formed through the electroplating process in the same step, which greatly improves the packaging efficiency. In other embodiments, the first conductive bump and the second conductive bump may be formed by separately performed electroplating processes in different steps. In other embodiments, the second conductive bump can be formed by other processes (e.g., ball-mounting process).

For the specific description of the encapsulation method in this embodiment, reference may be made to the corresponding description in the foregoing embodiment, and this embodiment is not described herein again.

Fig. 9 to fig. 10 are schematic structural diagrams corresponding to steps in the third embodiment of the board-level system-in-package method of the invention.

The same parts of this embodiment as those of the previous embodiments are not described herein again. The present embodiment differs from the previous embodiments in that: a first chip 30 is bonded to both of the opposite faces of the circuit board 10.

Referring to fig. 9, a circuit board 10 is provided, the circuit board 10 having opposing first and

second surfaces

101, 102. The cavity 18 is correspondingly formed in the first surface 101 and the second surface 102.

The cavity 18 is located in a partial thickness of the circuit board 10, and the cavity 18 is correspondingly formed in the first surface 101 and the second surface 102.

With continued reference to fig. 9, the first chip 30 is bonded on the first surface 101 and the second surface 102, respectively, the bonding layer 20 is further disposed to avoid the third pad 16, and the third pad 16 and the second pad 31 are opposite to each other to form a second gap 325.

The first chip 30 is bonded to two opposite surfaces of the circuit board 10, which is beneficial to improving the integration level of the package. The types of the first chips 30 bonded to the first surface 101 and the second surface 102 of the circuit board 10 may be the same or different.

Referring to fig. 10, a first conductive bump 40 is formed in the first gap 32 through an electroplating process, and the first conductive bump 40 electrically connects the first pad 11 and the second pad 31.

In this embodiment, during the electroplating process, a fourth conductive bump 81 is further formed in the second gap 35, and the fourth conductive bump 81 is electrically connected to the third pad 16 and the second pad 31. After all the first chips 30 are bonded to the circuit board 10, the first conductive bumps 40 can be formed in the first voids 32 and the fourth conductive bumps 81 can be formed in the second voids 35 at the same time when the plating process is performed, which greatly improves the packaging efficiency.

In other embodiments, the first conductive bump may be formed in the first gap on the first surface side of the circuit board and the fourth conductive bump may be formed in the second gap on the second surface side of the circuit board by two electroplating processes in different steps. After the first conductive bump on one side of the circuit board is formed, a molding layer or a protective layer covering the circuit board, the first chip and the first conductive bump can be formed on the side on which the first conductive bump is formed to cover the formed first conductive bump, so that the first conductive bump on the side can be prevented from being influenced in an electroplating process performed on the other surface of the circuit board.

For a specific description of the packaging method in this embodiment, reference may be made to the corresponding description in the foregoing embodiments, and details of this embodiment are not repeated herein.

Fig. 11 is a schematic structural diagram of a board-level system-in-package method according to a fourth embodiment of the invention.

The same parts of this embodiment as those of the previous embodiments are not described herein again. The present embodiment differs from the previous embodiments in that: in the step of providing the circuit board 10, the cavity 18 is located in a part of the thickness of the circuit board 10, and a plurality of air holes 19 are formed in the circuit board 10 at the bottom of the cavity 18 through the remaining thickness.

The actual device functional requirements of the first chip 30 are met by forming a plurality of air holes 19 through the remaining thickness in the circuit board 10 at the bottom of the cavity 18. For example, the first chip 30 is a sensor module chip, and the sensor module chip is a microphone sensor chip, and the microphone sensor chip is enabled to perform an acoustic wave sensing function by forming the air hole 19.

In this embodiment, after the cavity 18 is formed in the circuit board 10, the circuit board 10 with the remaining thickness at the bottom of the cavity 18 is etched by using a laser cutting process. Therefore, in the present embodiment, in the manufacturing process of the circuit board 10, the circuit structures are formed in all the layers of the non-wiring region, so that in the process of forming the cavity 18 and the air hole 19, only the insulating material can be removed without removing the conductive material, and accordingly, the difficulty of the process of forming the cavity 18 and the air hole 19 is reduced.

Fig. 12 to fig. 13 are schematic structural diagrams corresponding to steps in a fifth embodiment of a board-level system-in-package method according to the invention.

The parts of this embodiment that are the same as the parts of the previous embodiment will not be described herein again. The present embodiment differs from the previous embodiments in that: the packaging method realizes three-dimensional packaging (3D package).

Referring to fig. 12, a first chip 30 is provided, the first chip 30 has a third surface 301 and a fourth surface 302 opposite to each other, the second pad 31 is disposed on one side of the third surface 301 and recessed in the third surface 301, the first chip 30 further includes a fourth pad 36, the fourth pad 36 is disposed on one side of the fourth surface 302 and recessed in the fourth surface 302, and the fourth pad 36 and the second pad 31 are electrically connected.

In this embodiment, the first chip 30 has a via interconnection structure 33 formed therein, an end of the via interconnection structure 34 facing the third surface 301 is connected to the second pad 31, and an end of the via interconnection structure 33 facing the fourth surface 302 is connected to the fourth pad 36. Specifically, the Via interconnection structure 33 is a Through Silicon Via (TSV) interconnection structure.

In this embodiment, a third organic dielectric layer 37 or a third inorganic dielectric layer is formed on the fourth surface 302, and the fourth pad 36 is embedded in the third organic dielectric layer 37 or the third inorganic dielectric layer and partially exposed. For specific description of the third organic dielectric layer 37 and the third inorganic dielectric layer, reference may be made to the description of the first organic dielectric layer and the second inorganic dielectric layer in the foregoing embodiments, and details are not repeated here.

With continued reference to fig. 12, the packaging method further includes: providing a second chip 70, forming a fifth pad 34 on any surface of the second chip 70, and recessing the fifth pad 34 on the surface of the second chip 70.

The second chip 70 is used to bond with the first chip 30 to realize a specific function.

The fifth pad 34 is recessed on the surface of the second chip 70, so that after the bonding between the second chip 70 and the first chip 30 is subsequently performed, the fifth pad 34 and the fourth pad 36 can enclose a third gap. Accordingly, the fifth pad 34 is used to make an electrical connection with the fourth pad 36 of the first chip 30.

The second chip 70 may be of the same type as the first chip 30 or may be of a different type. For the detailed description of the second chip 70 and the fifth pad 34, reference may be made to the corresponding description of the first chip 30 and the second pad 31 in the foregoing embodiments, and details are not repeated herein.

With continued reference to fig. 12, the second chip 70 is bonded to the first chip 30, and the fourth bonding pad 36 and the fifth bonding pad 34 enclose a third gap 35; the first chip 30 is bonded to the circuit board 10.

The second chip 70 is bonded to the first chip 30, and the first chip 30 is bonded to the circuit board 10, so that the second chip 70 and the first chip 30 are stacked in a direction perpendicular to the surface of the circuit board 10, and accordingly, a three-dimensional package (3D package) is realized.

In this embodiment, after the first chip 30 is bonded to the circuit board 10, the second chip 70 is bonded to the first chip 30, so that the circuit board 10 can function as a support carrier in the process of implementing the second chip 70 and the first chip 30. In other embodiments, the first chip may be bonded to the circuit board after the second chip is bonded to the first chip.

In this embodiment, the second chip 70 and the first chip 30 are bonded together, and the fourth pad 36 and the fifth pad 34 are opposite to each other to form a third gap 35, so that a third conductive bump is formed in the third gap 35 by a subsequent electroplating process.

Regarding the bonding manner between the second chip 70 and the first chip 30, reference may be made to the foregoing corresponding description of the step of bonding the first chip 30 to the circuit board 10, and details are not repeated herein.

Referring to fig. 13, a first conductive bump 40 is formed in the first void 32 through an electroplating process.

The board-level system-in-package method further comprises the following steps: a third conductive bump 75 is formed in the third gap 35 by an electroplating process, and the third conductive bump 75 electrically connects the fourth pad 36 and the fifth pad 34.

The third conductive bump 75 electrically connects the fourth pad 36 and the fifth pad 34, thereby achieving electrical connection between the first chip 30 and the second chip 70. In this embodiment, after the first chip 30 and the second chip 70 are bonded, the first conductive bump 40 and the third conductive bump 75 are formed in the same electroplating process. The packaging process is simplified, and the packaging efficiency is improved. In other embodiments, the second conductive bump may be formed first after the second chip is bonded to the first chip, and then the first chip is bonded to the circuit board. The electrical connection between the second chip and the first chip is not limited to this. In other embodiments, the first chip may be bonded on the circuit board and the first conductive bump is formed by an electroplating process, and then the second chip and the first chip are electrically connected by directly using the solder ball. Or, according to the process requirement, the second chip is electrically connected with the first chip in a routing mode. Moreover, the second chip 70 may further continue to be stacked in a bonding manner, and a method of stacking the chips in the bonding manner is similar to the method of stacking the second chip 70 in the bonding manner, and is not described herein again.

For a detailed description of the electroplating process, the first conductive bump 40 and the second conductive bump 75, please refer to the corresponding description of the previous embodiments, which is not repeated herein.

Fig. 14 is a schematic structural diagram corresponding to each step in the sixth embodiment of the board-level system-in-package method of the invention.

The same parts of this embodiment as those of the previous embodiments are not described herein again. The present embodiment differs from the previous embodiments in that: an interconnect chip 300 is also bonded on the circuit board 10.

Referring to fig. 14, in the step of providing the circuit board 10, a plurality of sixth pads 55 are further formed on the surface of the circuit board 10 outside the cavity 18, and the sixth pads 55 are recessed on the surface of the circuit board 10.

The specific description of the sixth pad 55 can be combined with the corresponding description of the first pad, and is not repeated herein.

With continuing reference to fig. 14, the packaging method further includes: providing a plurality of interconnection chips 300, wherein the interconnection chips 300 are formed with conductive structures 305, and one surface of the interconnection chip 300 exposes a part of the conductive structures 305; bonding the interconnection chip 300 to the circuit board 10 with the conductive structures 305 and the sixth pads 55 relatively enclosing a fourth gap (not labeled); a fifth conductive bump 45 is formed in the fourth void by an electroplating process, and the fifth conductive bump 45 electrically connects the sixth pad 55 and the conductive structure 305 of the interconnect chip 300. Wherein the interconnect chip 300 is located on the circuit board 10 at the side of the first chip 30.

One of the surfaces of the interconnect chip 300 exposes a portion of the conductive structure 305, so that the conductive structure 305 can be electrically connected to the sixth pad 55. In this embodiment, the first conductive bump 40 and the fifth conductive bump 45 are formed in the same electroplating process, which is beneficial to improving the packaging efficiency.

In this embodiment, the interconnect chip 300 may be electrically connected to the circuit board 10 or electrically connected to the first chip 30 through the circuit board 10 by designing the wiring manner of the conductive structures 14 in the circuit board 10. The interconnection chip 300 may be used to electrically lead out the circuit board 10, so that the circuit board 10 may be subsequently interconnected with an external circuit or other chips through the interconnection chip 300; the interconnection chip 300 may also be used to electrically lead out the first chip 30, so as to lead out the terminals of the first chip 30 into the interconnection chip 300, so as to change the interconnection position of the first chip 30 and redistribute the terminals of the first chip 30.

In this embodiment, the conductive structure 305 penetrates through the interconnect chip 300, and both ends of the conductive structure 305 are exposed, wherein one end is used for electrically connecting with the sixth pad 55, and the other end is used for electrically connecting with other chips or external circuits. As an example, the conductive structure 305 includes an interconnect line 310 and a pad on one surface of the interconnect die 300, and a plug 320 embedded in the interconnect die 300 from the opposite surface, the plug 320 being connected to the interconnect line 310. Wherein, a surface of the interconnection chip 300 exposes a portion of the interconnection line 310, and a portion of the interconnection line 310 exposed by the surface of the interconnection chip 300 serves as a pad (not labeled). In other embodiments, the conductive structure may include only plugs extending through the interconnect die, the plugs being correspondingly exposed portions of the surface of the interconnect die. In other embodiments, the conductive structure may also include an interconnect line and a pad, where the pad is an exposed portion of the surface of the interconnect die, and the electrical property of the interconnect die may be subsequently extracted by forming a plug embedded in the interconnect die from the opposite surface.

Correspondingly, the invention also provides a board-level system-in-package structure. Fig. 6 is a schematic structural diagram of a board-level system-in-package structure according to a first embodiment of the invention.

In this embodiment, the board-level system-in-package structure includes: the circuit board 10, a cavity 18 is formed in the circuit board 10, a plurality of first bonding pads 11 are formed on the surface of the circuit board 10 outside the cavity 18, and the first bonding pads 11 are recessed on the surface of the circuit board 10; a plurality of first chips 30 bonded on the circuit board 10, wherein a second pad 31 is formed on one surface of the first chip 30, the second pad 31 is recessed in the surface of the first chip 30, the second pad 31 and the first pad 11 enclose a first gap (not labeled), and the first chip covers at least a portion of the cavity; and a first conductive bump 40 which is plated and is positioned in the first gap, wherein the first conductive bump 40 is electrically connected with the first bonding pad 11 and the second bonding pad 31.

Compared with the scheme of electrically connecting the chip and the circuit board by welding, the electroplated first conductive bump is formed by correspondingly adopting an electroplating process, and firstly, the process flow for forming the board-level system-level packaging structure provided by the embodiment of the invention is simple, and the packaging efficiency is high; secondly, in the packaging process of forming the board-level system-in-package structure of the embodiment of the invention, after all chips are bonded with the circuit board, the conductive bumps for electrically connecting each chip with the circuit board are formed by an electroplating process, so that compared with the scheme that each chip is individually welded to be electrically connected with the circuit board, the packaging efficiency is greatly improved; moreover, the electroplating process has high process compatibility with the packaging front section, and the board-level system-level packaging process is convenient to realize by utilizing the traditional chip manufacturing process or the wafer-level packaging process in the packaging process of the board-level system-level packaging structure; in addition, the cavity can be used as the working cavity of the first chip, so that when the first chip is prepared, the preparation process of all the working cavities is not required to be completed, the process complexity of preparing the chip is favorably reduced, the chip manufacturing efficiency is improved, and the cavity (namely the working cavity of the first chip) is arranged in the circuit board, so that the whole thickness of the packaging structure is reduced, and the requirements of thinning and miniaturization of the size of a device are favorably met.

In this embodiment, the circuit board 10 may be a printed circuit board. The circuit board 10 is not limited to a PCB board, but may be other types of circuit boards such as a ceramic circuit board. In this embodiment, the circuit board 10 includes a Multi layer board (Multi layer board). The multilayer board includes a non-wiring area 10a for forming a cavity 18. The non-wiring region 10a is used to form a cavity 18. In this embodiment, each layer includes at least a substrate 12 and an interconnect structure 14 on a surface of the substrate 12. The interconnect structure 14 may include interconnect lines, and interconnect pads on the interconnect lines. In this embodiment, each laminate further includes: and an interconnection plug 15 penetrating the substrate 12, the interconnection plug connecting the interconnection structures 14 on both sides of the substrate 12. The number of layers of the circuit board 10 may be determined according to actual requirements. The present embodiment is described by taking the circuit board 10 as a three-layer board as an example. In other embodiments, the circuit board may be a single-layer board, a double-layer board, a four-layer board, or the like.

In this embodiment, the first chip 30 is bonded to the circuit board 10, and the cavity 18 is a part of the working cavity of the first chip 30. Therefore, when the first chip 30 is manufactured, it is not necessary to complete the manufacturing process of all the working cavities, which is beneficial to reducing the complexity of the process for manufacturing the first chip 30 and improving the chip manufacturing efficiency, and moreover, a part of the working cavity of the first chip 30 is arranged in the circuit board 10, which reduces the overall thickness of the package structure and is beneficial to meeting the requirements of thinning and miniaturization of the device size.

In this embodiment, the cavity 18 is located in a portion of the thickness of the circuit board 10. In other embodiments, the cavity may also extend through the circuit board depending on the type of function of the first chip.

In this embodiment, the cavity 18 is used as a part of the working cavity of the first chip 30, and therefore, the bottom area and depth of the cavity 18 are determined according to the performance of the first chip 30.

The cavity 18 is located in a portion of the thickness of the circuit board 10, the cavity 18 being located in either or both of the first surface 101 and the second surface 102. In this embodiment, the cavity 18 is located on the first surface 101 of the circuit board 10 as an example.

The first pads 11 are used for corresponding electrical connection with the second pads 31 of the first chip 30. Specifically, the first pad 11 is recessed on the surface of the circuit board 10, so that the first pad 11 and the second pad 31 can enclose a first gap, so that the first gap can provide a space for forming the first conductive bump 40.

In this embodiment, the first pads 11 are located on the top layer of the interconnect structures 14 and electrically connected to the corresponding interconnect structures 14. The first pad 11 may be a pad, but is not limited to a pad, and may also be another conductive block having an electrical connection function. The material of the first pad 11 is a conductive material. In this embodiment, the material of the first pad 11 includes: any one or more of copper, titanium, aluminium, gold, nickel, iron, tin, silver, zinc or chromium.

In this embodiment, a first organic dielectric layer 13 or a first inorganic dielectric layer is formed on the surface (i.e., the first surface 101) of the circuit board 10 on one side of the first pad 11, and the first pad 11 is embedded in the first organic dielectric layer 13 or the first inorganic dielectric layer and partially exposed.

In this embodiment, the first conductive bump 40 is formed by an electroplating process, and since a soldering process is not required to achieve electrical connection between the first chip 30 and the circuit board 10, a solder resist and a flux are not required to be formed on the circuit board 10, and the first organic dielectric layer 13 or the first inorganic dielectric layer having a photolithographic bonding characteristic can be formed, thereby improving the forming efficiency of the circuit board 10 and saving the process flow. When the top layer of the circuit board 10 is the first organic medium layer 13 with the photoetching bonding characteristic, the first organic medium layer 13 with a certain thickness can be selected according to requirements, so that the first chip 30 can be conveniently bonded to the circuit board 10, and a bonding layer does not need to be additionally formed, so that the process can be saved, and the forming efficiency of the circuit board can be improved; when the top layer of the circuit board 10 is the first inorganic dielectric layer, the electroplating solution can enter the first gap more easily due to the small surface tension of the electroplating solution on the inorganic dielectric layer, thereby improving the formation yield and efficiency of the first conductive bump 40.

The first chip 30 is bonded to the circuit board 10 such that the cavity 18 can be part of a working cavity of the first chip 30. In this embodiment, the first chip 30 has a third surface 301 and a fourth surface 302 opposite to each other, and the second pad 31 is located on one side of the third surface 301 and recessed in the third surface 301. As an example, the third surface 301 is a chip front surface of the first chip 30, and the fourth surface 302 is a chip back surface of the first chip 30. In other embodiments, according to the function type of the first chip, the following steps may also be performed: the fourth surface is a front surface of the chip, and the third surface is a back surface of the chip.

In this embodiment, the number of the first chips 30 is multiple, and the multiple first chips 30 are chips with the same function; alternatively, the plurality of first chips 30 may include at least two chips with different functions, and the chips with different functions may be integrated together to realize a certain function. In this embodiment, the first chip 30 is exemplified as a chip requiring a cavity at both the top and bottom. Specifically, the first chip 30 may be an FBAR filter in a bulk acoustic wave filter, which includes a resonant structure 3013 (including upper and lower electrodes and a piezoelectric film between the upper and lower electrodes) and a first cavity 3011 as an upper cavity on both sides of the resonant structure 3013 and a cavity 18 as a lower cavity in the circuit board 10. In other embodiments, the first chip may be other chips having a cavity, such as an infrared thermopile sensor. For the specific description of the first chip 30, reference may be made to the corresponding description in the foregoing embodiments, and details are not repeated herein.

The second pad 31 is recessed in the third surface 301, so that the second pad 31 and the first pad 11 enclose a first gap, and the height of the first gap is increased.

The first voids 32 are used to provide spatial locations for forming the first conductive bumps 40. The first gap 32 exposes the first pad 11 and the second pad 31, and the first pad 11 and the second pad 31 are made of conductive materials, so that the first conductive bump is formed only on the exposed first pad 11 and the exposed second pad 31 by electroplating in the electroplating process for forming the first conductive bump 40.

In this embodiment, the height of the first gap is 5 μm to 200 μm, which is beneficial to making the electroplating solution easily enter the first gap for electroplating process, improving the formation quality of the first conductive bump 40, and preventing the height of the first conductive bump 40 from being too large.

In the present embodiment, the first pad 11 and the second pad 31 include facing portions and staggered portions.

The first pad 11 and the second pad 31 include opposite portions to ensure that the first conductive bump formed subsequently can have good contact with both the first pad 11 and the second pad 31, and further ensure that the first pad 11 and the second pad 31 can have good electrical connection through the first conductive bump 40. On the other hand, the first bonding pad 11 and the second bonding pad 31 further include a staggered portion, and the staggered portion is more easily contacted with the electroplating solution, so that the electroplating solution is easily flowed into the first gap when the first gap is smaller, and the formation of the relatively intact first conductive bump 40 is facilitated.

In this embodiment, the area of the facing portion of the first pad 11 and the second pad 31 is larger than one half of the area of the first pad 11 or the second pad 31. When the area of the facing portion of the first bonding pad 11 and the second bonding pad 31 is greater than one half of the area of the first bonding pad 11 or the second bonding pad 31, the electroplating process can be better realized, which is beneficial to completely filling the formed first conductive bump 40 in the first gap as much as possible, thereby ensuring that the first conductive bump 40 and the first bonding pad 11 and the second bonding pad 31 have enough contact areas, and correspondingly being beneficial to realizing lower contact resistance.

In this embodiment, the board-level system-in-package structure further includes: and a bonding layer 20 disposed between the circuit board 10 and the first chip 30 and avoiding the first pad 11 and the second pad 31.

The first chip 30 and the circuit board 10 are physically connected through the bonding layer 20, the bonding layer 20 is arranged to avoid the first bonding pad 11 and the second bonding pad 31, the bonding layer 20 not only realizes the physical connection between the first chip 30 and the circuit board 10, but also defines the forming position of the first conductive bump 40, which is beneficial to preventing the first conductive bump 40 from overflowing transversely in the electroplating process, and facilitates the control of the electroplating process.

In this embodiment, the bonding layer 20 is a lithographically bondable layer. In other embodiments, the bonding layer may also be one or more of a die attach film, glass, a dielectric material, and a polymer material, the dielectric material including: silicon oxide or silicon nitride.

In this embodiment, the first chip 30 completely covers the cavity 18, thereby facilitating subsequent packaging.

In this embodiment, the material of the bonding layer 20 includes: film-like dry film or liquid dry film. The dry film material has a relatively low elastic modulus, and is easily deformed to prevent damage when subjected to a thermal stress, thereby facilitating reduction of a bonding stress between the first chip 30 and the circuit board 10.

In this embodiment, the bonding layer 20 is disposed between the first chip 30 and the circuit board 10 and is disposed to avoid the first bonding pad 11 and the second bonding pad 31, so that the plating solution can flow into the first gap when the first conductive bump 40 is formed by the electroplating process. Specifically, the bonding layer 20 covers the remaining area outside the first gap between the first chip 30 and the circuit board 10 outside the cavity 18, and the bonding layer 20 is used to define the forming position of the first conductive bump 40, that is, the bonding layer 20 encloses the boundary of the first gap, so as to prevent the subsequent first conductive bump 40 from exceeding the boundary, facilitate the control of the electroplating process, and prevent the first conductive bump from laterally overflowing during the electroplating process. In addition, since the physical connection between the first chip 30 and the circuit board 10 is realized through the bonding layer 20, the bonding layer 20 covers the remaining area between the first chip 30 and the circuit board 10 outside the cavity 18 except the first gap, and the mechanical strength of the package structure is enhanced.

In this embodiment, the thickness of the bonding layer 20 is 5 μm to 200 μm, and the bonding layer 20 covers at least 10% of the area of the first chip 30, so as to ensure the bonding strength between the first chip 30 and the circuit board 10.

The first conductive bump 40 is used to electrically connect the first pad 11 and the second pad 31, and accordingly, the first chip 30 and the circuit board 10 are electrically connected. Wherein the bonding layer 20 covers a region of the periphery of the first conductive bump 40 between the first chip 30 and the surface of the circuit board 10 outside the cavity 18. In this embodiment, the cross-sectional area of the first conductive bump 40 is greater than 10 square microns, so that the area occupied by the first conductive bump 40 is not too large, the bonding strength between the first conductive bump 40 and the first pad 11 or the second pad 31 is ensured, and the good electrical connection between the first pad 11 and the second pad 31 is ensured.

In this embodiment, the board-level system-in-package structure further includes: and a molding layer 50 covering the first chip 30 and the circuit board 10.

The molding compound layer 50 is used for realizing the package integration of the first chip 30 and the circuit board 10. The plastic package layer 50 can also play the roles of insulation, sealing and moisture protection, and is beneficial to improving the reliability of the packaging structure. The plastic package layer 50 is made of a plastic package material, for example: and (3) epoxy resin. The epoxy resin has the advantages of low shrinkage, good cohesiveness, good corrosion resistance, excellent electrical property, lower cost and the like. In other embodiments, the board-level system-in-package structure may not include the molding layer based on actual device function requirements. For example, when the bonded first chip is an image sensor chip module, the molding layer may not be formed. If the plastic package layer is formed, an opening is required to be formed on the image sensor chip module to expose the optical filter.

For a specific description of the board-level system-in-package structure in this embodiment, reference may be made to the corresponding description in the foregoing embodiments, and details of this embodiment are not repeated herein.

Fig. 8 is a schematic structural diagram of a board-level system-in-package structure according to a second embodiment of the invention.

The parts of this embodiment that are the same as the parts of the previous embodiment will not be described herein again. The present embodiment differs from the previous embodiments in that: the circuit board 10 further includes third bonding pads 16 on a surface of the circuit board 10 facing away from the first chip 30.

The circuit board 10 includes opposing first and

second surfaces

101 and 102. In this embodiment, the cavity 18 is located in the first surface 101.

In this embodiment, the circuit board 10 comprises a plurality of boards, each of which includes at least a substrate 12 and an interconnect structure 14 on a surface of the substrate 12. The circuit board 10 further includes third pads 16, and the third pads 16 are located on the bottom layer of the interconnect structures 14 and electrically connected to the corresponding interconnect structures 14.

Specifically, the third pads 16 are formed on the second surface 102 of the circuit board 10. A part of the surface of the third pad 16 is exposed to the second surface 10. The third bonding pad 16 is recessed in the second surface 102 to facilitate formation of the second conductive bump. In this embodiment, a part of the surface of the interconnection structure 14 located at the bottom layer is exposed to the second surface 102, and the part of the interconnection structure 14 exposed by the second surface 102 is used as the third pad 16, so that it is not necessary to additionally form a pad on the second surface 102, which is beneficial to simplifying the process; alternatively, the third pad 16 is formed on the underlying interconnect structure 14 and exposed to the second surface 102. In this embodiment, a second organic dielectric layer 17 or a second inorganic dielectric layer is formed on the surface (i.e., the second surface 102) of the circuit board 10 on the side of the third pad 16, and the third pad 16 is disposed in the second organic dielectric layer 17 or the second inorganic dielectric layer and partially exposed.

In this embodiment, the board-level system-in-package structure further includes: and a second conductive bump 80 plated on the third bonding pad 16. The second conductive bump 80 is used to electrically connect the circuit board 10 with other chips or components.

Fig. 10 is a schematic structural diagram of a board-level system-in-package structure according to a third embodiment of the invention.

The same parts of this embodiment as those of the previous embodiments are not described herein again. The present embodiment differs from the preceding embodiments in that: the circuit board 10 has a first chip 30 bonded to opposite surfaces thereof.

The circuit board 10 has opposite first and

second surfaces

101 and 102, and the cavity 18 is located in a portion of the thickness of the circuit board 10 and in the first and

second surfaces

101 and 102, respectively.

The first chip 30 is bonded on the first surface 101 and the second surface 102, respectively, the bonding layer 20 is disposed to avoid the third bonding pad 16, and the third bonding pad 16 and the second bonding pad 31 are opposite to each other to form a second gap.

Correspondingly, a fourth conductive bump 81 is formed in the second gap, and the fourth conductive bump 81 is electrically connected to the second pad 31 and the third pad 16.

Fig. 11 is a schematic structural diagram of a fourth embodiment of a board-level system-in-package structure according to the invention.

The same parts of this embodiment as those of the previous embodiments are not described herein again. The present embodiment differs from the previous embodiments in that: the cavity 18 is located in a portion of the thickness of the circuit board 10, and a plurality of air holes 19 are formed through the remaining thickness in the circuit board 10 at the bottom of the cavity 18.

The actual device functional requirements of the first chip 30 are met by forming a plurality of air holes 19 through the remaining thickness in the circuit board 10 at the bottom of the cavity 18. For example, the first chip 30 is a sensor module chip, and the sensor module chip is a microphone module chip, and the microphone sensor is enabled to realize an acoustic wave sensing function by forming the air hole 19.

Fig. 13 is a schematic structural diagram of a fifth embodiment of a board-level system-in-package structure according to the invention.

The same parts of this embodiment as those of the previous embodiments are not described herein again. The present embodiment differs from the previous embodiments in that: the packaging method is used for realizing three-dimensional packaging (3D package).

The first chip 30 has a third surface 301 and a fourth surface 302 opposite to each other, the second pad 31 is located on one side of the third surface 301 and is recessed in the third surface 301, the first chip 30 further includes a fourth pad 36, the fourth pad 36 is located on one side of the fourth surface 302 and is recessed in the fourth surface 302, and the fourth pad 36 and the second pad 31 are electrically connected.

In the present embodiment, the first chip 30 has a via interconnection structure 33 formed therein, and an end of the via interconnection structure 34 facing the third surface 301 is connected to the second pad 31. Specifically, the via interconnection structure 33 is a through-silicon via interconnection structure. In this embodiment, an end of the via interconnection structure 33 facing the fourth surface 302 is connected to the fourth pad 36. In this embodiment, a third organic dielectric layer 37 or a third inorganic dielectric layer is formed on the fourth surface 302, and the fourth pad 36 is embedded in the third organic dielectric layer 37 or the third inorganic dielectric layer and partially exposed. In this embodiment, since the first chip 30, the circuit board 10 and the second chip are not electrically connected by using a soldering process, and a solder resist and a flux are not required to be formed on the fourth surface 302, a third organic dielectric layer 37 or a third inorganic dielectric layer with a lithographic bonding characteristic can be formed, thereby improving the forming efficiency of the first chip 30 and saving the process flow.

In this embodiment, the board-level system-in-package structure further includes: a second chip 70 bonded to the first chip 30, wherein a fifth pad 34 is formed on any surface of the second chip 70, the fifth pad 34 is recessed in the surface of the second chip 70, and the fifth pad 34 and the fourth pad 36 relatively enclose a third gap; a third conductive bump 75 plated in the third void, the third conductive bump 75 electrically connecting the fourth pad 36 and the fifth pad 34. The second chip 70 is bonded to the first chip 30 to perform a specific function. Wherein the second chip 70 is bonded to the first chip 30, and the first chip 30 is bonded to the circuit board 10, such that the second chip 70 and the first chip 30 are stacked in a direction perpendicular to a surface of the circuit board 10, thereby realizing a three-dimensional package. The second chip 70 may be of the same type as the first chip 30 or may be of a different type. For a detailed description of the second chip 70 and the fifth pad 34, reference may be made to the corresponding description of the first chip 30 and the second pad 31 in the foregoing embodiments, and details are not repeated here.

The fifth pad 34 is recessed in the surface of the second chip 70, so that the fifth pad 34 and the fourth pad 36 can enclose a third gap. Accordingly, the fifth pad 34 is used to make an electrical connection with the fourth pad 36 of the first chip 30.

The type of the second chip 70 may be the same as or different from the type of the first chip 30. For a detailed description of the second chip 70 and the fifth pad 34, reference may be made to the corresponding description of the first chip 30 and the second pad 31 in the foregoing embodiments, and no further description is provided herein.

A third conductive bump 75 is located in the third gap, and the third conductive bump 75 electrically connects the fourth pad 36 and the fifth pad 34, so as to realize the electrical connection between the first chip 30 and the second chip 70.

Fig. 14 is a schematic structural diagram of a sixth embodiment of a board-level system-in-package structure according to the invention.

The same parts of this embodiment as those of the previous embodiments are not described herein again. The present embodiment differs from the previous embodiments in that: the package structure further includes: and an interconnection chip 300 bonded to the circuit board 10 at a side of the first chip 30.

In this embodiment, a plurality of sixth pads 55 are further formed on the surface of the circuit board 10 outside the cavity 18, and the sixth pads 55 are recessed on the surface of the circuit board 10. The specific description of the sixth pad 55 can be combined with the corresponding description of the first pad, and is not repeated herein.

The interconnect chip 300 has a conductive structure 305 formed therein, wherein a surface of the interconnect chip 300 exposes a portion of the conductive structure 305, and the conductive structure 305 and the sixth pad 55 relatively enclose a fourth gap (not shown); and an electroplated fifth conductive bump 45 positioned in the fourth void, the fifth conductive bump 45 electrically connecting the sixth pad 55 and the conductive structure 305 of the interconnect die 300.

One of the surfaces of the interconnect chip 300 exposes a portion of the conductive structure 305, so that the conductive structure 305 can be electrically connected to the sixth pad 55. In this embodiment, the conductive structure 305 penetrates through the interconnect chip 300, and both ends of the conductive structure 305 are exposed, wherein one end is used for electrically connecting with the sixth pad 55, and the other end is used for electrically connecting with other chips or external circuits. As an example, the conductive structure 305 includes an interconnect line 310 and a pad on one surface of the interconnect die 300, and a plug 320 embedded in the interconnect die 300 from the opposite surface, the plug 320 being connected to the interconnect line 310. Wherein, a surface of the interconnection chip 300 exposes a portion of the interconnection line 310, and a portion of the interconnection line 310 exposed by the surface of the interconnection chip 300 serves as a pad (not labeled). In other embodiments, the conductive structure may include only plugs extending through the interconnect die, the plugs being correspondingly exposed portions of the surface of the interconnect die. In other embodiments, the conductive structure may also include an interconnect line and a pad, where the pad is an exposed portion of the surface of the interconnect die, and the electrical property of the interconnect die may be subsequently extracted by forming a plug embedded in the interconnect die from the opposite surface.

Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims

1. A board level system-in-package method is characterized by comprising the following steps:

providing a circuit board, wherein a cavity is formed in the circuit board, a plurality of first welding pads are formed on the surface of the circuit board outside the cavity, and the first welding pads are sunken on the surface of the circuit board;

providing a plurality of first chips, wherein a second welding pad is formed on one surface of each first chip and is sunken on the surface of each first chip;

bonding the first chip on the circuit board, wherein a first gap is defined by the first welding pad and the second welding pad, and the first chip at least covers part of the cavity;

and forming a first conductive bump in the first gap through an electroplating process, wherein the first conductive bump is electrically connected with the first welding pad and the second welding pad.

2. The board-level system-in-package method according to claim 1, wherein the first chip is bonded on the circuit board through a bonding layer, the bonding layer being disposed away from the first bonding pad and the second bonding pad; the bonding layer comprises the following materials: one or more of a lithographically bondable material, including a dry film, a die attach film, glass, a dielectric material, and a polymer material, the dielectric material including silicon oxide or silicon nitride.

3. The board level system-in-package method according to claim 2, wherein the bonding layer has a thickness of 5 μm to 200 μm, and the bonding layer covers at least 10% of the area of the first chip.

4. The board level system-in-package method of claim 1, wherein the first pad and the second pad which are opposite comprise a facing portion and a staggered portion, and the area of the facing portion is larger than one-half of the area of the first pad or the area of the second pad.

5. The board-level system-in-package method according to claim 1, wherein the height of the first voids is 5 μm to 200 μm.

6. The board level system-in-package method of claim 1, wherein an exposed area of the first pad or the second pad is 5-200 μm.

7. The board-level system-in-package method of claim 1, wherein a cross-sectional area of the first conductive bump is greater than 10 square microns.

8. The board level system in package method according to any one of claims 1 to 7, wherein said electroplating process comprises electroless plating.

9. The board-level system-in-package method of claim 8, wherein the electroless plating comprises:

electroless palladium plating and immersion gold, wherein the time of chemical nickel is 30 minutes to 50 minutes, the time of chemical gold is 4 minutes to 40 minutes, and the time of chemical palladium is 7 minutes to 32 minutes;

or, chemical nickel gold, wherein the chemical nickel time is 30 minutes to 50 minutes, and the chemical gold time is 4 minutes to 40 minutes;

or, chemical nickel, wherein the time of chemical nickel is 30 minutes to 50 minutes.

10. The board-level system-in-package method of claim 1, wherein in the step of providing the circuit board, the circuit board has a first surface and a second surface opposite to each other, and the first pads are located on one side of the first surface and recessed in the first surface;

the circuit board further comprises a third welding pad, wherein the third welding pad is positioned on one side of the second surface and is sunken in the second surface;

the board-level system-in-package method further comprises the following steps: forming a second conductive bump on the third pad by an electroplating process;

or in the step of bonding the first chip to the circuit board, the first chip is bonded to the first surface and the second surface respectively, and the third bonding pad and the second bonding pad surround a second gap oppositely;

the board-level system-in-package method further comprises the following steps: and forming a fourth conductive bump in the second gap through an electroplating process, and electrically connecting the third welding pad and the second welding pad.

11. The board-level system-in-package method according to claim 10, wherein a first organic dielectric layer or a first inorganic dielectric layer is formed on the first surface, and the first pad is embedded in the first organic dielectric layer or the first inorganic dielectric layer;

and a second organic medium layer or a second inorganic medium layer is formed on the second surface, and the third welding pad is embedded in the second organic medium layer or the second inorganic medium layer.

12. The board-level system-in-package method according to claim 1, wherein in the step of providing a circuit board, the cavity is located in a partial thickness of the circuit board;

or the cavity is positioned in the circuit board with partial thickness, and a plurality of air holes penetrating through the rest thickness are formed in the circuit board at the bottom of the cavity.

13. The board-level system-in-package method according to claim 1, wherein in the step of providing the circuit board, the circuit board has a first surface and a second surface opposite to each other;

the cavity is located in a portion of the thickness of the circuit board and the cavity is located in either or both of the first and second surfaces.

14. The board level system-in-package method of claim 1, wherein in the step of providing the plurality of chips, the first chip has a third surface and a fourth surface opposite to each other, the second pad is located on one side of the third surface and is recessed in the third surface, the first chip further includes a fourth pad located on one side of the fourth surface and is recessed in the fourth surface, and an electrical connection is formed between the fourth pad and the second pad;

the board-level system-in-package method further comprises the following steps: providing a second chip, wherein a fifth welding pad is formed on any surface of the second chip, and the fifth welding pad is sunken on the surface of the second chip; bonding the first chip and the second chip, wherein a third gap is defined by the fourth welding pad and the fifth welding pad oppositely; and forming a third conductive bump in the third gap through an electroplating process, wherein the third conductive bump is electrically connected with the fourth welding pad and the fifth welding pad.

15. The board-level system-in-package method according to claim 1, wherein in the step of providing the circuit board, a plurality of sixth pads are further formed on the surface of the circuit board outside the first cavity, and the sixth pads are recessed in the surface of the circuit board;

the board-level system-in-package method further comprises the following steps: providing a plurality of interconnection chips, wherein conductive structures are formed in the interconnection chips, and one surfaces of the interconnection chips expose parts of the conductive structures; bonding the interconnection chip on the circuit board, wherein the conductive structure of the interconnection chip and the sixth welding pad oppositely enclose a fourth gap; forming a fifth conductive bump in the fourth void by an electroplating process, the fifth conductive bump electrically connecting the sixth pad and the conductive structure of the interconnect die; wherein the interconnect chip is located on a circuit board on the first chip side; the interconnection chip is electrically connected with the circuit board, or the interconnection chip is electrically connected with the first chip through the circuit board.

16. The board-level system-in-package method according to claim 1, wherein the plurality of first chips are same-function chips; or, the plurality of first chips at least comprise chips with two different functions; the first chip includes: the first chip is at least one of a bare chip, a plastic package layer wrapped on the surface, a shielding layer arranged on the top surface and an interconnection through hole structure penetrating through the chip formed in the first chip;

the first chip includes at least one of a CIS chip, a sensor module chip, a MEMS chip, and a filter chip.

The sensor module chip comprises at least one of a biosensor chip, a radio frequency sensing module chip, an infrared radiation sensing module chip, a visible light signal sensing module chip, an acoustic wave signal sensing module chip and an electromagnetic wave signal sensing module chip; the filter chip comprises one or two of a surface acoustic wave resonator and a bulk acoustic wave resonator; the MEMS chip comprises a microphone sensor chip or a thermopile sensor chip.

17. A board level system-in-package structure, comprising:

the circuit board is provided with a cavity, a plurality of first welding pads are formed on the surface of the circuit board outside the cavity, and the first welding pads are sunken on the surface of the circuit board;

the circuit board comprises a plurality of first chips, a plurality of second chips and a plurality of first bonding pads, wherein the plurality of first chips are bonded on the circuit board, one surfaces of the first chips are provided with second bonding pads, the second bonding pads are sunken on the surfaces of the first chips, first gaps are formed by the second bonding pads and the first bonding pads in an opposite surrounding mode, and at least part of the cavities are covered by the first chips;

and the electroplated first conductive bump is positioned in the first gap, and the first conductive bump is electrically connected with the first welding pad and the second welding pad.

18. The board-level system-in-package structure of claim 17, further comprising: the bonding layer is positioned between the circuit board and the first chip and arranged to avoid the first welding pad and the second welding pad; the bonding layer comprises the following materials: a photo-lithographically-usable material comprising a dry film, a dielectric material comprising silicon oxide or silicon nitride, or glass.

19. The board level system in package structure of claim 17, wherein the first and second opposing pads comprise opposing portions and staggered portions, the opposing portions having an area greater than one-half of the area of the first pad or the second pad.

20. The board-level system-in-package structure of claim 16, wherein the height of the first void is 5 μ ι η to 200 μ ι η.

21. The board-level system-in-package structure of claim 17, wherein the circuit board has a first surface and a second surface opposite to each other, and the first pads are located on one side of the first surface and recessed in the first surface;

the circuit board further comprises a third welding pad, the third welding pad is positioned on one side of the second surface and is recessed in the second surface:

the board-level system-in-package structure further comprises: and the electroplated second conductive bump is positioned on the third bonding pad.

Or the first chip is bonded to the first surface and the second surface respectively, and the third bonding pad and the second bonding pad relatively enclose the second gap;

a fourth conductive bump is formed in the second gap and electrically connected to the second pad and the third pad.

22. The board-level system-in-package structure of claim 21, wherein a first organic dielectric layer or a first inorganic dielectric layer is formed on the first surface, and the first pad is embedded in the first organic dielectric layer or the first inorganic dielectric layer;

23. The board-level system-in-package structure of claim 17, wherein the cavity is located in a partial thickness of the circuit board;

or the cavity is positioned in the circuit board with partial thickness, and a plurality of air holes penetrating through the thickness are formed in the circuit board at the bottom of the cavity.

24. The board-level system-in-package structure of claim 17, wherein the circuit board has first and second opposing surfaces;

the cavity is located in a portion of the thickness of the circuit board, and the cavity is located in either or both of the first and second surfaces.

25. The board level system in package structure of claim 17, wherein the first chip has a third surface and a fourth surface opposite to each other, the second pad is located on one side of the third surface and recessed in the third surface, the first chip further comprises a fourth pad located on one side of the fourth surface and recessed in the fourth surface, and an electrical connection is formed between the fourth pad and the second pad;

the board-level system-in-package structure further comprises: the second chip is bonded on the first chip, a fifth welding pad is formed on any surface of the second chip, the fifth welding pad is sunken on the surface of the second chip, and a third gap is formed by the fifth welding pad and the fourth welding pad in an opposite surrounding manner; and the third electroplated conductive bump is positioned in the third gap, and the third conductive bump is electrically connected with the fourth welding pad and the fifth welding pad.

26. The board-level system-in-package structure of claim 17, wherein a plurality of sixth pads are further formed on the surface of the circuit board outside the first cavity, and the sixth pads are recessed in the surface of the circuit board;

the board-level system-in-package structure further comprises: the interconnection chip is bonded on the circuit board at the side part of the first chip, a conductive structure is formed in the interconnection chip, one surface of the interconnection chip is exposed to a part of the conductive structure, and the conductive structure of the interconnection chip and the sixth welding pad oppositely enclose a fourth gap; a fifth electroplated conductive bump in the fourth void, the fifth conductive bump electrically connecting the sixth bonding pad and the conductive structure of the interconnect die;

the interconnection chip is electrically connected with the circuit board, or the interconnection chip is electrically connected with the first chip through the circuit board.