CN114664857A - Three-dimensional memory, preparation method thereof, storage system and electronic equipment - Google Patents

Abstract

The invention provides a three-dimensional memory and a preparation method thereof, a storage system and electronic equipment, relates to the technical field of semiconductor chips, and aims to solve the problem that a grid line layer positioned at a high level is easy to penetrate through and improve the electrical property and yield of the three-dimensional memory. The three-dimensional memory includes a stacked structure, a plurality of first stops, a barrier layer, a protective layer, and a plurality of contact pillars. The stack structure includes a step structure including a plurality of step structures arranged in a first direction and having different heights in a second direction. The first plurality of stops are located on a plurality of steps of the at least one stair step structure. The barrier layer covers the step structure and is located between the step structure and the first stopping portion. The protective layer covers the barrier layer and the first stopping portion, and at least part of the protective layer is located between the barrier layer and the first stopping portion. The contact pillar is connected with the gate layer in the step corresponding to the first stop portion. The three-dimensional memory is applied to a storage system to realize reading and writing operations of data.

Description

Three-dimensional memory, preparation method thereof, storage system and electronic equipment

Technical Field

The disclosure relates to the technical field of semiconductor chips, and in particular to a three-dimensional memory, a manufacturing method thereof, a storage system and electronic equipment.

Background

As the feature size of memory cells approaches the lower process limit, planar processes and fabrication techniques become challenging and costly, which causes the storage density of 2D or planar NAND flash memories to approach the upper limit. To overcome the limitations imposed by 2D or planar NAND flash memories, memories having a three-dimensional structure (3D NAND) have been developed to increase the storage density by arranging memory cells three-dimensionally over a substrate.

In the actual manufacturing process of the three-dimensional memory, in order to realize the electrical connection between the contact portion and the gate electrode layer in the stacked structure, it is necessary to etch a contact hole of each gate electrode layer exposing the step region in the dielectric layer covering the stacked structure, and then fill a conductive material in the contact hole to form the contact portion.

However, as the integration degree of the three-dimensional memory is increased and the number of stacked layers is increased, the depth of the contact hole is increasingly increased, and the gate layer located at a higher layer is easily etched through in the process of forming the contact hole. In this case, after the contact hole is filled with a conductive material for forming a contact portion, a short circuit between different gate layers (i.e., a word line electrical connection between different layers) may be caused, thereby causing a failure of the memory device.

Disclosure of Invention

The embodiment of the disclosure provides a three-dimensional memory, a preparation method of the three-dimensional memory, a storage system and electronic equipment.

The embodiment of the disclosure adopts the following technical scheme:

in one aspect, a three-dimensional memory is provided. The semiconductor structure includes a stacked structure, a plurality of first stoppers disposed along the first direction, a barrier layer, a protective layer, and a plurality of contact pillars.

The stack structure comprises gate layers and dielectric layers which are alternately arranged; the stacked structure includes a stepped structure including a plurality of stepped structures arranged in a first direction and having different heights in a second direction; the stair step structure comprises a plurality of steps; the first direction and the second direction are perpendicular to each other. And a plurality of first stopping portions arranged along the first direction and positioned on a plurality of steps of at least one stepped structure, wherein each first stopping portion is arranged on one step.

And the barrier layer covers the step structure and is positioned between the step structure and the first stopping part. A protective layer covering the barrier layer and the first stop portion. The contact pillar penetrates through the protective layer, the first stopping portion and the blocking layer and is connected with the gate layer in the step corresponding to the first stopping portion.

In some embodiments, the three-dimensional memory further comprises an isolation structure extending along the first direction and through the stacked structure; the isolation structure divides the stacked structure into a plurality of memory blocks, each memory block including the step structure; and the stepped structure where the first stopping part is located and the isolation structure are arranged at intervals.

In some embodiments, the memory block includes a first step structure, a second step structure, and a third step structure along the second direction, and the first stop portion is disposed on a plurality of steps of the second step structure.

In some embodiments, the storage block includes a first step structure and a second step structure along the second direction, the first step structure is spaced apart from the isolation structure, and the first stop portion is disposed on a plurality of steps of the first step structure.

In some embodiments, each memory block further comprises a sidewall; the isolation structure comprises a first isolation structure and a second isolation structure; along the second direction, the first isolation structure is located between two adjacent side walls, and the second isolation structure is located between two adjacent step structures; and along the second direction, the step structures in the two storage blocks adjacent to the second isolation structure are symmetrically arranged.

In some embodiments, the height of the plurality of stair-step structures in the memory block gradually decreases along the second direction and from the first isolation structure toward the second isolation structure.

In some embodiments, the height of two step structures adjacent to two sides of the second isolation structure along the second direction is the same.

In some embodiments, the three-dimensional memory further comprises a plurality of second stops disposed along the first direction. And a plurality of second stop portions provided along the first direction on a plurality of steps of the other step structure except the step structure provided with the first stop portion. Wherein the barrier layer is further located between the step structure and the second stopper, and the protective layer further covers the second stopper.

In some embodiments, the three-dimensional memory further includes a plurality of gate line isolation structures extending along the first direction, the gate line isolation structures being located between two adjacent isolation structures, the gate line isolation structures penetrating the second stopper and the stacked structure; along the first direction, each grid line isolation structure comprises a plurality of sub-isolation structures which are separated from each other.

In some embodiments, a thickness of the second stop is less than or equal to a thickness of the gate layer; the material of the second stopper is the same as that of the gate layer.

In some embodiments, the thickness of the second stop is greater than the thickness of the gate layer; the second stopper is made of the same material as the gate line isolation structure.

In some embodiments, the material of the second stop is the same as the material of the first stop.

In some embodiments, the material of the second stop is carbon-doped silicon oxide.

In some embodiments, the material of the first stop comprises silicon nitride.

In another aspect, a method for manufacturing a three-dimensional memory is provided, including:

forming an initial stacked structure; the initial stacking structure comprises sacrificial layers and dielectric layers which are alternately arranged; the initial stacking structure comprises a step structure, and the step structure comprises a plurality of step structures which are arranged along a first direction and have different heights along a second direction; the stair step structure comprises a plurality of steps; the first direction and the second direction are perpendicular to each other.

And forming a barrier layer covering the step structure.

Forming a plurality of first stops on one side of the barrier layer far away from the step structure; the plurality of first stopping portions are arranged along the first direction and are positioned on a plurality of steps of at least one stepped structure, and each first stopping portion is arranged on one step.

Forming a protective layer; the protective layer covers the barrier layer and the first stopper.

And replacing the sacrificial layer with a gate layer to form a stacked structure.

Forming a plurality of contact pillars penetrating the protection layer, the first stopper, and the barrier layer, and electrically connected to the gate layer in the step corresponding to the first stopper.

In some embodiments, forming a plurality of first stops on a side of the barrier layer away from the step structure comprises: forming a preset stop layer on one side of the barrier layer, which is far away from the step structure; and removing the part of the preset stop layer corresponding to the connection part of the steps to form a plurality of first stop parts.

In some embodiments, the method of making further comprises: forming a first isolation groove extending along a first direction and penetrating through the initial stacking structure, wherein the first isolation groove divides the initial stacking structure into a plurality of initial storage blocks, and each initial storage block comprises the step structure; and forming an isolation structure in the first isolation groove.

In some embodiments, the method of making further comprises: forming a second isolated sub-portion extending along the first direction and penetrating the initial stacked structure; forming a first sub-isolation groove, a second sub-isolation groove and a second isolation groove which extend along a first direction and penetrate through the initial stacking structure; along the first direction, the first sub-partition groove and the second sub-partition groove are respectively contacted with two ends of the second isolating sub-portion; the second isolation sub-portions are arranged in the first direction and the second direction; forming a first isolated sub-part in the first sub-groove, a third isolated sub-part in the second sub-groove, and a second isolated structure in the second sub-groove; wherein the first, third and second isolated subsections constitute at least part of a first isolation structure.

In some embodiments, the method of making further comprises: forming a plurality of second stops on one side of the barrier layer far away from the step structure; the plurality of second stopping portions are arranged along the first direction, and the plurality of second stopping portions are positioned on a plurality of steps of the other step structures except the step structure provided with the first stopping portion; each second stop is located on one of the steps.

In some embodiments, the method of making further comprises: forming a plurality of third separation grooves extending along the first direction; the third separating groove penetrates through the second stopping part and the initial stacking structure; each of the third slots comprises a plurality of third sub-slots separated from each other along the first direction; and forming a grid line isolation structure in the third separation groove.

In some embodiments, the forming a plurality of contact pillars comprises: etching the protective layer to the first stop part to form a plurality of contact holes; etching the first stop part exposed by the contact hole, and the barrier layer and the dielectric layer below the first stop part to expose the gate layer from the contact hole; and forming a contact pillar in the contact hole.

In yet another aspect, a storage system is provided. The storage system includes: a controller, and the three-dimensional memory of any of the above embodiments; the controller is coupled to the three-dimensional memory and is used for controlling the three-dimensional memory to store data.

In yet another aspect, an electronic device is provided. The electronic device includes: the storage system of any of the above embodiments.

Drawings

In order to more clearly illustrate the technical solutions in the present disclosure, the drawings needed to be used in some embodiments of the present disclosure will be briefly described below, and it is apparent that the drawings in the following description are only drawings of some embodiments of the present disclosure, and other drawings can be obtained by those skilled in the art according to the drawings. Furthermore, the drawings in the following description may be regarded as schematic diagrams, and do not limit the actual size of products, the actual flow of methods, the actual timing of signals, and the like, involved in the embodiments of the present disclosure.

FIG. 1 is a perspective block diagram of a three-dimensional memory according to some embodiments;

fig. 2 is a structural view of a contact pillar and a step in the related art;

fig. 3 is another structural view of a contact pillar and a step in the related art;

FIG. 4 is a block diagram of a contact stud according to some embodiments;

FIG. 5A is a top view of a three-dimensional memory according to some embodiments;

FIG. 5B is a top view of a three-dimensional memory according to some embodiments;

FIG. 6 is an enlarged view of the region CC in FIG. 5A;

FIG. 7A is a cross-sectional view taken along section line D-D' of FIG. 6;

FIG. 7B is another cross-sectional view taken along section line D-D' of FIG. 6;

FIG. 8 is a cross-sectional view taken along section line E-E' of FIG. 6;

FIG. 9 is another cross-sectional view taken along section line E-E' of FIG. 6;

FIG. 10 is another enlarged view of the region CC in FIG. 5A;

FIG. 11 is a cross-sectional view taken along section line F-F' of FIG. 10;

FIG. 12A is a block diagram of a stepped structure according to some embodiments;

FIG. 12B is a block diagram of another stepped structure according to some embodiments;

FIG. 13 is a further enlarged view of the CC region of FIG. 5A;

FIG. 14 is a further enlarged view of the region CC in FIG. 5A;

FIG. 15 is a cross-sectional view taken along section line G-G' of FIG. 14;

FIG. 16 is a block diagram of a memory string according to some embodiments;

FIG. 17 is an equivalent circuit diagram of the memory string of FIG. 16;

FIG. 18 is a further enlarged view of the region CC in FIG. 5A;

FIG. 19A is a cross-sectional view taken along section line H-H' of FIG. 18;

FIG. 19B is another cross-sectional view taken along section line H-H' of FIG. 18;

FIG. 20 is a cross-sectional view taken along section line I-I' of FIG. 18;

FIG. 21 is another cross-sectional view taken along section line I-I' of FIG. 18;

FIG. 22 is a further enlarged view of the region CC in FIG. 5A;

FIG. 23 is a cross-sectional view taken along section line J-J' of FIG. 22;

FIG. 24A is a block diagram of yet another stepped structure according to some embodiments;

FIG. 24B is a block diagram of yet another stepped structure according to some embodiments;

FIG. 25 is a further enlarged view of the region CC in FIG. 5A;

FIG. 26 is a further enlarged view of the region CC in FIG. 5A;

FIG. 27 is a cross-sectional view taken along section line K-K' of FIG. 26;

fig. 28, 31, 32, 37, 40, 47, 49, 52, and 54 are flowcharts of a method of fabricating a three-dimensional memory according to some embodiments;

fig. 29A to 30, 33A to 36, 38 to 39, 41A to 46, 48, 50 to 51, 53, 55 to 58 are step diagrams of a method for manufacturing a three-dimensional memory according to some embodiments;

fig. 59, 66, 72, 74, 77-78, 80 are flow diagrams of another method of fabricating a three-dimensional memory according to some embodiments;

fig. 60 to 65, 67 to 71, 73, 75 to 76, 79 and 81 to 84 are step diagrams of another method of manufacturing a three-dimensional memory according to some embodiments;

FIG. 85 is a block diagram of another three-dimensional memory according to some embodiments;

FIG. 86 is a block diagram of yet another three-dimensional memory according to some embodiments;

FIG. 87 is a block diagram of a memory system according to some embodiments;

FIG. 88 is a block diagram of yet another memory system according to some embodiments.

Detailed Description

Technical solutions in some embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings, and it is obvious that the described embodiments are only a part of the embodiments of the present disclosure, and not all of the embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments provided by the present disclosure belong to the protection scope of the present disclosure.

In the description of the present disclosure, it is to be understood that the terms "center", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like indicate orientations or positional relationships based on those shown in the drawings, and are only for convenience in describing and simplifying the disclosure, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed in a specific orientation, and be operated, and thus, should not be construed as limiting the disclosure.

Throughout the specification and claims, the term "comprising" is to be interpreted in an open, inclusive sense, i.e., as "including, but not limited to," unless the context requires otherwise. In the description herein, the terms "one embodiment," "some embodiments," "an example embodiment," "exemplary" or "some examples" or the like are intended to mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the disclosure. The schematic representations of the terms used above are not necessarily referring to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be included in any suitable manner in any one or more embodiments or examples.

In the following, the terms "first", "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the embodiments of the present disclosure, "a plurality" means two or more unless otherwise specified.

In describing some embodiments, expressions of "coupled" and "connected," along with their derivatives, may be used. For example, the term "connected" may be used in describing some embodiments to indicate that two or more elements are in direct physical or electrical contact with each other. As another example, some embodiments may be described using the term "coupled" to indicate that two or more elements are in direct physical or electrical contact. The term "coupled," however, may also mean that two or more elements are not in direct contact with each other, but yet still co-operate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents herein.

"at least one of A, B and C" has the same meaning as "A, B or at least one of C", both including the following combination of A, B and C: a alone, B alone, C alone, a and B in combination, a and C in combination, B and C in combination, and A, B and C in combination.

"A and/or B" includes the following three combinations: a alone, B alone, and a combination of A and B.

As used herein, "about," "approximately," or "approximately" includes the stated values as well as average values that are within an acceptable range of deviation for the particular value, as determined by one of ordinary skill in the art in view of the measurement in question and the error associated with measurement of the particular quantity (i.e., the limitations of the measurement system).

In the context of this disclosure, the meaning of "on … …," above, "and" over "should be interpreted in the broadest manner such that" on.

Example embodiments are described herein with reference to cross-sectional and/or plan views as idealized example figures. In the drawings, the thickness of layers and regions are exaggerated for clarity. Variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, example embodiments should not be construed as limited to the shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the exemplary embodiments.

Referring to fig. 1 to 3, fig. 1 is a schematic perspective view illustrating a three-dimensional memory 100, and fig. 2 and 3 are two structural diagrams illustrating a portion of a contact pillar and a step in the related art.

In some embodiments, as shown in fig. 1, the three-dimensional memory 100 includes a stacked structure having a step structure and including a plurality of gate layers G and dielectric layers (not shown in fig. 1) alternately disposed. The gate layer G and the dielectric layer both extend along the first direction X. In the third direction Z, at least one lower gate layer G of the plurality of gate layers G is configured as a source select gate SGS, at least one upper gate layer G of the plurality of gate layers G is configured as a drain select gate SGD, and the gate layers G between the source select gate SGS and the drain select gate SGD are configured as a plurality of word lines WL.

The three-dimensional memory 100 further includes a plurality of contact pillars CNT therein in order to supply electrical signals to the source side select gate SGS, the drain side select gate SGD, and the word line WL. Among the plurality of contact pillars CNT, the contact pillar CNT electrically connected to the drain select gate SGD is configured as a drain select gate contact pillar SGD CNT, the contact pillar CNT electrically connected to the source select gate SGS is configured as a source select gate contact pillar SGS CNT, and the contact pillar CNT electrically connected to the word line WL is configured as a word line contact pillar WL CNT.

Referring to fig. 2, as the integration level is increased, the number of stacked layers of the gate layer G and the dielectric layer in the three-dimensional memory is gradually increased, and the depth difference of different contact pillars CNT in the third direction Z is gradually increased. Therefore, in the process of forming the plurality of contact pillars CNT, the high step is easily penetrated by the contact hole where the contact pillar CNT is located, so that after the plurality of contact pillars CNT are formed, a short circuit occurs between different gate layers G, and the failure of the three-dimensional memory is caused.

To address this problem, referring to fig. 3, in the related art, the thickness of the gate layer G at the step is increased to improve the problem that the gate layer G is easily penetrated during the manufacturing process of the contact pillar CNT. However, in order to prevent the contact hole from penetrating the gate layer G at the step, the gate layer G at the step needs to have a larger thickness, and thus the formation difficulty is higher.

Therefore, while the thickness of the gate layer G at the step is increased as much as possible, the related art also prevents the contact hole from penetrating the gate layer G at the step by reducing the etching rate. However, as shown in fig. 4, since the etching rate is slow and the etching directionality is poor, the contact hole obtained by etching has poor linearity and the contact pillar CNT has poor linearity. In the process of etching the contact hole, due to poor etching directionality, a dummy channel structure adjacent to the contact hole may be etched, so that after the contact pillar is formed, a conductive material is also filled in the dummy channel structure, a plurality of gate electrode layers are short-circuited with one another, and the three-dimensional memory is poor.

In addition, when the thickness of the gate layer G at the step is large, a conductive material may remain in the gate line isolation groove during the replacement of the gate layer by using the gate line isolation groove, so that after the replacement of the gate layer is completed, a short circuit between multiple gate layers is caused, and the failure of the three-dimensional memory is caused.

To solve at least one of the above problems, referring to fig. 5A to 8, some embodiments of the present disclosure provide a three-dimensional memory 200.

As shown in fig. 5A and 5B, the three-dimensional memory 200 includes a core array area AA and a step area SS along a first direction X. As shown in fig. 5A, the three-dimensional memory 200 may include two core array areas AA and a step area SS between the two core array areas AA. Alternatively, as shown in fig. 5B, the three-dimensional memory 200 may include two step areas SS and a core array area AA, the core array area AA being located between the two step areas SS.

It is to be understood that the distribution of the core array area AA and the step area SS in the three-dimensional memory 200 provided by some embodiments of the present disclosure is not limited thereto.

Fig. 6 is an enlarged view of the region CC in fig. 5A. Fig. 7A and 7B are sectional views of fig. 6 at sectional lines D-D ', and fig. 8 is a sectional view of fig. 6 at sectional lines E-E'.

Referring to fig. 6 to 8, the three-dimensional memory 200 includes a stacked structure 10, a plurality of first stoppers 20 disposed along a first direction X, a protective layer 30, and a plurality of contact pillars 40.

The stacked structure 10 includes gate layers 11 and dielectric layers 12 alternately disposed.

In some examples, referring to fig. 7A, the gate layer 11 may be a single layer structure. At this time, the gate layer 11 includes the conductive layer 111. Materials of conductive layer 111 include, but are not limited to, tungsten, cobalt, copper, aluminum, or doped crystalline silicon, doped silicon, and/or silicide.

In other examples, referring to fig. 7B, the gate layer 11 may be a multi-layer composite structure. At this time, the gate layer 11 may include the high dielectric constant layer 112, the metal compound layer 113, and the conductive layer 111 which are sequentially formed. The material of the high-k layer 112 may include, for example, aluminum oxide (AL)₂O₃) The material of the metal compound layer 113 may include tantalum nitride or titanium nitride, for example.

Illustratively, the dielectric layer 12 may be made of an insulating material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, or combinations thereof.

In the stacked structure 10, the thicknesses of the gate layers 11 may be substantially the same or different. The thicknesses of the dielectric layers 12 may be substantially the same or different. The thicknesses of the gate layers 11 and the dielectric layers 12 can be selected according to actual requirements. In addition, the number of stacked layers of the stacked structure 10 determines the number of memory cells; the more the number of stacked layers of the stacked structure 10, the higher the integration level, that is, the greater the number of memory cells. Specifically, the number of stacked layers and the stacking height of the stacked structure 10 may be designed according to actual storage requirements, which is not limited in this disclosure.

The stacked structure 10 includes a step structure 13, and the step structure 13 includes a plurality of step structures 14 arranged along a first direction X and having different heights along a second direction Y. The stepped structure 14 includes a plurality of steps 141. The first direction X and the second direction Y are perpendicular to each other.

It is understood that when the step structure 13 includes the step structures 14 arranged along the first direction X and having different heights along the second direction Y, the heights of two adjacent step structures 14 in the plurality of step structures 14 included in the step structure 13 are different, and the heights of two step structures 14 arranged at intervals may be the same.

In some examples, referring to fig. 6 and 8, the step structure 13 may include three step structures 14 having different heights disposed along the second direction Y.

In other examples, referring to fig. 6 and 9, the step structure 13 may include three step structures 14 arranged along the second direction Y, and the two step structures 14 at both sides have a different height from the step structure 14 at the middle, but the two step structures 14 at both sides have the same height.

In still other examples, referring to fig. 10 and 11, the step structure 13 may include two step structures 14 having different heights disposed along the second direction Y.

It is noted that the number of the stepped structures 14 in the present disclosure is not limited thereto.

The plurality of first stop portions 20 are disposed along the first direction X and on the plurality of steps 141 of the at least one stepped structure 14, and each first stop portion 20 is disposed on one step 141.

As shown in fig. 8, 9 and 11, the plurality of first stops 20 may be located on only the plurality of steps 141 of one stepped structure 14. The plurality of first stop portions 20 may be located on the plurality of steps 141 of the plurality of stepped structures 14.

As shown in fig. 8, the step 141 may include a gate layer 11 and a dielectric layer 12. Alternatively, the step 141 may include the multi-layered gate layer 11 and the multi-layered dielectric layer 12. The present disclosure is not so limited.

As shown in fig. 8, the protective layer 30 covers the step structure 13 and the first stop 20, and at least a portion of the protective layer 30 is located between the first stop 20 and a step 141 adjacent to the first stop 20.

It is understood that the "step 141 adjacent to the first stop portion 20" may include not only the step 141 adjacent to the first stop portion 20 in the first direction X as shown in fig. 7A, but also the step 141 adjacent to the first stop portion 20 in the second direction Y as shown in fig. 8.

Illustratively, the protective layer 30 may be made of silicon oxide, including but not limited to tetraethylorthosilicate (abbreviated TEOS), siloxane, silsesquioxane, and the like. Illustratively, the protective layer 30 may be formed by a Chemical Vapor Deposition (CVD) process, a spin coating process, or the like.

At least part of the protective layer 30 is arranged between the first stopping portion 20 and the step 141 adjacent to the first stopping portion 20, so that the sacrificial layer is spaced from the first stopping portion 20 by the protective layer 30 in the process of forming the gate layer 11, and the situation that the contact column penetrates through the replaced first stopping portion, the contact column is electrically connected with the multilayer gate layer and the three-dimensional memory fails due to the fact that the first stopping portion is replaced at the same time when the sacrificial layer is replaced by the gate layer is avoided.

The plurality of contact pillars 40 are connected to the gate layer 11 in the step corresponding to the first stopper 20, and the contact pillars 40 penetrate the protective layer 30 and the first stopper 20.

Illustratively, the contact post 40 may be made of a conductive material including, but not limited to, metals such as tungsten, copper, aluminum, etc., metal silicides, metal nitrides, and/or doped polysilicon.

It will be appreciated that the above-described step structure 13 is located within the step zone SS. When the step region SS is located between the two core array regions AA, the topography of the step structure 13 can be as shown in fig. 12A and 12B. That is, along the first direction X, the step structure 13 may include at least one step group, and the heights of the plurality of steps 141 in the step group gradually increase or gradually decrease

Illustratively, as shown in fig. 12A and 12B, the step structure 13 may include 8 step groups, which are a first step group 131, a second step group 132, a third step group 133, a fourth step group 134, a fifth step group 135, a sixth step group 136, a seventh step group 137, and an eighth step group 138 in sequence along the first direction X. Wherein the heights of the plurality of steps 141 of the first, third, fifth and seventh step groups 131, 133, 135 and 137 are gradually decreased along the first direction X. The heights of the plurality of steps 141 in the second, fourth, sixth, and eighth step groups 132, 134, 136, and 138 are gradually increased along the first direction X. Of course, the form of the step structure 13 in the present disclosure is not limited thereto.

In the three-dimensional memory 200 provided in some embodiments of the present disclosure, the plurality of first stop portions 20 are disposed on the at least one step structure 14 of the step structure 13, so that when forming the contact hole 41 where the contact pillar 40 is located, a portion of the protective layer on the first stop portion 20 may be removed by an etching process (e.g., wet etching) to expose a portion of the first stop portion 20, and then the exposed portion of the first stop portion 20, the dielectric layer 12 between the first stop portion 20 and the underlying gate layer 11 may be removed by the etching process to expose a portion of the gate layer 11.

In the first etching process, due to the existence of the first stop portion 20, the contact holes 41 corresponding to different depths of the steps 141 with different heights can be stopped on the first stop portion 20 on the step 141. In the second etching process, since the distances from the first stop portions 20 to the gate layer 11 of the step 141 where the first stop portions 20 are located are substantially the same, the contact holes 41 corresponding to different depths of the step 141 with different heights can be stopped on the gate layer 11 of the step 141 with the same etching time in the second etching process.

Like this, when forming contact post 40 in contact hole 41, contact post 40 all can with the gate layer 11 contact that corresponds step 141 to be favorable to avoiding because of the increase of the rete quantity in the stack structure, the contact post runs through the multilayer gate layer, makes the condition of short circuit take place between the multilayer gate layer, has improved the electrical property and the yield of three-dimensional memory.

Meanwhile, due to the arrangement of the first stop portion 20, when the contact hole where the contact pillar is located is formed through an etching process, the etching speed can be high, so that the straightness of the contact hole 41 (or the contact pillar 40) is good, the dielectric layer in the virtual channel structure adjacent to the contact pillar 40 is not easy to etch, and the yield of the three-dimensional memory 200 is improved.

Referring to fig. 6-12B, in some embodiments, the three-dimensional memory 200 further includes an isolation structure 50. The isolation structure 50 extends along the first direction X and penetrates the stacked structure 10. The isolation structure 50 divides the stacked structure 10 into a plurality of memory blocks 15. Each memory block 15 comprises a step structure 13. The step structure 14 where the first stop portion 20 is located is spaced apart from the isolation structure 50.

Here, the "stepped structure 14 in which the first stop portion 20 is located is provided at a distance from the partition structure 50", that is, the plurality of first stop portions 20 are provided at a distance from the partition structure 50.

In some embodiments of the present disclosure, the stacked structure 10 is divided into a plurality of memory blocks 15 by using the isolation structure 50, so that the storage density of the three-dimensional memory 200 can be further improved. Meanwhile, the stepped structure 14 where the first stop portion 20 is located and the isolation structure 50 are arranged at intervals, so that the situation that the contact column penetrates through the replaced first stop portion and is electrically connected with a multilayer gate layer to cause failure of the three-dimensional memory due to the fact that the first stop portion 20 is replaced in the subsequent process of forming the gate layer 11 by utilizing the isolation groove where the isolation structure 50 is located to replace the gate can be avoided.

It should be noted that, while the isolation structure 50 divides the stacked structure 10 into a plurality of memory blocks 15, the isolation structure 50 also divides the gate layer 11 into a plurality of gate lines (e.g., source-side select gates or drain-side select gates or word lines). Each memory block 15 includes a plurality of gate lines arranged at intervals in the third direction Z.

For example, the first direction X may be an extending direction of the gate line. The second direction Y may be an extending direction of the bit line. The third direction Z may be a stacking direction of the stacked structure 10.

In some examples, referring to fig. 6, 8 and 9, in the second direction Y, the memory block 15 includes a first stepped structure 14A, a second stepped structure 14B and a third stepped structure 14C, and the first stopper 20 is provided on a plurality of steps 141 of the second stepped structure 14B.

In this way, the second step structure 14B, the first step structure 14A, and the third step structure 14C have height differences in the third direction Z, and are disposed at intervals from the isolation structure 50 (i.e., the first step structure 14A and the third step structure 14C exist between the second step structure 14B and the isolation structure 20), so as to be beneficial to forming the first stopping portion 20 in subsequent etching steps, so that a gap exists between the first stopping portion 20 and the adjacent step 141, and the first stopping portion is prevented from being replaced.

In other examples, referring to fig. 11, along the second direction Y, the memory block 15 includes a first stepped structure 14A and a second stepped structure 14B, the first stepped structure 14A is disposed at a distance from the isolation structure 50, and the first stop portion 20 is disposed on the plurality of steps 141 of the first stepped structure 14A.

In this way, the first step structure 14A and the second step structure 14B have a height difference in the third direction Z and are spaced from the isolation structure 50, so that the first stop portion 20 is formed in the subsequent etching step, and a space is formed between the first stop portion 20 and the sidewall of the adjacent step 141, thereby preventing the first stop portion 20 from being replaced.

In some embodiments, referring to fig. 6-11, each memory block 15 further includes a sidewall 16. The isolation structure 50 includes a first isolation structure 51 and a second isolation structure 52. Along the second direction Y, the first isolation structure 51 is located between two adjacent side walls 16, and the second isolation structure 52 is located between two adjacent step structures 13. The sidewall 16 is configured to improve the structural stability of the three-dimensional memory 200.

In some examples, as shown in fig. 6 and 10, the first isolation structure 51 may be a unitary structure, that is, when the first isolation structure 51 is prepared, an isolation groove where the first isolation structure 51 is located may be obtained by etching through one etching process, and the first isolation structure 51 is formed in the isolation groove.

In other examples, as shown in fig. 13, the first isolation structure 51 may include a first isolation sub-portion 511, a second isolation sub-portion 512, and a third isolation sub-portion 513 sequentially connected in the first direction X. The size of the second partition sub-portion 512 in the second direction Y is greater than the size of the first partition sub-portion 511 in the second direction Y, and the size of the second partition sub-portion 512 in the second direction Y is greater than the size of the third partition sub-portion 513 in the second direction Y.

Illustratively, the size of the first partition sub-portion 511 in the second direction Y is substantially the same as the size of the third partition sub-portion 513 in the second direction Y.

Illustratively, the first and third insulating subsections 511 and 513 are located in the core array region AA, the second insulating subsection 512 is located in the step region SS, and the second insulating subsection 512 is in contact with the sidewall 16.

For example, the second isolating sub-portion 512 may be simultaneously prepared with the dummy channel structure and the channel structure. The first and third insulating subsections 511 and 513 may be prepared after the channel structure is prepared. Based on this, the material of the second isolation sub-portion 512 may be the same as that of the dummy channel structure or the channel structure.

By providing the second partition sub-portion 512 in some embodiments of the present disclosure, the present disclosure can be used to divide two adjacent storage blocks 15, and can also be used to support the stacked structure 10, so as to prevent the stacked structure 10 from collapsing.

In some embodiments, referring to fig. 6, 10 and 13, the step structures 13 in the two memory blocks 15 adjacent to the second isolation structure 52 are symmetrically disposed along the second direction Y.

It is understood that "the step structures 13 in the two memory blocks 15 are symmetrically arranged" may be, for example, that the step structures 13 of the two memory blocks 15 include the same number of step structures 14, and the two step structures 14 of the two step structures 13 having the same distance to the second isolation structure 52 have the same height.

In some embodiments, referring to fig. 8 and 11, the heights of the plurality of step structures 14 in the memory block 15 gradually decrease along the second direction Y from the first isolation structure 51 toward the second isolation structure 52.

In other embodiments, referring to fig. 9, along the second direction Y and from the first isolation structure 51 toward the second isolation structure 52, the heights of the plurality of step structures 14 in the memory block 15 are first decreased and then increased.

In some embodiments, referring to fig. 8 and 9, along the second direction Y, the heights of two step structures 14 adjacent to both sides of the second isolation structure 52 are the same.

In some embodiments, referring to fig. 11, the three-dimensional memory 200 further includes a plurality of second stops 60 disposed along the first direction X. The plurality of second stops 60 are located on the plurality of steps 141 of the other stepped structures 14 than the stepped structure 14 provided with the first stop 20 among the plurality of stepped structures 14.

The protective layer 30 also covers the second stop portion 60, and at least a portion of the protective layer 30 is located between the second stop portion 60 and the step 141 adjacent to the second stop portion 60.

For example, referring to fig. 8 and 9, when the first stop 20 is located on the plurality of steps 141 of the second stepped structure 14B, the second stop 60 may be located on the plurality of steps 141 of the first and third stepped structures 14A and 14C.

For example, referring to fig. 11, when the first stop 20 is located on the plurality of steps 141 of the first stepped structure 14A, the second stop 60 may be located on the plurality of steps 141 of the second stepped structure 14B.

In some embodiments, the material of the first and second stops 20, 60 is the same. Illustratively, when the materials of the first and second stops 20 and 60 are the same, the materials of the first and second stops 20 and 60 may include silicon carbonitride doped, for example. Alternatively, for example, when the materials of the first and second stops 20 and 60 are the same, the materials of the first and second stops 20 and 60 may be, for example, silicon nitride.

Illustratively, the material of the first stopper 20 may be silicon nitride.

Thus, the material of the first stop portion 20 is different from the material of the gate layer 11, and the etching selection ratio of the first stop portion 20 is different from the etching selection ratio of the gate layer 11, so that the first stop portion 20 is not easily etched through when a contact hole is formed by etching using an etching process. Therefore, when the contact hole 41 where the contact pillar 40 is located is prepared, the plurality of contact holes 41 corresponding to the steps 141 with different heights are all stopped on the first stopping portion 20, the distance between the bottom of each contact hole 41 and the step 141 is substantially the same, and then the etching process is used to etch the first stopping portion 20 exposed by the plurality of contact holes 41 and the dielectric layer 12 below the first stopping portion 20, so that the contact hole 41 exposes the gate layer 11 in the step 141 corresponding to the contact hole 41. Therefore, the problem that after the contact hole penetrates through the upper step and the contact column is formed by filling the conductive material in the contact hole, short circuit occurs between the grid electrode layers in the adjacent upper steps is solved, and the electrical property and the yield of the three-dimensional memory are improved.

In some embodiments, as shown in fig. 14 and 15, the three-dimensional memory 200 further includes a plurality of gate line isolation structures 70 extending along the first direction X between two adjacent isolation structures 50, wherein the gate line isolation structures 70 penetrate the second stop 60 and the stacked structure 10 therebelow. Along the first direction X, each gate line isolation structure 70 includes a plurality of sub-isolation structures 71 separated from each other. The material of the second stop portion 60 is the same as that of the gate layer 11.

The "gate line isolation structure 70 penetrates through the second stopping portion 60 and the stacked structure 10 therebelow", that is, the isolation groove where the gate line isolation structure 70 is located penetrates through the second stopping portion 60 and the stacked structure 10 therebelow, so that the gate can be replaced by using the isolation groove where the gate line isolation structure 70 is located, and the sacrificial layer in the initial stacked structure 101 is replaced by the gate layer 11. Meanwhile, the material of the second stop portion is replaced with the material of the gate layer by the isolation groove in which the gate line isolation structure 70 is located.

The gate line isolation structure 70 can also be used to relieve stress for the three-dimensional memory 200 by being provided.

In some examples, the second stop portion 60 may be the same as the gate layer 11, being a single-layer structure. At this time, the second stop portion 60 also includes the conductive layer 111. Materials of conductive layer 111 include, but are not limited to, tungsten, cobalt, copper, aluminum, or doped crystalline silicon, doped silicon, and/or silicide

In other examples, the second stop 60 may be the same as the gate layer 11, being a composite multilayer structure. At this time, the second stop portion 60 may include the high dielectric constant layer 112, the metallic compound layer 113, and the conductive layer 111, and the high dielectric constant layer 112 wraps the conductive layer 111 with the metallic compound layer 113 between the high dielectric constant layer 112 and the conductive layer 111. The material of the high-k layer 112 may include aluminum oxide (AL), for example₂O₃) The material of the metal compound layer 113 may include tantalum nitride or titanium nitride, for example.

In some embodiments, referring to fig. 8, 9, 11, and 15, the thickness of the first stopper 20 is the same as the thickness of the gate layer 11 of the previous step 141 in the third direction Z. The previous step 141 is adjacent to the step 141 corresponding to the first stop portion 20 and is higher than the step 141 corresponding to the first stop portion 20.

In this case, the first stop portion 20 may be formed by using a sacrificial layer of the gate layer 11 formed with the previous step 141, so that the first stop portion 20 does not need to be separately deposited, and thus the fabrication process of the three-dimensional memory 200 may be simplified and the fabrication cost of the three-dimensional memory 200 may be reduced.

In some embodiments, the three-dimensional memory 200 includes a plurality of memory cell strings 201 distributed in an array within the core array area AA. Illustratively, referring to fig. 16, along the third direction Z, the memory cell string 201 includes a ground selection line layer 202 (bottom selection gate), a word line layer 203, a string selection line layer 204 (top selection gate), and a bit line 205, which are sequentially disposed. Memory cell string 201 also includes an array of channel structures 206 that extend through string select line layer 204, word line layer 203, and ground select line layer 202 along third direction Z. A channel structure 206 connects the string select line layer 204, the word line layer 203, and the ground select line layer 202 in series to form a memory cell string 201.

In some embodiments, referring to fig. 16, the channel structure 206 may include a blocking layer 2061, a storage layer 2062, a tunneling layer 2063, a channel layer 2064, and a fill layer 2065, which are sequentially disposed.

Illustratively, the barrier layer 2061 may comprise a layer, for example, the barrier layer 2061 comprises silicon dioxide (SiO)₂) A layer; the barrier layer 2061 may also comprise multiple layers, for example, the barrier layer 2061 comprises silicon dioxide and aluminum oxide (Al)₂O₃) And (5) laminating. The storage layer 2062 may include one layer, for example, the storage layer 2062 includes a silicon nitride (SiN) layer; the memory layer 2062 may also include multiple layers, for example, the memory layer 2062 includes a silicon nitride, a silicon oxynitride (SiON), a silicon nitride stack. The tunneling layer 2063 may comprise multiple layers, for example, the tunneling layer 2063 comprises a silicon monoxide (SiO), silicon oxynitride, silicon oxide stack. The material of the channel layer 2064 may include a semiconductor material, for example, polysilicon and/or single crystal silicon. The material of the fill layer 2065 may comprise an insulating material, such as silicon dioxide.

Referring to fig. 17, a first terminal of a memory cell string 201 is connected to a bit line 205, and a second terminal is connected to a source line SL. The memory cell string 201 includes a plurality of transistors connected in series between a first terminal and a second terminal, the plurality of transistors including at least one top select transistor Q1, at least one memory transistor M, and at least one bottom select transistor Q2. Illustratively, one top select transistor Q1, four memory transistors M, and one bottom select transistor Q2 are shown in fig. 17. The four memory transistors M are M1, M2, M3 and M4 respectively.

Referring to fig. 5A, 5B, and 18-21, another three-dimensional memory 300 is provided in other embodiments of the present disclosure.

Similarly, as shown in fig. 5A and 5B, the three-dimensional memory 300 includes a core array area AA and a step area SS along the first direction X. As shown in fig. 5A, the three-dimensional memory 300 may include two core array areas AA and a step area SS between the two core array areas AA. Alternatively, as shown in fig. 5B, the three-dimensional memory 300 may include two step areas SS and a core array area AA, and the core array area AA is located between the two step areas SS.

It is to be understood that the distribution of the core array area AA and the step area SS in the three-dimensional memory 300 according to some embodiments of the disclosure is not limited thereto.

As shown in fig. 18, the three-dimensional memory 300 includes a stacked structure 10 ', a plurality of first stoppers 20 ' disposed along a first direction X, a barrier layer 30 ', a protective layer 40 ', and a plurality of contact pillars 50 '.

The stacked structure 10 ' includes gate layers 11 ' and dielectric layers 12 ' alternately disposed.

In some examples, as shown in fig. 19A, the gate layer 11' may be a single-layer structure. At this time, the gate layer 11 'includes the conductive layer 111'. Materials of the conductive layer 111' include, but are not limited to, tungsten, cobalt, copper, aluminum, or doped crystalline silicon, doped silicon, and/or silicide.

In other examples, as shown in fig. 19B, the gate layer 11' may be a multi-layer composite structure. At this time, the gate layer 11 'may include the high dielectric constant layer 112', the metal compound layer 113 ', and the conductive layer 111' which are sequentially formed. Wherein, the material of the high dielectric constant layer 112' may include alumina AL, for example₂O₃The material of the metal compound layer 113' may include tantalum nitride or titanium nitride, for example.

Illustratively, the dielectric layer 12' may be made of an insulating material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, or combinations thereof.

In the stacked structure 10 ', the thicknesses of the gate layers 11' may be substantially the same or different; the thicknesses of the dielectric layers 12' may be substantially the same or different. The thicknesses of the gate layers 11 'and the dielectric layers 12' can be selected according to actual requirements. In addition, the number of stacked structures of the stacked structure 10' determines the number of memory cells; the more the number of stacked structures of the stacked structure 10', the higher the integration level, i.e., the greater the number of memory cells. The number and height of the stacked structures 10' may be designed according to actual storage requirements, which is not specifically limited by the present disclosure.

The stacked structure 10 'includes a step structure 13', and the step structure 13 'includes a plurality of step structures 14' disposed along the first direction X and having different heights along the second direction Y. The stepped structure 14 'includes a plurality of steps 141'. The first direction X and the second direction Y are perpendicular to each other.

It is understood that, when the step structure 13 'includes the step structures 14' arranged along the first direction X and having different heights along the second direction Y, the heights of the two step structures 14 'arranged at intervals may be the same as long as the heights of two adjacent step structures 14' in the plurality of step structures 14 'included in the step structure 13' are different.

Based on this, in some examples, referring to fig. 20, the stepped structure 13 'may include three stepped structures 14' having different heights disposed along the second direction Y.

In other examples, referring to fig. 21, the step structure 13 'may include three step structures 14' arranged along the second direction Y, and the two step structures 14 'at both sides have a different height from the step structure at the middle, but the two step structures 14' at both sides have the same height.

In still other examples, referring to fig. 22 and 23, the step structure 13 'may include two step structures 14' having different heights disposed along the second direction Y.

It is noted that the number of step structures 14' in some embodiments of the present disclosure is not limited thereto.

A plurality of first stoppers 20 ' disposed in the first direction X are located on the plurality of steps 141 ' of the at least one stepped structure 14 ', and each first stopper 20 ' is disposed on one step 141 '.

As shown in fig. 20, 21 and 23, the plurality of first stops 20 ' may be located on only the plurality of steps 141 ' of one stepped structure 14 '. The plurality of first stop portions 20 ' may be located on the plurality of steps 141 ' of the plurality of stepped structures 14 '.

As shown in fig. 20, 21 and 23, the step 141 ' may include a gate layer 11 ' and a dielectric layer 12 '. Alternatively, the step 141 ' may include the multi-layered gate layer 11 ' and the multi-layered dielectric layer 12 '. The present disclosure is not so limited.

The barrier layer 30 'covers the step structure 13' and is located between the step structure 13 'and the first stopper 20'.

Illustratively, the barrier layer 30' may be made of an insulating material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, or combinations thereof.

It is understood that, as shown in fig. 20, 21 and 23, the "barrier layer 30 ' is located between the step structure 13 ' and the plurality of first stops 20 ', i.e., the barrier layer 30 ' is located between the first stop 20 ' and the step 141 ' of the step structure 13 ' in the third direction Z, and the barrier layer 30 ' is located between the first stop 20 ' and the step 141 ' adjacent to the first stop 20 ' in the first direction X and the second direction Y.

Some embodiments of the present disclosure can protect the step structure 13 ' and thus the stacked structure 10 ' by providing the barrier layer 30 ' on one hand. On the other hand, the gate layer 11 ' and the first stop portion 20 ' in the stepped structure 13 ' can be blocked, so that the situation that the first stop portion 20 ' is connected with the sacrificial layer and the first stop portion 20 ' is replaced when the gate layer 11 ' in the stepped structure 13 ' is formed can be avoided, and the situation that the gate layer 11 ' and the first stop portion 20 ' are electrically connected with each other to cause the failure of the three-dimensional memory 300 can be avoided.

The protective layer 40 ' covers the barrier layer 30 ' and the first stop 20 '.

Illustratively, the protective layer 40' may be made of silicon oxide, including but not limited to tetraethylorthosilicate (abbreviated TEOS), siloxane, silsesquioxane, and the like. Illustratively, the protective layer 40' may be formed by a Chemical Vapor Deposition (CVD) process, a spin coating process, or the like.

In some examples, referring to fig. 19A and 20, when the protective layer 40 ' covers the barrier layer 30 ' and the first stopper 20 ', at least a portion of the protective layer 40 ' is located between a sidewall of the first stopper 20 ' and the barrier layer 30 ' in the first direction X, and at least a portion of the protective layer 40 ' is located between a sidewall of the first stopper 20 ' and the barrier layer 30 ' in the second direction Y.

This is advantageous in that the plurality of first stop portions 20 'are separated from each other, and electrical connection between the plurality of first stop portions 20' is avoided.

The plurality of contact pillars 50 'and the contact pillars 50' penetrate the protective layer 40 ', the first stopper 20', and the barrier layer 30 'and are connected to the gate layer 11' in the step 141 'corresponding to the first stopper 20'.

Illustratively, the contact pillars 50' may be made of a conductive material including, but not limited to, metals such as tungsten, copper, aluminum, etc., metal silicides, metal nitrides, and/or doped polysilicon.

It will be appreciated that the above-described step structure 13' is located within the step region SS. When the step region SS is located between the two core array regions AA, the topography of the step structure 13' can be as shown in fig. 24A and 24B. That is, along the first direction X, the step structure 13 'may include at least one step group, and the heights of the plurality of steps 141' in the step group are gradually or gradually decreased.

For example, as shown in fig. 24A and 24B, along the first direction X, the step structure 13 ' may include 8 step groups, which are a first step group 131 ', a second step group 132 ', a third step group 133 ', a fourth step group 134 ', a fifth step group 135 ', a sixth step group 136 ', a seventh step group 137 ', and an eighth step group 138 ' in sequence. Wherein the heights of the plurality of steps 141 ' of the first step group 131 ', the third step group 133 ', the fifth step group 135 ' and the seventh step group 137 ' are gradually decreased along the first direction X. The heights of the plurality of steps 141 ' in the second step group 132 ', the fourth step group 134 ', the sixth step group 136 ', and the eighth step group 138 ' are gradually increased along the first direction X. Of course, the form of the step structure 13' in the present disclosure is not limited thereto.

In the three-dimensional memory 300 provided in some embodiments of the present disclosure, a plurality of first stops 20 ' are disposed on at least one step structure 14 ' of the step structure 13 ', so that when forming the contact hole 51 ' where the contact pillar 50 ' is located, a portion of the protection layer on the first stop 20 ' may be removed by an etching process (e.g., wet etching) to expose a portion of the first stop 20 ', and then the exposed portion of the first stop 20 ', the barrier layer 30 ' and the dielectric layer 12 ' between the first stop 20 ' and the lower gate layer 11 ' may be removed by the etching process to expose a portion of the gate layer 11 '.

In the first etching process, due to the existence of the first stop portion 20 ', the contact holes 51 ' corresponding to different depths of the steps 141 ' with different heights may all stop on the first stop portion 20 ' on the step 141 '. In the second etching process, since the distances from the first stop portions 20 'to the gate layer 11' of the step 141 'where the first stop portions 20' are located are substantially the same, the contact holes 51 'corresponding to the steps 141' with different heights and different depths can be stopped on the gate layer 11 'of the step 141' in the same etching time.

Like this, when forming contact post 50 ' in contact hole 51 ', contact post 50 ' all can with the grid layer 11 ' contact that corresponds step 141 ' to be favorable to avoiding because of the increase of the rete quantity in the stacked structure, the contact post runs through the multilayer grid layer, makes the condition of short circuit take place between the multilayer grid layer, has improved the electrical property and the yield of three-dimensional memory.

Meanwhile, the first stop portion 20 'can also increase the etching rate of the contact hole 51', and the linearity of the contact hole 51 '(or the contact post 50') is improved. Further, the dielectric layer in the dummy trench structure adjacent to the contact pillar 50' is not easily etched, and the yield of the three-dimensional memory 300 is improved.

Referring to fig. 18-23, in some embodiments, the three-dimensional memory 300 further includes an isolation structure 60'. The isolation structure 60 'extends along the first direction X and penetrates the stacked structure 10'. The isolation structure 60 ' divides the stacked structure 10 ' into a plurality of memory blocks 15 '. Each memory block 15 'comprises a step structure 13'. Wherein the stepped structure 14 ' where the first stop 20 ' is located is spaced apart from the spacer structure 60 '.

It is understood that the isolation structure 60 ' may also penetrate the barrier layer 30 ' while penetrating the stacked structure 10 '.

The step structure 14 ' where the first stop 20 ' is located is spaced apart from the separation structure 60 ', that is, the first stop 20 ' is spaced apart from the separation structure 60 '.

In some embodiments of the present disclosure, the stacked structure 10 ' is divided into a plurality of memory blocks 15 ' by using the isolation structure 60 ', so that the storage density of the three-dimensional memory 300 can be further improved. Meanwhile, the stepped structure 14 ' where the first stop portion 20 ' is located and the isolation structure 60 ' are arranged at intervals, so that the situation that the contact column penetrates through the replaced first stop portion and is electrically connected with a multi-layer gate layer to cause failure of the three-dimensional memory due to the fact that the first stop portion 20 ' is replaced in the process of forming the gate layer 11 ' by performing gate replacement by using an isolation groove where the isolation structure is located in the subsequent process can be avoided.

In some examples, referring to fig. 20 and 21, in the second direction Y, the memory block 15 ' includes a first stepped structure 14A ', a second stepped structure 14B ', and a third stepped structure 14C ', and the first stopper 20 ' is provided on the plurality of steps 141 ' of the second stepped structure 14B '.

In this way, the second step structure 14B ' and the first step structure 14A ', the third step structure 14C ' have a height difference in the third direction Z, and are disposed at an interval from the isolation structure 60 ' (i.e., the first step structure 14A ', the third step structure 14C ' exist between the second step structure 14B ' and the isolation structure 60 '), so as to be beneficial to avoiding the first stop portion 20 ' from being replaced.

In other examples, referring to fig. 23, along the second direction Y, the memory block 15 ' includes a first step structure 14A ' and a second step structure 14B ', the first step structure 14A ' is spaced apart from the isolation structure 60 ', and the first stop portion 20 ' is disposed on the plurality of steps 141 of the first step structure 14A '.

In this way, the first step structure 14A 'and the second step structure 14B' have a height difference in the third direction Z and are spaced apart from the spacer structure 50 ', so that the first stop portion 20' can be prevented from being replaced.

In some embodiments, referring to fig. 20-24B, each memory block 15 'further includes a sidewall 16'. Isolation structure 60 ' includes a first isolation structure 61 ' and a second isolation structure 62 '. Along the second direction Y, the first isolation structure 61 'is located between two adjacent side walls 16', and the second isolation structure 62 'is located between two adjacent step structures 13'. The sidewall 16' is configured to improve the structural stability of the three-dimensional memory 300.

In some examples, as shown in fig. 18 and fig. 22, the first isolation structure 61 'may be a unitary structure, that is, when the first isolation structure 61' is prepared, an isolation groove where the first isolation structure 61 'is located may be obtained by etching through one etching process, and the first isolation structure 61' is formed in the isolation groove.

In other examples, as shown in fig. 25, the first isolation structure 61 'may include a first isolation sub-portion 611', a second isolation sub-portion 612 ', and a third isolation sub-portion 613' that are sequentially connected along the first direction X. The size of the second partition sub-portion 612 'in the second direction Y is greater than that of the first partition sub-portion 611' in the second direction Y, and the size of the second partition sub-portion 612 'in the second direction Y is greater than that of the third partition sub-portion 613' in the second direction Y.

Illustratively, the first and third insulating subsections 611 ' and 613 ' are located in the core array region AA, the second insulating subsection 612 ' is located in the step region SS, and the second insulating subsection 612 ' contacts the sidewall 16 '.

For example, the second insulating sub-portion 612' may be simultaneously prepared with the dummy channel structure and the channel structure. The first and third insulating sub-portions 611 'and 613' may be prepared after the channel structure is prepared. Based on this, the material of the second isolation sub-portion 612' may be the same as that of the dummy channel structure or the channel structure.

By providing the second partition sub-portion 612 ', the present disclosure can be used to divide two adjacent storage blocks 15', on the one hand, and can also be used to support the stacked structure 10 ', on the other hand, to prevent the stacked structure 10' from collapsing in some embodiments.

In some embodiments, referring to fig. 22, 25 and 26, the step structures 13 ' in the two memory blocks 15 ' adjacent to the second isolation structure 62 ' are symmetrically disposed along the second direction Y.

It is understood that "the step structures 13 'in the two memory blocks 15' are symmetrically arranged" may be, for example, that the step structures 13 'of the two memory blocks 15' include the same number of step structures 14 ', and the two step structures 14' having the same distance to the second isolation structure 62 'in the two step structures 13' have the same height.

In some embodiments, referring to fig. 20 and 23, the heights of the plurality of step structures 14 'in the memory block 15' are gradually decreased along the second direction Y from the first isolation structure 61 'toward the second isolation structure 62'.

In other embodiments, referring to fig. 21, along the second direction Y and from the first isolation structure 61 'to the second isolation structure 62', the heights of the plurality of step structures 14 'in the memory block 15' are first decreased and then increased.

In some embodiments, referring to fig. 20 and 21, the two step structures 14 'adjacent to both sides of the second isolation structure 62' have the same height along the second direction Y.

In some embodiments, referring to fig. 20, 21 and 23, the three-dimensional memory 300 further includes a plurality of second stops 70' disposed along the first direction X. The plurality of second stops 70 'are located on the plurality of steps 141' of the other stepped structures 14 'except the stepped structure 14' provided with the first stop 20 'among the plurality of stepped structures 14'.

The barrier layer 30 ' is also located between the step structure 13 ' and the second stop 70 '. Likewise, it is understood that, as shown in fig. 23, the "barrier layer 30 ' is also located between the step structure 13 ' and the plurality of second stops 70 ', that is, the barrier layer 30 ' is located between the second stops 70 ' and the steps 141 ' of the step structure 13 ' in the third direction Z, and the barrier layer 30 ' is located between the second stops 70 ' and the steps 141 ' adjacent to the second stops 70 ' in the first direction X and the second direction Y. The protective layer 40 'also covers the second stop 70'.

Illustratively, when the protective layer 40 'also covers the second stop portion 70', at least a portion of the protective layer 40 'is located between the sidewall of the second stop layer 70' and the barrier layer 30 'in the first direction X, and at least a portion of the protective layer 40' is located between the sidewall of the second stop layer 70 'and the barrier layer 30' in the second direction Y.

For example, referring to fig. 20 and 21, when the first stop 20 ' is located on the plurality of steps 141 ' of the second stepped structure 14B ', the second stop 70 ' may be located on the plurality of steps 141 ' of the first and third stepped structures 14A ' and 14C '.

For example, referring to fig. 23, when the first stop 20 'is located on the plurality of steps 141' of the first stepped structure 14A ', the second stop 70' may be located on the plurality of steps 141 'of the second stepped structure 14B'.

In some embodiments, the material of the first and second stops 20 ', 70' may be the same.

Based on this, the material of the first stop 20 'and the second stop 70' may include silicon carbonitride or silicon nitride, for example.

In other embodiments, the material of the first stop 20 'and the second stop 70' may be different.

Illustratively, the material of the first stopper 20' may be, for example, silicon nitride.

In the case where the material of the first stop portion 20 'includes silicon nitride or silicon carbonitride, the material of the first stop portion 20' is different from the material of the gate layer 11 ', the etching selectivity of the first stop portion 20' is different from the etching selectivity of the gate layer 11 ', and the first stop portion 20' is not easily etched through when a contact hole is formed by etching using an etching process. Therefore, when the contact hole 51 ' where the contact pillar 50 ' is located is prepared, the plurality of contact holes 51 ' corresponding to the steps 141 ' with different heights are all stopped on the first stopping portion 20 ', and the distance between the bottom of each contact hole 51 ' and the step 141 ' is substantially the same, and then the etching process is used to etch the first stopping portion 20 ' exposed by the plurality of contact holes 51 ', the barrier layer 30 ' and the dielectric layer 12 ' under the first stopping portion 20 ', so that the gate layer 11 ' in the step 141 ' corresponding to the contact holes 51 ' is exposed. Therefore, the problem that after the contact hole penetrates through the high-rise step and the contact column is formed by filling the conductive material in the contact hole, short circuit occurs between the grid electrode layers in the adjacent high-rise steps is avoided, and the electrical performance and the yield of the three-dimensional memory are improved.

In some embodiments, as shown in fig. 26 and 27, the three-dimensional memory 300 further includes a plurality of gate line isolation structures 80 ' extending along the first direction X between two adjacent isolation structures 60 ', the gate line isolation structures 80 ' penetrating the second stopper 70 ' and the stacked structure 10 '. Along the first direction X, each gate line isolation structure 80 'includes a plurality of sub-isolation structures 81' separated from each other.

The "gate line isolation structure 80 'penetrates through the second stop portion 70' and the stacked structure 10 '", that is, the isolation groove where the gate line isolation structure 80' is located penetrates through the second stop portion 70 'and the stacked structure 10'.

Stress can also be relieved for the three-dimensional memory 300 by providing the gate line isolation structure 80'.

In some embodiments, the thickness of the second stop portion 70 ' is less than or equal to the thickness of the gate layer 11 ', and at this time, the material of the second stop portion 70 ' is the same as the material of the gate layer.

It is understood that when the thickness of the second stop portion 70 ' is less than or equal to the thickness of the gate layer 11 ', the sacrificial layer in the initial stacked structure 101 ' may be replaced with the gate layer 11 ' while the material of the second stop portion 70 ' is replaced with the gate layer 11 ' material by using the isolation trench in which the gate line isolation structure 80 ' is located.

Based on this, in some examples, the second stop portion 70 'may be the same as the gate layer 11', being a single-layer structure. At this time, the second stop portion 70 'also includes the conductive layer 111'. Materials of the conductive layer 111' include, but are not limited to, tungsten, cobalt, copper, aluminum, or doped crystalline silicon, doped silicon, and/or silicide

In other examples, the second stop 70 'may be the same as the gate layer 11', being a composite multilayer structure. At this time, the second stopping portion 70 ' may include a high dielectric constant layer 112 ', a metal compound layer 113 ', and a conductive layer 111 ', and the high dielectric constant layer 112 ' wraps the conductive layer 111 ', and the metal compound layer 113 ' is located between the high dielectric constant layer 112 ' and the conductive layer 111 '. The material of the high-k layer 112' may include alumina AL, for example₂O₃The material of the metal compound layer 113' may include tantalum nitride or titanium nitride, for example.

In other embodiments, the thickness of the second stop portion 70 'is greater than the thickness of the gate layer 11', and at this time, the material of the second stop portion 70 'is the same as the material of the gate line isolation structure 80'.

Based on this, in some examples, the materials of the second stopper 70 'and the gate line isolation structure 80' may each include a dielectric material, for example, silicon oxide and/or silicon nitride. In other examples, the second stopper 70 'and the gate line isolation structure 80' may be a composite stacked structure, for example, the second stopper 70 '(or the gate line isolation structure 80') may include a dielectric material layer and a conductive material layer (such as at least one of tungsten, cobalt, copper, aluminum, or polysilicon) sequentially disposed. In still other examples, the second stop 70' may include a dielectric material, and a high dielectric constant layer encasing the dielectric material. In still other examples, the second stop 70' may also include a composite laminate structure, and a high dielectric constant layer encasing the composite laminate structure.

Two three-dimensional memories for solving the technical problem that a high-level gate layer is easily penetrated by a contact pillar are introduced above. The two methods for manufacturing the three-dimensional memory will be described below.

Referring to fig. 28, some embodiments of the present disclosure provide a method for manufacturing a three-dimensional memory 200, including steps S1 to S6:

s1, referring to fig. 29A, 29B and 30, the initial stacked structure 101 is formed. The initial stacked structure 101 includes a sacrificial layer 110 and a dielectric layer 12. The initial stacked structure 101 includes a step structure 13, and the step structure 13 includes a plurality of step structures 14 arranged along the first direction X and having different heights along the second direction Y. Each stepped structure 14 includes a plurality of steps 141. The first direction X and the second direction Y are perpendicular to each other.

It is noted that the sacrificial layer 110 and the dielectric layer 12 may be formed by, for example, a Chemical Vapor Deposition (CVD) process, a Plasma Enhanced Chemical Vapor Deposition (PECVD) process, a high density plasma chemical vapor deposition (HDP-CVD) process, an Atomic Layer Deposition (ALD) process, or a sputtering process.

Illustratively, the sacrificial layer 110 and the dielectric layer 12 have different etching selection ratios, so that the sacrificial layer 110 can be removed in a subsequent process, while the dielectric layer 12 is remained, thereby forming a gate line gap for forming the gate layer 11. Illustratively, the material of the sacrificial layer 110 may be silicon nitride, and the material of the dielectric layer 12 may be silicon oxide.

The number of the sacrificial layers 110 and the dielectric layers 12 in the initial stacked structure 101 may be designed according to actual requirements, and for example, the initial stacked structure 101 may have 16 sacrificial layers 110 and dielectric layers 12, or 32 sacrificial layers 110 and dielectric layers 12. The present disclosure is not so limited. It is worth noting that the number of initial film layer pairs in the drawings provided in the present disclosure is merely an example and does not constitute a limitation of the present disclosure.

In the initial stacked structure 101, the thicknesses of the plurality of sacrificial layers 110 may be substantially the same or different; the thicknesses of the plurality of dielectric layers 12 may be substantially the same or different. The thicknesses of the plurality of sacrificial layers 110 and the plurality of dielectric layers 12 may be selected according to actual requirements.

In some examples, as shown in fig. 31, step S1, forming an initial stacked structure 101, includes:

and S11, forming a preset stack structure 1011, wherein the preset stack structure 1011 comprises the sacrificial layer 110 and the dielectric layer 12 which are alternately arranged.

S12, the predetermined stacked structure 1011 is etched to form a plurality of reference steps 142 arranged along the second direction Y. Each reference step 142 corresponds to a stair-step structure 14.

S13, forming a plurality of steps 141 arranged along the first direction X based on the reference step 142 to form the stair structure 14 by using a trim etching process and a cutting process. The initial stacked structure 101 includes a plurality of stepped structures 14.

In some examples, as shown in fig. 32, the step S12 of etching the preset stack 1011 to form a plurality of reference steps 142 arranged along the second direction Y includes:

s121, as shown in fig. 33A and 33B, a first mask layer 21 is formed on the predetermined stack structure 1011. The first mask layer 21 exposes the first area W1 of the predetermined stack structure 1011.

S122, as shown in FIG. 34, at least one sacrificial layer 110 and at least one dielectric layer 12 of the first area W1 of the predetermined stacked structure 1011 are etched.

S123, as shown in fig. 35A and 35B, the first mask layer 21 is trimmed to expose the second area W2 of the predetermined stack structure 1011. The first region W1 is located inside the second region W2. There is a space between the boundary of the first region W1 and the boundary of the second region W2 along the second direction Y.

S124, as shown in fig. 36, at least one sacrificial layer 110 and at least one dielectric layer 12 of the second area W2 of the predetermined stacked structure 1011 are etched to form three reference steps 142 with different heights in the second direction Y.

For example, in step S122, one sacrificial layer 110 and one dielectric layer 12 of the first region W1 of the predetermined stacked structure 1011 may be etched, and in step S124, one sacrificial layer 110 and one dielectric layer 12 of the second region W2 of the predetermined stacked structure 1011 may be etched to form three reference steps 142 with different heights in the second direction Y.

When one sacrificial layer 110 and one dielectric layer 12 of the first region W1 of the predetermined stacked structure 1011 are etched in step S122, and when one sacrificial layer 110 and one dielectric layer 12 of the second region W2 of the predetermined stacked structure 1011 are etched in step S124, the heights of two adjacent step structures 14 in the third direction Z are different by the height of one sacrificial layer 110 and the height of one dielectric layer 12.

In other implementations, as shown in fig. 37, the step S12 of etching the preset stacked structure 1011 to form a plurality of reference steps 142 arranged along the second direction Y includes:

in step S125, as shown in fig. 38, a second mask layer 22 is formed on the predetermined stack structure 1011. The second mask layer 22 exposes at least one third region W3 of the predetermined stack structure 1011.

The exposure of the two third regions W3 by the second mask layer 22 is illustrated in fig. 38, and the disclosure is not limited thereto.

S126, as shown in fig. 39, at least one sacrificial layer 110 and at least one dielectric layer 12 in the third area W3 of the predetermined stacked structure 1011 are etched to form three reference steps 142 with a height decreasing first and then increasing in the second direction Y.

Illustratively, the predetermined stacked structure 1011 may be etched using a wet etching process or a dry etching process.

It should be noted that, the above steps are described by taking the formation of three reference steps 142 as an example, and in other embodiments, two reference steps 142 or more than three reference steps 142 may be formed.

Illustratively, when two step structures 14 are included in the step structure 13, the step structures 14 can be obtained by steps S121, S122, and S13.

For example, when three or more step structures 14 are included in the step structure 13, after performing steps S121 to S124, the first mask layer 21 may be trimmed multiple times, so that the area of the initial stacked structure to which the first mask layer 21 can be exposed is increased, and after trimming the first mask layer 21 each time, at least one initial film layer pair 102 of the initial stacked structure 101 exposed by the first mask layer 21 is etched to form three or more reference steps 142, so as to form three or more step structures 14.

It is noted that after obtaining the plurality of step structures 14, the trimmed first mask layer 21 or second mask layer 22 needs to be removed.

Illustratively, in step S13, a plurality of steps 141 arranged along the first direction X are formed based on the reference step 142 by using a trimming etching process and a cutting process, so as to form the step structure 14 and simultaneously form the sidewall 16.

S2, a plurality of first stop portions 20 are formed on the plurality of steps 141 of the at least one stepped structure 14. The plurality of first stop portions 20 are disposed in the first direction X, and each first stop portion 20 is disposed on one step 141.

In some examples, as shown in fig. 40, the step S2 of forming a plurality of first stops 20 on the plurality of steps 141 of the at least one stepped structure 14 includes:

s21, etching the uppermost sacrificial layer 110 and the dielectric layer 12 in each step 141 to form a plurality of first stops 20.

Referring to fig. 29A and fig. 41A, and fig. 29B and fig. 41B, the sacrificial layer 110 and the dielectric layer 12 located uppermost in each step 141 are etched, for example, a portion 143 of the sacrificial layer 110 and the dielectric layer 12 located at the intersection of the step 141 in the second direction Y may be etched. Referring to fig. 30 and 42, the uppermost sacrificial layer 110 and the dielectric layer 12 in each step 141 are etched, for example, a portion 144 of the sacrificial layer 110 and the dielectric layer 12 at the intersection of the steps 141 in the first direction X is etched.

In this way, by etching the uppermost sacrificial layer 110 and the dielectric layer 12 at each step 141, a portion of the uppermost sacrificial layer 110 and the dielectric layer 12 at the junction of the steps 141 is removed to form a plurality of first stops 20, without separately depositing an additional film layer, thereby reducing the manufacturing process and manufacturing cost of the three-dimensional memory 200.

Meanwhile, there is a space between the first stop portion 20 and the step formed, so that the first stop portion 20 is not easily replaced in a subsequent process of replacing the sacrificial layer 110 with the gate layer 11. Therefore, in the subsequent process of forming the contact hole 41, the contact holes 41 corresponding to different steps 141 can be stopped on the corresponding first stop portion 20 after the first etching, and then stopped on the gate layer 11 after the second etching, so that the contact hole is prevented from penetrating through the upper steps, and the problem of short circuit between the upper steps after the contact pillar is formed is solved.

S3, referring to fig. 43 and 44, the protective layer 30 is formed. The protective layer 30 covers the step structure 13 and the first stopper 20, and at least a portion of the protective layer 30 is located between the first stopper 20 and the step 141 adjacent to the first stopper 20.

The protective layer 30 may be made of silicon oxide, including but not limited to tetraethoxysilane (abbreviated as TEOS), siloxane, silsesquioxane, and the like.

Illustratively, the protective layer 30 may be formed by a Chemical Vapor Deposition (CVD) process, a spin coating process, or the like.

Illustratively, the protective layer 30 may be planarized by a Chemical Mechanical Polishing (CMP) process after it is formed.

S4, referring to fig. 45 and 46, the sacrificial layer 110 is replaced with the gate layer 11 to form the stacked structure 10.

In some embodiments, the three-dimensional memory 200 includes an isolation structure 50, the isolation structure 50 includes a first isolation structure 51 and a second isolation structure 52, and the first isolation structure 51 and the second isolation structure 52 are both a unitary structure.

Based on this, in some examples, as shown in fig. 47, the method of making further comprises:

s41, referring to fig. 48, a first separation groove 501 extending along the first direction X and penetrating the initial stacked structure 101 is formed, and the first separation groove 501 divides the initial stacked structure 101 into a plurality of initial memory blocks 150. Each initial memory block 150 includes a stair-step structure 13.

Illustratively, the first isolation trenches 501 may be formed by using a dry etching process, and the first isolation trenches 501 penetrate the initial stacked structure 101 along the third direction Z.

Illustratively, the sacrificial layer 110 may be replaced with the gate layer 11 by using the first isolation trenches 501. For example, a wet etching process may be used to immerse the etching liquid into the initial stacked structure 101 from the first isolation groove 501. At this time, since the sacrificial layer 110 and the dielectric layer 12 have different etching selection ratios, the sacrificial layer 110 can be etched and the dielectric layer 12 can be remained during the etching process, thereby forming a cavity at a corresponding formed portion.

Illustratively, the gate layer 11 may be formed in the cavity by one or more of CVD, PVD, ALD.

The gate layer 11 may be a single layer structure, for example, the gate layer 11 includes a conductive material, including but not limited to tungsten, cobalt, copper, aluminum, or doped crystalline silicon. Alternatively, the gate layer 11 may be a multi-layer composite structure, for example, the gate layer 11 may include sequentially formed high-k layers (such as aluminum oxide AL)₂O₃) A metal compound layer (such as tantalum nitride or titanium nitride), and a conductive layer (such as tungsten).

In some examples, as shown in fig. 47, the method of making further comprises:

s42, as shown in fig. 45, isolation structures 50 are formed in the first trenches 501.

Illustratively, the isolation structure 50 may be formed by one or more of CVD, PVD, ALD processes. The isolation structure 50 may include only one or more dielectric material layers, or may include one or more dielectric material layers and at least one conductive material layer sequentially disposed.

Among them, the isolation structure 50 may divide the stacked structure 10 into a plurality of memory blocks 15, so that the storage density of the three-dimensional memory 200 may be further improved.

In other embodiments, as shown in fig. 13, the three-dimensional memory 200 includes an isolation structure 50, and the isolation structure 50 includes a first isolation structure 51 and a second isolation structure 52. The first isolation structure 51 may include a first isolation sub-portion 511, a second isolation sub-portion 512, and a third isolation sub-portion 513 sequentially connected along the first direction X.

In some examples, as shown in fig. 49, the method of making can further comprise:

s43, referring to fig. 50, the second isolating sub-portion 512 extending along the first direction X and penetrating the initial stacked structure 101 is formed.

Based on this, the second isolating sub-portion 512 may be prepared simultaneously with the dummy channel structure and/or the channel structure, for example, the second isolating sub-portion 512 may be formed after the initial stack structure 101 is formed and before the protective layer 30 is formed.

S44, referring to fig. 51, a first sub-groove 502, a second sub-groove 503, and a second sub-groove 504 extending along the first direction X and penetrating the initial stacked structure 101 are formed. The first sub-sub groove 502 and the second sub-groove 503 are in contact with both ends of the second partition sub-portion 512, respectively, along the first direction X. Along the second direction Y, the second isolation trenches 504 are located between two adjacent second isolation subsections 512.

In some examples, as shown in fig. 49, the method of making can further comprise:

s45, referring to fig. 13, the first isolation sub-portion 511 is formed in the first sub-groove 502, the third isolation sub-portion 513 is formed in the second sub-groove 503, and the second isolation structure 52 is formed in the second sub-groove 504.

The first, third and second isolating subsections 511, 513 and 512 constitute at least part of the first isolating structure 51.

In some implementations, referring to fig. 41A, 41B, and 42, the method of making can further include:

the plurality of second stop portions 60 are formed on the plurality of steps 141 of the other step structure 14 than the step structure 14 provided with the first stop portion 20 among the plurality of step structures 14.

In some embodiments, referring to fig. 52, the method of making can further comprise:

s46, referring to fig. 53, a plurality of third grooves 505 extending in the first direction X are formed. The third partition 505 penetrates the second stop portion 60 and the initial stacked structure 101. Each of the third slots 505 includes a plurality of third sub-slots 506 separated from each other along the first direction X.

In some embodiments, referring to fig. 41, the method of making further comprises:

s47, referring to fig. 45, a gate line isolation structure 70 is formed in the third bank 505.

For example, before the step S4 of replacing the sacrificial layer 120 with the gate layer 11 to form the stacked structure 10, a plurality of third isolation trenches 505 extending along the first direction X may be formed. The gate line isolation structure 70 may be formed in the third bank 505 after step S4.

In some examples, third septum 505 may be formed simultaneously with first septum 501. In other examples, the third partition groove 505 may be formed simultaneously with the first sub-partition groove 502, the second sub-partition groove 503, and the second partition groove 504.

In this way, in the process of replacing the sacrificial layer 110 with the gate layer 11, the material of the second stop portion can be replaced with the same material as the gate layer 11 by using the plurality of third trenches 505.

S5, referring to fig. 6 to 11, a plurality of contact pillars 40 are formed. The contact pillar 40 penetrates the protective layer 30 and the first stopper 20, and is electrically connected to the gate layer 11 in the step 141 corresponding to the first stopper 20.

Referring to fig. 54, for example, the step S5 of forming the plurality of contact pillars 40 includes the steps S51 to S53:

s51, referring to fig. 55 and 56, the protective layer 30 is etched to the first stopper 20, and a plurality of contact holes 41 are formed.

Illustratively, the contact hole 41 may be formed by a wet etching process.

Since the first stop portion 20 and the gate layer 11 are made of different materials and have different etching selectivity, the first stop portion 20 is not easily etched through like the gate layer 11 in the process of forming the contact hole 41, and the contact holes 41 corresponding to the steps 141 with different heights may each stop on the first stop portion 20 on the corresponding step, thereby exposing the first stop portion 20.

S52, referring to fig. 57 and 58, the exposed first stopper 20 of the contact hole 41 and the dielectric layer 12 under the first stopper 20 are etched to expose the gate layer 11 of the contact hole 41.

Illustratively, the exposed first stopper 20 of the contact hole 41 and the dielectric layer 12 under the first stopper 20 may be etched by dry etching, so that the contact 41 exposes the gate layer 11.

Here, the distances between the first stop portions 20 on the different steps 141 and the gate layer 11 in the steps 141 are substantially the same, and thus, the same thickness of the film layer may be etched at the different steps 141 to expose the gate layer 11. Therefore, the contact holes 41 formed in the three-dimensional memory can be in good contact with the gate layer 11 corresponding to the steps 141, and cannot penetrate through the gate layer 11 corresponding to the steps, so that the situation that the gate layer is penetrated, short circuits occur among different gate layers after the contact pillars 40 are formed can be effectively avoided, and the electrical performance and the virtuous performance of the three-dimensional memory are improved.

S53, referring to fig. 6 to 11, the contact post 40 is formed in the contact hole 41.

Illustratively, the contact post 40 may be formed by one of CVD, PVD, ALD processes. The material of the contact post 40 is a conductive material, such as at least one conductive material of tungsten, cobalt, copper, aluminum, doped crystalline silicon, or silicide.

Some embodiments of the present disclosure further provide another method for manufacturing a three-dimensional memory 300, wherein similar steps to those in the above embodiments are implemented by referring to the method for manufacturing the three-dimensional memory 200 provided in the above embodiments.

Referring to fig. 59, the method of fabricating the three-dimensional memory 300 includes steps S1 'to S5':

s1 ', see fig. 60 and 61, forming the initial stacked structure 101'. The initial stacked structure 101 ' includes sacrificial layers 110 ' and dielectric layers 12 ' alternately disposed. The initial stacked structure 101 'includes an initial step structure 130', and the initial step structure 130 'includes a plurality of stepped structures 14' disposed along the first direction X and having different heights along the second direction Y. The stepped structure 14 'includes a plurality of steps 141'. The first direction X and the second direction Y are perpendicular to each other.

Similar to the method for manufacturing the three-dimensional memory 200 provided in the previous embodiment, the sacrificial layer 110 'and the dielectric layer 12' may be formed by, for example, a Chemical Vapor Deposition (CVD) process, a Plasma Enhanced Chemical Vapor Deposition (PECVD) process, a high density plasma chemical vapor deposition (HDP-CVD) process, an Atomic Layer Deposition (ALD) process, or a sputtering process.

The sacrificial layer 110 ' and the dielectric layer 12 ' have different etching selection ratios, so that the sacrificial layer 110 ' can be removed in a subsequent process, while the dielectric layer 12 ' is remained, thereby forming a gate line gap for forming the gate layer 11 '. Illustratively, the material of the sacrificial layer 110 'may be silicon nitride, and the material of the dielectric layer 12' may be silicon oxide.

The number of the sacrificial layers 110 'and the dielectric layers 12' in the initial stacked structure 101 'may be designed according to actual requirements, and for example, the initial stacked structure 101' may have 16 pairs of sacrificial layers 110 'and dielectric layers 12', or 32 pairs of sacrificial layers 110 'and dielectric layers 12', which is not limited by this disclosure. It is worth noting that the number of initial film layer pairs 102' in the figures provided in the present disclosure is merely an example and not a limitation of the present disclosure.

In the initial stacked structure 101 ', the thicknesses of the plurality of sacrificial layers 110' may be substantially the same or different; the thicknesses of the dielectric layers 12' may be substantially the same or different. The thicknesses of the plurality of sacrificial layers 110 'and the plurality of dielectric layers 12' may be selected according to actual requirements.

Here, the process of forming the initial stacked structure 101' may refer to steps S11 to S13 in the method for manufacturing the three-dimensional memory 200.

S2 ', as shown in fig. 62 and 63, a barrier layer 30 ' is formed covering the stepped structure 13 '.

Illustratively, the barrier layer 30' may be made of an insulating material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, or combinations thereof.

S3 ', referring to fig. 64 and 65, a plurality of first stoppers 20' are formed at a side of the barrier layer 30 'away from the stepped structure 13'. The plurality of first stoppers 20 ' are disposed along the first direction X on the plurality of steps 141 ' of the at least one stepped structure 14 ', and each first stopper 20 ' is disposed on one step 141 '.

In some examples, referring to fig. 66, the forming of the plurality of first stoppers 20 'at the side of the barrier layer 30' away from the step structure 13 'at step S3' may include:

s31 ', see fig. 67 and 68, a pre-stopper layer 21' is formed on a side of the barrier layer 30 'away from the step structure 13'.

S32 ', referring to fig. 64 and 65, a plurality of first stopping portions 20 ' are formed by removing portions 211 ' of the preset stopping layer 21 ' where the corresponding steps 141 ' meet.

In some examples, the material of the preset stop layer 21 'may be the same as the material of the sacrificial layer 120'.

In other examples, the material of the preset stop layer 21 'may be different from the material of the sacrificial layer 120'. At this time, the material of the predetermined stop layer 21' may be silicon carbonitride doped, for example.

S4 ', referring to fig. 69 and 70, the protective layer 40' is formed. The protective layer 40 ' covers the barrier layer 30 ' and the first stop 20 '.

It is understood that, referring to fig. 64 and 65, after the plurality of first stoppers 20 ' are formed, a gap exists between the sidewall of the first stopper 20 ' and the barrier layer 30 ' in both the first direction X and the second direction Y. Thus, after the protective layer 40 'is subsequently formed, at least a portion of the protective layer 40' may fall into a gap between the sidewall of the first stopper 20 'and the barrier layer 30'.

S5 ', referring to fig. 71, the sacrificial layer 110' is replaced with the gate layer 11 ', forming a stacked structure 10'.

In some embodiments, the three-dimensional memory 300 further comprises an isolation structure 60'. Isolation structure 60 ' includes a first isolation structure 61 ' and a second isolation structure 62 ', and first isolation structure 61 ' and second isolation structure 62 ' are each a unitary structure.

Based on this, in some examples, as shown in fig. 72, the method of making may further comprise:

s51 ', referring to fig. 73, a first separation groove 601' extending in the first direction X and penetrating the initial stacked structure 101 'is formed, and the first separation groove 601' divides the initial stacked structure 101 'into a plurality of initial memory blocks 150'. Each initial memory block 150 'includes a stair-step structure 13'.

Illustratively, the first isolation grooves 601 ' may be formed by using a dry etching process, and the first isolation grooves 601 ' penetrate the initial stacked structure 101 ' along the third direction Z.

Illustratively, the sacrificial layer 110 ' may be replaced with the gate layer 11 ' by using the first isolation trenches 601 '. For example, a wet etching process may be used to immerse the etching liquid into the initial stacked structure 101 'from the first isolation groove 601'. At this time, since the sacrificial layer 110 'and the dielectric layer 12' have different etching selection ratios, the sacrificial layer 110 'can be etched and the dielectric layer 12' can be remained during the etching process, thereby forming a cavity at a portion correspondingly formed.

Illustratively, the gate layer 11' may be formed in the cavity by one or more of CVD, PVD, ALD.

In some examples, as shown in fig. 72, the method of making can further include:

s52 ', referring to fig. 71, isolation structures 60 ' are formed in the first trenches 601 '.

Illustratively, the isolation structure 60' may be formed by one or more of CVD, PVD, ALD processes. The isolation structure 60' may include only one or more dielectric material layers, or may include one or more dielectric material layers and at least one conductive material layer sequentially disposed.

In other embodiments, as shown in fig. 25, three-dimensional memory 300 includes isolation structures 60 ', and isolation structures 60' include first isolation structures 61 'and second isolation structures 62'. The first isolation structure 61 'may include a first isolation sub-portion 611', a second isolation sub-portion 612 ', and a third isolation sub-portion 613' sequentially connected along the first direction X.

Based on this, in some examples, as shown in fig. 74, the method of making may further comprise:

s53 ', see fig. 75, a second isolation sub-portion 612 ' extending along the first direction X and penetrating the initial stacked structure 101 ' is formed.

Based on this, the second insulating sub-portion 612 'may be formed simultaneously with the dummy channel structure and/or the channel structure, for example, the second insulating sub-portion 612' may be formed after the initial stacked structure 101 'is formed and before the protective layer 40' is formed.

S54 ', see fig. 76, forming a first sub-compartment groove 602 ', a second sub-compartment groove 603 ' and a second sub-compartment groove 604 ' extending in the first direction X and penetrating the initial stacked structure 101 '; along the first direction X, the first sub-groove 602 ' and the second sub-groove 603 ' are in contact with both ends of the second separator sub-portion 612 ', respectively. Along the second direction Y, the second isolation grooves 604 'are located between two adjacent second isolation subsections 612'.

In some examples, as shown in fig. 74, the method of making further comprises:

s55 ', referring to fig. 71, a first partition sub-portion 611 ' is formed in the first sub-groove 602 ', a third partition sub-portion 613 ' is formed in the second sub-groove 603 ', and a second partition structure 62 ' is formed in the second sub-groove 604 '.

The first, third and second isolation subsections 611, 613 and 612 'form at least part of the first isolation structure 61'.

In some embodiments, as shown in fig. 77, the method of making further comprises:

s7 ', referring to fig. 71, a plurality of second stoppers 70' are formed on a side of the barrier layer 30 'away from the stepped structure 13'. The plurality of second stop portions 70 'are disposed along the first direction X, and the plurality of second stop portions 70' are located on the plurality of steps 141 'of the stepped structures 14' other than the stepped structure 14 'provided with the first stop portion 20'. Each second stop 70 'is located on one step 141'.

In some embodiments, as shown in fig. 78, the method of making further comprises:

s56 ', as shown in fig. 79, a plurality of third grooves 605' extending in the first direction X are formed. The third partition 605 ' penetrates the second stopper 70 ' and the initial stacked structure 101 '. Along the first direction X, each third slot 605 'comprises a plurality of third sub-slots 606' separated from each other.

For example, the third isolation groove 605 'may be formed simultaneously with the first isolation groove 601', or the third isolation groove 605 'may be formed simultaneously with the second first sub-isolation groove 602', the second sub-isolation groove 603 ', and the second isolation groove 604'.

In some embodiments, as shown in fig. 78, the method of making further comprises:

s57 ', referring to fig. 71, a gate line isolation structure 80 ' is formed in the third trenches 605 '.

For example, before the step S5 ' of replacing the sacrificial layer 120 ' with the gate layer 11 ' to form the stacked structure 10 ', a plurality of third trenches 605 ' extending along the first direction X may be formed. After step S5 ', a gate line isolation structure 80 ' is formed in the third isolation trench 605 '.

In this way, in the process of replacing the sacrificial layer 110 ' with the gate layer 11 ', the material of the second stop portion 70 ' may be replaced with the same material as the gate layer 11 ' using the plurality of third barrier grooves 505 '.

S6 ', forming a plurality of contact pillars 50'. The contact pillar 50 ' penetrates through the protective layer 40 ', the first stopper 20 ', and the barrier layer 30 ' to be connected to the gate layer 11 ' in the step 141 ' corresponding to the first stopper 20 '.

Illustratively, referring to FIG. 80, S6 ', forming a plurality of contact pillars 50' includes steps S61 'through S63':

s61 ', referring to fig. 81 and 82, the protective layer 40' is etched to the first stopper 20 ', forming a plurality of contact holes 51'.

S62 ', referring to fig. 83 and 84, the first stopper 20' exposed by the contact hole 51 'and the barrier layer 30' and the dielectric layer 12 'under the first stopper 20' are etched such that the contact hole 51 'exposes the gate layer 11'.

S63 ', referring to fig. 19A, the contact stud 50 ' is formed in the contact hole 51 '.

In some embodiments, referring to fig. 85 and 86, the three-dimensional memory 200 (or the three-dimensional memory 300) may further include a peripheral device 400.

Illustratively, with continuing reference to fig. 85 and 86, the peripheral device 400 includes a substrate 401 and a peripheral circuit layer 402.

The types of the peripheral circuit layer 402 include various types, which can be selected according to actual needs. The peripheral circuit layer 402 may include, for example, page buffers, decoders (e.g., row and column decoders), sense amplifiers, drivers (e.g., word line drivers), or any active (or passive) components of a circuit (e.g., transistors, diodes, resistors, capacitors, etc.).

The peripheral circuit layer 402 may include a plurality of transistors, for example. Illustratively, at least a portion of the plurality of transistors are formed in the substrate 401 (e.g., below a top surface of the substrate 401) and/or formed directly on the substrate 401.

In addition, the peripheral circuit layer 402 may include any other circuit compatible with a high-level logic process. Illustratively, the peripheral circuitry layer 402 includes logic circuitry (e.g., processors and programmable logic devices), and/or memory circuitry (e.g., static random access memory).

As shown in fig. 87, some embodiments of the present disclosure provide a storage system 1000, the storage system 1000 including a three-dimensional memory 200 (three-dimensional memory 300) and a controller 2000. And a controller 2000 coupled to the three-dimensional memory 200 (the three-dimensional memory 300) to control the three-dimensional memory 2000 to store data.

The Storage system 1000 may be integrated into various types of Storage devices, for example, included in the same package (e.g., a Universal Flash Storage (UFS) package or an Embedded multimedia Card (eMMC) package). That is, the storage system 1000 may be applied to and packaged into different types of electronic products, such as a mobile phone (e.g., a cell phone), a desktop computer, a tablet computer, a laptop computer, a server, an in-vehicle device, a game console, a printer, a positioning device, a wearable device, a smart sensor, a mobile power supply, a Virtual Reality (VR) device, an Augmented Reality (AR) device, or any other suitable electronic device having storage therein.

In some embodiments, referring to fig. 87, the memory system 1000 includes a controller 2000 and a three-dimensional memory 200 (or a three-dimensional memory 300), and the memory system 1000 may be integrated into a memory card.

The Memory Card includes any one of a PC Card (PCMCIA), a Compact Flash (CF) Card, a Smart Media (SM) Card, a Memory stick, a Multimedia Card (MMC), a Secure Digital Memory Card (SD), and a UFS.

In other embodiments, referring to fig. 88, the storage system 1000 includes a controller 2000 and a plurality of three-dimensional memories 200 (or three-dimensional memories 300), and the storage system 1000 is integrated into a Solid State Drive (SSD).

In storage system 1000, in some embodiments, controller 2000 is configured for operation in a low duty cycle environment, such as an SD card, CF card, Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, mobile phones, and the like.

In other embodiments, the controller 2000 is configured for operation in a high duty cycle environment SSD or eMMC for data storage and enterprise storage arrays of mobile devices such as smart phones, tablets, laptops, and the like.

In some embodiments, the controller 2000 may be configured to manage data stored in the three-dimensional memory 200 (or the three-dimensional memory 300) and communicate with an external device (e.g., a host). In some embodiments, the controller 2000 may also be configured to control operations of the three-dimensional memory 200 (or the three-dimensional memory 300), such as read, erase, and program operations. In some embodiments, the controller 2000 may also be configured to manage various functions with respect to data stored or to be stored in the three-dimensional memory 200 (or the three-dimensional memory 200), including at least one of bad block management, garbage collection, logical to physical address translation, wear leveling. In some embodiments, the controller 2000 is further configured to process an error correction code with respect to data read from the three-dimensional memory 200 (or the three-dimensional memory 200) or written to the three-dimensional memory 200 (or the three-dimensional memory 200).

Of course, the controller 2000 may also perform any other suitable functions, such as formatting the three-dimensional memory 200 (or the three-dimensional memory 300); for example, the controller 2000 may communicate with an external device (e.g., a host) through at least one of various interface protocols.

It should be noted that the interface protocol includes at least one of a USB protocol, an MMC protocol, a Peripheral Component Interconnect (PCI) protocol, a PCI express (PCI-E) protocol, an Advanced Technology Attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a Small Computer System Interface (SCSI) protocol, an Enhanced Small Disk Interface (ESDI) protocol, an Integrated Drive Electronics (IDE) protocol, and a Firewire protocol.

Some embodiments of the present disclosure provide an electronic device, which may be any of a cell phone, a desktop computer, a tablet computer, a notebook computer, a server, an in-vehicle device, a wearable device (e.g., a smart watch, a smart bracelet, smart glasses, etc.), a mobile power source, a game console, a digital multimedia player, etc.

The electronic device may include the storage system 1000 described above, and may further include at least one of a Central Processing Unit (CPU), a cache (cache), and the like.

The above description is only for the specific embodiments of the present disclosure, but the scope of the present disclosure is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present disclosure should be covered within the scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims (23)

1. A three-dimensional memory, comprising:

the stack structure comprises gate layers and dielectric layers which are alternately arranged; the stacked structure includes a stepped structure including a plurality of stepped structures arranged in a first direction and having different heights in a second direction; the stair step structure comprises a plurality of steps; the first direction and the second direction are perpendicular to each other;

a plurality of first stoppers provided along the first direction on a plurality of steps of at least one of the stepped structures, each of the first stoppers being provided on one of the steps;

the barrier layer covers the step structure and is positioned between the step structure and the first stopping part;

a protective layer covering the barrier layer and the first stopper;

and the contact posts penetrate through the protective layer, the first stop part and the barrier layer and are connected with the gate layer in the step corresponding to the first stop part.

2. The three-dimensional memory according to claim 1, further comprising:

an isolation structure extending in the first direction and penetrating the stacked structure; the isolation structure divides the stacked structure into a plurality of memory blocks, each memory block including the step structure;

and the stepped structure where the first stopping part is located and the isolation structure are arranged at intervals.

3. The three-dimensional memory according to claim 2, wherein the memory block includes a first step structure, a second step structure, and a third step structure along the second direction, the first stopper being provided on a plurality of steps of the second step structure.

4. The three-dimensional memory according to claim 2, wherein along the second direction, the memory block comprises a first step structure and a second step structure, the first step structure is spaced apart from the isolation structure, and the first stop portion is disposed on a plurality of steps of the first step structure.

5. The three-dimensional memory according to claim 2, wherein each memory block further comprises a sidewall;

the isolation structure comprises a first isolation structure and a second isolation structure;

along the second direction, the first isolation structure is located between two adjacent side walls, and the second isolation structure is located between two adjacent step structures; and along the second direction, the step structures in the two storage blocks adjacent to the second isolation structure are symmetrically arranged.

6. The three-dimensional memory according to claim 5, wherein the heights of the plurality of staircase structures in the memory block gradually decrease along the second direction from the first isolation structure toward the second isolation structure.

7. The three-dimensional memory according to claim 5, wherein the two step structures adjacent to both sides of the second isolation structure have the same height along the second direction.

8. The three-dimensional memory according to claim 2, further comprising:

a plurality of second stopping portions provided along the first direction on a plurality of steps of the other step structure except the step structure provided with the first stopping portion;

wherein the barrier layer is further located between the step structure and the second stopper, and the protective layer further covers the second stopper.

9. The three-dimensional memory according to claim 8, further comprising:

a plurality of gate line isolation structures extending along the first direction, the gate line isolation structures being located between two adjacent isolation structures, the gate line isolation structures penetrating the second stop portion and the stacked structure; along the first direction, each grid line isolation structure comprises a plurality of sub-isolation structures which are separated from each other.

10. The three-dimensional memory according to claim 9, wherein a thickness of the second stopper is less than or equal to a thickness of the gate layer; the material of the second stopper is the same as that of the gate layer.

11. The three-dimensional memory according to claim 9, wherein a thickness of the second stopper is larger than a thickness of the gate layer; the second stopper is made of the same material as the gate line isolation structure.

12. The three-dimensional memory according to claim 8, wherein a material of the second stopper is the same as a material of the first stopper.

13. The three-dimensional memory according to claim 12, wherein the material of the second stopper is carbon-doped silicon oxide.

14. The three-dimensional memory according to any one of claims 1 to 12, wherein a material of the first stopper comprises silicon nitride.

15. A method for preparing a three-dimensional memory is characterized by comprising the following steps:

forming an initial stacked structure; the initial stacking structure comprises sacrificial layers and dielectric layers which are alternately arranged; the initial stacking structure comprises a step structure, and the step structure comprises a plurality of step structures which are arranged along a first direction and have different heights along a second direction; the stair step structure comprises a plurality of steps; the first direction and the second direction are perpendicular to each other;

forming a barrier layer covering the step structure;

forming a plurality of first stops on one side of the barrier layer far away from the step structure; the plurality of first stopping parts are arranged along the first direction and are positioned on a plurality of steps of at least one stepped structure, and each first stopping part is arranged on one step;

forming a protective layer; the protective layer covers the barrier layer and the first stop;

replacing the sacrificial layer with a gate layer to form a stacked structure;

forming a plurality of contact pillars penetrating the protection layer, the first stopper, and the barrier layer, and electrically connected to the gate layer in the step corresponding to the first stopper.

16. The method of claim 15, wherein forming a plurality of first stops on a side of the barrier layer away from the step structure comprises:

forming a preset stop layer on one side of the barrier layer, which is far away from the step structure;

and removing the part of the preset stop layer corresponding to the connection part of the steps to form a plurality of first stop parts.

17. The method of manufacturing according to claim 15, further comprising:

forming a first isolation groove extending along a first direction and penetrating through the initial stacking structure, wherein the first isolation groove divides the initial stacking structure into a plurality of initial storage blocks, and each initial storage block comprises the step structure;

and forming an isolation structure in the first isolation groove.

18. The method of manufacturing according to claim 15, further comprising:

forming a second isolated sub-portion extending along the first direction and penetrating the initial stacked structure;

forming a first sub-separation groove, a second sub-separation groove and a second separation groove which extend along the first direction and penetrate through the initial stacking structure; along the first direction, the first sub-partition groove and the second sub-partition groove are respectively contacted with two ends of the second isolating sub-portion; the second isolation sub-portions are arranged in the first direction and the second direction;

forming a first isolated sub-part in the first sub-groove, a third isolated sub-part in the second sub-groove, and a second isolated structure in the second sub-groove;

wherein the first, third and second isolated subsections constitute at least part of a first isolation structure.

19. The method of manufacturing according to claim 15, further comprising:

forming a plurality of second stops on one side of the barrier layer far away from the step structure; the plurality of second stopping portions are arranged along the first direction, and the plurality of second stopping portions are positioned on a plurality of steps of the other step structures except the step structure provided with the first stopping portion; each second stop is located on one of the steps.

20. The method of manufacturing according to claim 15, further comprising:

forming a plurality of third separation grooves extending along the first direction; the third separating groove penetrates through the second stopping part and the initial stacking structure; each of the third slots comprises a plurality of third sub-slots separated from each other along the first direction;

and forming a grid line isolation structure in the third separation groove.

21. The method of any one of claims 15 to 20, wherein the forming a plurality of contact pillars comprises:

etching the protective layer to the first stop part to form a plurality of contact holes;

etching the first stop part exposed by the contact hole, and the barrier layer and the dielectric layer below the first stop part to expose the gate layer from the contact hole;

and forming a contact pillar in the contact hole.

22. A storage system, comprising: a controller, and the three-dimensional memory of any one of claims 1-14;

the controller is coupled to the three-dimensional memory and is used for controlling the three-dimensional memory to store data.

23. An electronic device, characterized in that the electronic device comprises: a storage system according to claim 22.

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