CN114624970B - Deviation correcting and aligning method for exposure process of direct-writing lithography machine - Google Patents
Deviation correcting and aligning method for exposure process of direct-writing lithography machine Download PDFInfo
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- CN114624970B CN114624970B CN202210158742.1A CN202210158742A CN114624970B CN 114624970 B CN114624970 B CN 114624970B CN 202210158742 A CN202210158742 A CN 202210158742A CN 114624970 B CN114624970 B CN 114624970B
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- 238000000034 method Methods 0.000 title claims abstract description 56
- 238000001459 lithography Methods 0.000 title claims abstract description 10
- 230000009466 transformation Effects 0.000 claims description 38
- 238000005192 partition Methods 0.000 claims description 15
- 238000001259 photo etching Methods 0.000 claims description 6
- 239000013598 vector Substances 0.000 claims description 4
- RPNUMPOLZDHAAY-UHFFFAOYSA-N Diethylenetriamine Chemical compound NCCNCCN RPNUMPOLZDHAAY-UHFFFAOYSA-N 0.000 claims description 2
- 238000004519 manufacturing process Methods 0.000 abstract description 4
- 238000010586 diagram Methods 0.000 description 6
- 238000006073 displacement reaction Methods 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000012858 packaging process Methods 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
Classifications
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F9/00—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically
- G03F9/70—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically for microlithography
- G03F9/7003—Alignment type or strategy, e.g. leveling, global alignment
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/70—Microphotolithographic exposure; Apparatus therefor
- G03F7/70383—Direct write, i.e. pattern is written directly without the use of a mask by one or multiple beams
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/70—Microphotolithographic exposure; Apparatus therefor
- G03F7/70425—Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
- G03F7/70466—Multiple exposures, e.g. combination of fine and coarse exposures, double patterning or multiple exposures for printing a single feature
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- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
Abstract
The invention relates to the field of direct-writing lithography machines, and discloses a deviation correcting and aligning method for a direct-writing lithography machine, which can improve productivity in a mode of reducing chip mounting accuracy, correct deviation of offset generated during chip mounting through a medium layer, has wider requirements on chip mounting accuracy, does not influence production yield, ensures normal chip functions, and can solve the problem of high-accuracy chip mounting machine productivity.
Description
Technical Field
The invention relates to the field of direct-writing lithography machines, in particular to a deviation correcting and aligning method for a direct-writing lithography machine.
Background
With the shrinking size of semiconductor chips, the semiconductor display MiniLED is developed to MicroLED, and the requirements on chip packaging patch accuracy are higher and higher due to the improvement of functional density and the shortening of interconnection length, which is at most 3-5 um at present. If the requirements for the patch accuracy are too high, the productivity is reduced; if the patch accuracy is too low, it may lead to functional failure.
The invention provides a deviation rectifying and aligning method for a direct-writing photoetching machine, which solves the problems that chip mounting accuracy and productivity are difficult to be compatible and chip mounting accuracy is bottleneck.
Disclosure of Invention
In order to solve the technical problems, the invention provides a deviation rectifying and aligning method for a direct writing lithography machine.
In order to solve the technical problems, the invention adopts the following technical scheme:
a deviation rectifying and aligning method for exposure process of direct writing lithography machine,
Wherein the exposure process comprises a first exposure process and a second exposure process; in the first exposure procedure, the dielectric layer is aligned with the chip layer, and the first condition is required to be satisfied: the maximum alignment center distance d1 between the dielectric layer pattern and the chip layer pattern is smaller than JE1; in the second exposure procedure, the circuit layer is aligned with the dielectric layer, and the second condition is required to be satisfied: the maximum alignment center distance d2 between the circuit layer pattern and the dielectric layer pattern is less than JE2; in the second exposure process, the circuit layer pattern only undergoes rigid transformation; JE1 and JE2 are set threshold values; { Die 1,Die2,…Dien } is n chips to be interconnected, and m pairs of sites exist on each chip;
the deviation rectifying and aligning method comprises the following steps:
Step one: measuring the coordinates of m opposite sites on each chip, and calculating to obtain the central coordinates of each chip and the angle error caused by the patch;
Step two: carrying out partition rigid transformation on the medium layers corresponding to the chips: calculating the medium layer partition rigidity transformation parameters corresponding to the chips according to the central coordinates and the angle errors of the chips, wherein the medium layer partition rigidity transformation parameters comprise rotation angles and translation vectors;
Step three: continuously correcting the rigidity transformation parameters of the medium layer partitions corresponding to the chips until the first exposure procedure meets the first condition;
step four: and carrying out global rigid transformation on the circuit layers corresponding to the chips: calculating a global rigidity transformation parameter of the circuit layer, if the global rigidity transformation parameter of the circuit layer can enable the second exposure procedure to meet the second condition, finishing the deviation correction of the medium layer, and exposing the medium layer; the line layer global rigid transformation parameters include rotation angles and translation vectors.
The partition rigid transformation of the dielectric layers means that the dielectric layers corresponding to the chips adopt independent rigid transformation parameters; the global rigidity transformation of the circuit layers means that the circuit layers corresponding to the chips adopt the same rigidity transformation parameters.
Specifically, in the invention, two chips which need to be interconnected are shared, and four opposite sites exist on each chip, and the coordinates of the opposite sites are the actual coordinates of the opposite sites.
Specifically, the threshold JE1 is set according to the overlay accuracy of the dielectric layer pattern; the threshold JE2 is set according to the overlay accuracy of the circuit layer.
Compared with the prior art, the invention has the beneficial technical effects that:
In the traditional mask photoetching machine manufacturing process, once the mask plate pattern structure is determined, the mask plate pattern structure can not be adjusted and changed in real time, the direct-writing photoetching machine applying the correction algorithm plays a certain role, the productivity can be improved in a manner of reducing the chip mounting precision, the deviation amount generated during chip mounting is corrected through a medium layer, the requirement on the chip mounting precision is wider, meanwhile, the production yield is not influenced, the chip function is ensured to be normal, and the problem of the productivity of the high-precision chip mounter can be solved.
Drawings
FIG. 1 is a flow chart of the method for correcting and aligning deviation according to the present invention;
FIG. 2 is a schematic diagram of two-dimensional rectification of two chips according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of the center-to-center distances between the dielectric layer pattern and the chip layer pattern and between the dielectric layer pattern and the circuit layer pattern in the exposure process;
FIG. 4 is a graph showing tolerance constraints in an embodiment of the present invention;
FIG. 5 is a schematic diagram of the theoretical relative positions of two chips according to the present invention;
FIG. 6 is a schematic diagram showing the actual relative positions of two chip patches according to the present invention;
FIG. 7 is a schematic diagram of theoretical relative positions of dielectric layers after a first iteration of the present invention;
FIG. 8 is a schematic diagram of an iterative rectification of a dielectric layer of the present invention.
Detailed Description
A preferred embodiment of the present invention will be described in detail with reference to the accompanying drawings.
As shown in fig. 3, in the Micro LED packaging process, after the chip mounting is completed, the dielectric layer is exposed by using a photo-etching machine, and after a series of process steps, the circuit layer is continuously exposed. In the two exposure processes, the basic conditions that need to be satisfied are typically:
1) Condition one: in the first exposure process, the dielectric layer is aligned with the chip layer, the requirement that the alignment of the dielectric layer pattern and the chip layer pattern is accurate enough is satisfied, and the worst case is tangent, so that after the first exposure process, the maximum alignment center distance d1 between the dielectric layer pattern and the chip layer pattern is smaller than a threshold JE1.
2) Condition II: a second exposure process: the circuit layer is aligned with the medium layer, the requirements of the alignment precision of the circuit layer pattern and the medium layer pattern are required to be met, the worst condition is tangential, and after the second exposure procedure, the maximum alignment center distance d2 between the circuit layer pattern and the medium layer pattern is required to be smaller than a threshold JE2.
3) And (3) a third condition: the line layer pattern cannot be expanded or contracted during the second exposure process, and must be rigidly transformed (i.e., can only be rotated or translated).
The specific expression of the rigid transformation referred to in the present invention is represented using the following matrix operation:
Wherein x 'and y' are transformed chuck coordinates, x and y are theoretical coordinates of graphic data, θ is a rotation angle, and tx and ty are translation.
The deviation rectifying and aligning method of the invention ensures that the three conditions are simultaneously satisfied through the deviation rectifying of the dielectric layer.
In the invention, if the data (medium layer and circuit layer) of each layer corresponding to each chip adopts the same transformation parameters, the data is defined as global transformation; if each layer of data corresponding to each chip adopts independent transformation parameters, the data is defined as partition transformation.
The principle of the deviation rectifying and aligning method in the invention is introduced by using two chips which need to be interconnected as examples, the two chips are Die1 and Die2 respectively,
Let Die1 and Die2 be at a theoretical distance L 0 in the x-direction and 0 in the y-direction. The relative positional relationship is schematically shown in fig. 5.
Due to the patch error, the actual relative positional relationship of the two Die deviates from the theory, and the actual patch situation may be as shown in fig. 6. Due to the patch error, the Die1 actual angle is rotated counter-clockwise by eθ1 relative to the theoretical position, and the Die2 actual angle is rotated clockwise by eθ2 relative to the theoretical position. The direction shown in the axis aa' is the direction of the average of the angles of the two chips (note: not the y direction in the coordinate system). L is the length of the connecting line of the central points of the two chips, the projection length of the connecting line in the mean value angle direction is Lh, and the projection length of the connecting line in the direction perpendicular to the mean value angle direction is Lw.
In the exposure process of the traditional mask photoetching machine, the overlay result exceeds the index due to the patch error, and the chip functions are invalid. In a direct-writing lithography machine, the dielectric layer can perfectly solve the problem by correcting the deviation.
From the above known quantities, the initial rigidity transformation parameters (partition transformation, including only rotation and translation) of each of the two-chip dielectric layer theoretical graphic data (GDS coordinates) can be obtained. And converting and inputting the theoretical GDS coordinates of the dielectric layers into theoretical chuck (control moving stage) coordinates of two chip dielectric layers to be exposed. The first iteration exposes the two chip dielectric layers to a theoretical relative positional relationship, as shown in fig. 7. The theoretical medium layer chuck coordinate after the first iteration should satisfy the ideal relative position relation. In particular, in terms of angle, the two chip dielectric layer patterns are now parallel and along the two chip patch angle error mean direction (aa', not the y direction). In terms of distance, the two patterns are separated by 0 in the aa 'direction and by L 0 in the direction perpendicular to aa'.
Obviously, if the first iteration is performed and the first condition is satisfied, in the second exposure process (global transformation of the circuit layer to the dielectric layer), the second exposure process will be perfectly aligned (without considering the alignment error of the stage itself) because the pattern of the dielectric layer is in an ideal positional relationship. However, in actual production, the first iteration usually makes the condition one unsatisfied. For this purpose, the deviation-correcting alignment method mentioned in this patent provides an iterative method that minimizes the theoretical alignment error of condition two when the condition is established. If the second condition is not satisfied, the deviation rectifying operation cannot be completed. Otherwise, the correction is successful. Global stiffness transformation should be used in the second exposure process to ensure that no collapsible deformation of the line layer pattern occurs. The theoretical accuracy limits of the two exposure processes are determined by threshold conditions JE1 and JE 2. Fig. 8 shows the position after the first iteration, the final position after the iteration is completed, and the actual chip mounting position in the process of rectifying the dielectric layer.
The iterative method is set forth below.
When the first iteration condition is not met, the two dielectric layer patterns after the first iteration are respectively approximated to the actual patch positions of Die1 and Die 2. Through successive approximation, a certain iteration exists, and the alignment result of the dielectric layer pattern and the chip layer can just meet the first condition. Firstly, setting the angle iteration step delta theta, calculating the needed iteration times n when the pattern of the dielectric layer is iterated from the theoretical position relation to the actual patch position relation,
n＝θ0/Δθ；
Θ 0 is the total amount of angle iterations. Further calculating the iteration step length of Lw and Lh according to the iteration times
ΔLw＝(Lw-L0)/n；
ΔLh＝Lh/n；
When the angle displacement iteration satisfies the relation, the correction and alignment method can be ensured to have a solution. It should be noted that, when the dielectric layer pattern iterates (the dielectric layers are subjected to partition rigid transformation), the dielectric layer pattern portions corresponding to the two chips iterate towards the direction of the actual patch position relationship (the iteration amounts are opposite in sign and equal in size). In addition, when the theoretical chuck coordinates of the dielectric layer are calculated each time, the angle is calculated first, and then the displacement (vector) is calculated.
In this embodiment, each chip has 4 pairs of points, and only the correction state of a certain pair of points of Die1 is shown in fig. 2. As shown in fig. 1, the implementation steps of the deviation rectifying and aligning method are described in detail as follows:
1) Firstly, measuring actual chuck (control moving carrier) coordinates of 8 opposite sites of Die1 and Die 2;
2) Calculating to obtain the center coordinates of the two chips and the angle errors caused by the patches respectively;
3) According to the parameters, initializing medium layer partition rigidity transformation parameters (TD 1 and TD 2) of two chips: rotation angle, displacement in x-direction and y-direction;
4) Continuously iterating partition rigid transformation parameters of the corresponding medium layers of the two chips to meet a first condition;
5) When the condition is met, calculating a global rigidity transformation parameter TD3 of the circuit layer, and judging whether a theoretical exposure result of the circuit layer meets a condition II;
6) And when the second condition is not met, prompting that the medium layer fails to rectify, otherwise prompting that the medium layer succeeds in rectify, and exposing the medium layer.
When actual correction is performed, threshold values JE1 and JE2 are reasonably set according to the alignment precision requirement of the medium layer and the circuit layer.
The following table shows the actual patch errors for two chips:
| Error term | Die1 | Die2 |
| X-direction error Ex/um | 9.5 | 21.8 |
| Y-direction error Ey/um | -1 | -18 |
| Angle error Eth/degree | 0.0143 | 0.0215 |
After the deviation rectifying and aligning method in the invention is applied, the maximum alignment error of the dielectric layer is 7.48um, the maximum alignment error of the circuit layer is 6.74um, and the alignment error of the machine is ignored. Therefore, after the deviation rectifying and aligning method is used, the tolerance to the patch errors is greatly improved.
When the tolerance of Ex and Ey is mutually restricted for a given angle error, fig. 4 shows the tolerance restriction curves for displacement errors in the x-direction and y-direction for two chip angle errors of 0.03 degrees and-0.03 degrees, respectively.
It will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein.
Furthermore, it should be understood that although the present disclosure describes embodiments, not every embodiment is provided with a single embodiment, and that this description is provided for clarity only, and that the disclosure is not limited to specific embodiments, and that the embodiments may be combined appropriately to form other embodiments that will be understood by those skilled in the art.
Claims (2)
1. A deviation rectifying and aligning method for an exposure process of a direct writing lithography machine is characterized in that:
Wherein the exposure process comprises a first exposure process and a second exposure process; in the first exposure procedure, the dielectric layer is aligned with the chip layer, and the first condition is required to be satisfied: the maximum alignment center distance d1 between the dielectric layer pattern and the chip layer pattern is smaller than JE1; in the second exposure procedure, the circuit layer is aligned with the dielectric layer, and the second condition is required to be satisfied: the maximum alignment center distance d2 between the circuit layer pattern and the dielectric layer pattern is less than JE2; in the second exposure process, the circuit layer pattern only undergoes rigid transformation; JE1 and JE2 are set threshold values; { Die 1,Die2,…Dien } is n chips to be interconnected, and m pairs of sites exist on each chip;
the deviation rectifying and aligning method comprises the following steps:
Step one: measuring the coordinates of m opposite sites on each chip, and calculating to obtain the central coordinates of each chip and the angle error caused by the patch;
Step two: carrying out partition rigid transformation on the medium layers corresponding to the chips: calculating the medium layer partition rigidity transformation parameters corresponding to the chips according to the central coordinates and the angle errors of the chips, wherein the medium layer partition rigidity transformation parameters comprise rotation angles and translation vectors;
Step three: continuously correcting the rigidity transformation parameters of the medium layer partitions corresponding to the chips until the first exposure procedure meets the first condition;
Step four: and carrying out global rigid transformation on the circuit layers corresponding to the chips: calculating a global rigidity transformation parameter of the circuit layer, if the global rigidity transformation parameter of the circuit layer can enable the second exposure procedure to meet the second condition, finishing the deviation correction of the medium layer, and exposing the medium layer;
the partition rigid transformation of the dielectric layers means that the dielectric layers corresponding to the chips adopt independent rigid transformation parameters; the global rigidity transformation of the circuit layers means that the circuit layers corresponding to the chips adopt the same rigidity transformation parameters.
2. The method for correcting and aligning the exposure process of the direct-writing photoetching machine according to claim 1, which is characterized in that: the threshold JE1 is set according to the overlay accuracy of the dielectric layer; the threshold JE2 is set according to the overlay accuracy of the circuit layer.
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001274073A (en) * | 2000-03-28 | 2001-10-05 | Toshiba Corp | Method and system for overlay exposure |
| CN110083020A (en) * | 2019-03-01 | 2019-08-02 | 安徽工程大学 | A kind of method of different machine alignment precision optimization |
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| JP2009200122A (en) * | 2008-02-19 | 2009-09-03 | Canon Inc | Exposure system and process for fabricating device |
| JP2010278041A (en) * | 2009-05-26 | 2010-12-09 | Toshiba Corp | Method of forming template for imprinting and imprinting method using the template |
| JP5864762B2 (en) * | 2011-10-07 | 2016-02-17 | カール・ツァイス・エスエムティー・ゲーエムベーハー | Method for controlling movement of optical elements of a lithography system |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001274073A (en) * | 2000-03-28 | 2001-10-05 | Toshiba Corp | Method and system for overlay exposure |
| CN110083020A (en) * | 2019-03-01 | 2019-08-02 | 安徽工程大学 | A kind of method of different machine alignment precision optimization |
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