CN114567614A - Method and device for realizing ARP protocol processing based on FPGA - Google Patents
Method and device for realizing ARP protocol processing based on FPGA Download PDFInfo
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- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L61/00—Network arrangements, protocols or services for addressing or naming
- H04L61/09—Mapping addresses
- H04L61/10—Mapping addresses of different types
- H04L61/103—Mapping addresses of different types across network layers, e.g. resolution of network layer into physical layer addresses or address resolution protocol [ARP]
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y02D30/00—Reducing energy consumption in communication networks
- Y02D30/50—Reducing energy consumption in communication networks in wire-line communication networks, e.g. low power modes or reduced link rate
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Abstract
The invention discloses a method and a device for realizing ARP protocol processing based on FPGA, wherein the method receives a network data packet through an initialized MAC interface, identifies the type of the network data packet and correspondingly processes the identification result. The invention undertakes the ARP protocol processing process through FPGA hardware, reduces the occupation of the CPU time by the ARP protocol processing process, and can also prevent the impact of ARP flooding attack on the CPU; the ARP protocol is processed in a FPGA hardware mode, so that the ARP resolution response speed can be increased, and the IP data sending delay can be reduced; the ARP protocol is processed in a FPGA hardware mode, on one hand, the whole ARP protocol processing flow is solidified by the FPGA and can not be modified; on the other hand, the MAC address mapping table is realized in the FPGA, is not in the system memory and cannot be tampered by software, so that the safety of the network system is improved.
Description
Technical Field
The invention relates to a method and a device for realizing ARP protocol processing based on FPGA, belonging to the technical field of computer network communication.
Background
An FPGA (field Programmable Gate array) field Programmable Gate array is a product developed further on the basis of Programmable devices such as PAL (Programmable array logic), GAL (general array logic) and the like, and appears as a semi-custom circuit in the field of Application Specific Integrated Circuits (ASICs), thereby not only solving the defects of the custom circuit, but also overcoming the defect of limited Gate circuits of the original Programmable devices.
The ARP (address Resolution protocol) protocol is a basic network protocol, the operation of which is generally transparent to an application program or a system, and is usually implemented in a network protocol stack of an operating system, and a CPU executes a specific software module to implement ARP protocol processing, and places the Resolution result in a device memory for caching.
At present, when a network device processes an ARP message, system resources, including CPU time and memory space, need to be occupied, and meanwhile, because of the requirements of system memory access and MAC table lookup efficiency, security and lookup efficiency of caching an MAC address table in a memory during the operation of the network system are very critical.
Disclosure of Invention
Therefore, the invention provides a method and a device for realizing ARP protocol processing based on FPGA, which realize the ARP protocol processing in a FPGA hardware mode and solve the problems of safety and efficiency in the traditional pure software mode for ARP processing.
In order to achieve the above purpose, the invention provides the following technical scheme: in a first aspect, a method for implementing ARP protocol processing based on FPGA is provided, which includes the following steps:
s001: resetting and initializing operation parameters of the FPGA module, wherein the operation parameters comprise a network interface, a local address, the number of cache entries, aging time and whether a high-speed expansion interface is started or not of the FPGA;
s002: receiving a network data packet through an initialized MAC interface, performing type identification on the network data packet, and if the network data packet is a normal data communication IP packet, turning to S101 for processing;
s101: analyzing the network data packet into a normal data communication IP packet, and turning to S102;
s102: the address retrieval unit searches a destination MAC address entry of the network data packet in the MAC address mapping table, and goes to S103;
s103: and judging the search result of S102: if the destination MAC address entry exists, go to S104; otherwise go to S105;
s104: delivering the target MAC address entry and the network data packet to a subsequent processing logic;
s105: the trigger request sending unit generates a corresponding ARP request packet, performs a request process of a target MAC address, and goes to S106;
s106: and broadcasting the ARP request packet through the communication interface and sending the ARP request to the target equipment.
As a preferred scheme of implementing ARP protocol processing based on FPGA, in S002, if the network data packet is an ARP reply packet, the process goes to S201:
s201: receiving the ARP response packet of the target equipment, and turning to S202;
s202: the response processing unit analyzes the ARP response packet data, extracts address information and transfers to S203;
s203: and refreshing the MAC address mapping table and writing the newly added entries into the table entries.
As a preferred scheme of implementing ARP protocol processing based on FPGA, in S002, if the network data packet is an ARP request packet, the process goes to S301:
s301: receiving an ARP request packet of the target device, and turning to S302;
s302: judging whether the request is a request for resolving the IP address of the local machine: if the IP of the local computer is the IP, the S304 is switched to; otherwise go to S303;
s303: directly ending the treatment;
s304: triggering a response processing unit to generate a corresponding ARP response packet, filling the MAC address of the local machine into the ARP response packet, and turning to S305;
s305: and sending an ARP response packet to the target equipment through the network communication port receiving the ARP request packet.
As a preferred scheme of the method for implementing ARP protocol processing based on FPGA, in S001, an unused MAC address entry within a preset time is deleted at regular time according to a set aging policy.
In a second aspect, a device for implementing ARP protocol processing based on FPGA is provided, where the method for implementing ARP protocol processing based on FPGA according to the first aspect or any possible implementation manner includes:
the parameter configuration unit is used for resetting and initializing operation parameters of the FPGA module, wherein the operation parameters comprise a network interface, a local address, the number of cache entries, aging time and whether a high-speed expansion interface is started or not of the FPGA;
the data identification unit is used for receiving a network data packet through the initialized MAC interface and identifying the type of the network data packet;
the address retrieval unit is used for searching a target MAC address entry of the network data packet in an MAC address mapping table if the network data packet is a normal data communication IP packet;
the search judging unit is used for judging the search result and judging whether the MAC address mapping table has a target MAC address item;
the first sending unit is used for the MAC address mapping table to have a destination MAC address entry and delivering the destination MAC address entry and the network data packet to a subsequent processing logic;
and the second sending unit is used for generating a corresponding ARP request packet if the MAC address mapping table has no destination MAC address entry, performing a request process of a destination MAC address, broadcasting the ARP request packet through the communication interface, and sending an ARP request to the target equipment.
The device for realizing the ARP protocol processing based on the FPGA further comprises a response processing unit, if the network data packet is an ARP response packet, the response processing unit analyzes the ARP response packet data, extracts address information, refreshes an MAC address mapping table and writes newly added entries into the table entry.
The device for realizing the ARP protocol processing based on the FPGA preferably further comprises an analysis judging unit used for judging whether the network data packet is an ARP request packet or not, and the ARP request packet is a request for analyzing the local IP address.
The device for realizing the ARP protocol processing based on the FPGA preferably further comprises an ending processing unit used for directly ending the processing when judging that the device is not a request for analyzing the local IP address.
The preferred scheme of the device for realizing the ARP protocol processing based on the FPGA further comprises a response processing unit, wherein the response processing unit is used for generating a corresponding ARP response packet when judging that the request for analyzing the local IP address is received, filling the local MAC address into the ARP response packet, and sending the ARP response packet to the target device through the network communication port receiving the ARP request packet.
The device for realizing the ARP protocol processing based on the FPGA preferably further comprises an aging control unit, wherein the aging control unit is used for deleting unused MAC address entries in preset time at regular time according to a set aging strategy.
The invention has the following advantages: the FPGA hardware is used for bearing the ARP protocol processing process, so that the occupation of the ARP protocol processing process on the CPU time is reduced, and the impact of ARP flooding attack on the CPU can be prevented; the ARP protocol is processed in a FPGA hardware mode, so that the ARP resolution response speed can be increased, and the IP data sending delay can be reduced; the ARP protocol is processed in a FPGA hardware mode, on one hand, the whole ARP protocol processing flow is solidified by the FPGA and can not be modified; on the other hand, the MAC address mapping table is realized in the FPGA, is not in the system memory and cannot be tampered by software, so that the safety of the network system is improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below. It should be apparent that the drawings in the following description are merely exemplary, and that other embodiments can be derived from the drawings provided by those of ordinary skill in the art without inventive effort.
The structures, ratios, sizes, and the like shown in the present specification are only used for matching with the contents disclosed in the specification, so that those skilled in the art can understand and read the present invention, and do not limit the conditions for implementing the present invention, so that the present invention has no technical significance, and any structural modifications, changes in the ratio relationship, or adjustments of the sizes, without affecting the functions and purposes of the present invention, should still fall within the scope of the present invention.
Fig. 1 is a schematic flow chart of a method for implementing ARP protocol processing based on FPGA according to embodiment 1 of the present invention;
fig. 2 is a schematic diagram of an apparatus for implementing ARP protocol processing based on FPGA according to embodiment 2 of the present invention.
Detailed Description
The present invention is described in terms of particular embodiments, other advantages and features of the invention will become apparent to those skilled in the art from the following disclosure, and it is to be understood that the described embodiments are merely exemplary of the invention and that it is not intended to limit the invention to the particular embodiments disclosed. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Example 1
Referring to fig. 1, embodiment 1 of the present invention provides a method for implementing ARP protocol processing based on FPGA, including the following steps:
s001: resetting and initializing operation parameters of the FPGA module, wherein the operation parameters comprise a network interface, a local address, the number of cache entries, aging time and whether a high-speed expansion interface is started or not of the FPGA;
s002: receiving a network data packet through an initialized MAC interface, performing type identification on the network data packet, and if the network data packet is a normal data communication IP packet, turning to S101 for processing;
s101: analyzing the network data packet into a normal data communication IP packet, and turning to S102;
s102: the address retrieval unit searches a destination MAC address entry of the network data packet in the MAC address mapping table, and goes to S103;
s103: and judging the search result of S102: if the destination MAC address entry exists, go to S104; otherwise go to S105;
s104: delivering the target MAC address entry and the network data packet to a subsequent processing logic;
s105: the trigger request sending unit generates a corresponding ARP request packet, performs a request process of a target MAC address, and goes to S106;
s106: and broadcasting an ARP request packet through the communication interface and sending an ARP request to the target equipment.
Specifically, after the FPGA module is powered on, the FPGA module completes reset, receives a configuration management instruction, initializes operating parameters such as a network interface, a local address, a cache entry number, aging time, whether a high-speed expansion interface is enabled, and receives a network data packet through an initialized MAC interface, performs type identification on the network data packet, and if the network data packet is a normal data communication IP packet, an address retrieval unit searches a destination MAC address entry of the network data packet in an MAC address mapping table, and determines a search result: if the destination MAC address entry exists, the destination MAC address entry and the network data packet are delivered to a subsequent processing logic; if the target MAC address item does not exist, the trigger request sending unit generates a corresponding ARP request packet, the request process of the target MAC address is carried out, the ARP request packet is broadcasted through the communication interface, and the ARP request is sent to the target equipment.
In this embodiment, in S002, if the network data packet is an ARP reply packet, the process goes to S201:
s201: receiving the ARP response packet of the target equipment, and turning to S202;
s202: the response processing unit analyzes the ARP response packet data, extracts address information and transfers to S203;
s203: and refreshing the MAC address mapping table and writing the newly added entries into the table entries.
Specifically, if the network data packet is an ARP reply packet, the reply processing unit parses the ARP reply packet data, extracts address information, refreshes an MAC address mapping table, and writes the newly added entry into the table entry.
In this embodiment, in S002, if the network data packet is an ARP request packet, the process goes to S301:
s301: receiving an ARP request packet of the target device, and turning to S302;
s302: judging whether the request is a request for resolving the IP address of the local machine: if the IP of the local computer is the IP, the S304 is switched to; otherwise go to S303;
s303: directly ending the treatment;
s304: triggering a response processing unit to generate a corresponding ARP response packet, filling the MAC address of the local machine into the ARP response packet, and turning to S305;
s305: and sending an ARP response packet to the target equipment through the network communication port which receives the ARP request packet.
Specifically, if the network data packet is an ARP request packet, it is determined whether the network data packet is a request for resolving an IP address of the local computer: if the IP address is the local IP, triggering a response processing unit to generate a corresponding ARP response packet, filling the MAC address of the local into the ARP response packet, and sending the ARP response packet to the target equipment through the network communication port receiving the ARP request packet; if not, directly ending the process
In this embodiment, in S001, according to the set aging policy, the unused MAC address entry within the preset time is deleted at regular time. According to the set aging strategy, the unused address entries in the MAC address mapping table within a period of time are deleted at regular time, so that the new address entries can be stored, and the effective utilization of RAM space is realized.
In summary, in the present invention, after the FPGA module is powered on, the FPGA module completes reset, receives a configuration management instruction, initializes the network interface, the local address, the number of cache entries, the aging time, and whether to enable the high-speed expansion interface of the FPGA, receives the network data packet through the initialized MAC interface, performs type identification on the network data packet, if the network data packet is a normal data communication IP packet, the address retrieval unit searches for a destination MAC address entry of the network data packet in the MAC address mapping table, and determines a search result: if the destination MAC address entry exists, the destination MAC address entry and the network data packet are delivered to a subsequent processing logic; if the target MAC address item does not exist, the trigger request sending unit generates a corresponding ARP request packet, the request process of the target MAC address is carried out, the ARP request packet is broadcasted through the communication interface, and the ARP request is sent to the target equipment. If the network data packet is an ARP response packet, the response processing unit analyzes the ARP response packet data, extracts address information, refreshes an MAC address mapping table and writes newly-added entries into the table entry. If the network data packet is an ARP request packet, judging whether the network data packet is a request for analyzing the IP address of the local machine: if the IP address is the local IP, triggering a response processing unit to generate a corresponding ARP response packet, filling the MAC address of the local into the ARP response packet, and sending the ARP response packet to the target equipment through the network communication port receiving the ARP request packet; if not, the process is directly ended. In addition, according to a set aging strategy, address entries which are not used in a period of time in the MAC address mapping table are deleted at regular time, so that new address entries can be stored, and effective utilization of RAM space is realized. The invention undertakes the ARP protocol processing process through FPGA hardware, reduces the occupation of the CPU time by the ARP protocol processing process, and can also prevent the impact of ARP flooding attack on the CPU; the ARP protocol is processed in a FPGA hardware mode, so that the ARP resolution response speed can be increased, and the IP data sending delay can be reduced; the ARP protocol is processed in a FPGA hardware mode, on one hand, the whole ARP protocol processing flow is solidified by the FPGA and can not be modified; on the other hand, the MAC address mapping table is realized in the FPGA, is not in the system memory and cannot be tampered by software, so that the safety of the network system is improved.
Example 2
Referring to fig. 2, an embodiment 2 of the present invention further provides a device for implementing ARP protocol processing based on FPGA, and a method for implementing ARP protocol processing based on FPGA in embodiment 1 or any possible implementation manner thereof is adopted, where the method includes:
the parameter configuration unit 1 is used for resetting and initializing operation parameters of the FPGA module, wherein the operation parameters comprise a network interface, a local address, the number of cache entries, aging time and whether a high-speed expansion interface is started or not of the FPGA;
the data identification unit 2 is used for receiving a network data packet through the initialized MAC interface and identifying the type of the network data packet;
the address retrieval unit 3 is configured to search a destination MAC address entry of the network data packet in an MAC address mapping table if the network data packet is a normal data communication IP packet;
a retrieval judging unit 4, configured to judge a search result, and judge whether a destination MAC address entry exists in the MAC address mapping table;
a first sending unit 5, configured to send a destination MAC address entry in the MAC address mapping table and to deliver the destination MAC address entry and the network data packet to a subsequent processing logic;
and the second sending unit 6 is configured to generate a corresponding ARP request packet if the MAC address mapping table does not have a destination MAC address entry, perform a request process of a destination MAC address, broadcast the ARP request packet through the communication interface, and send an ARP request to the target device.
In this embodiment, the apparatus further includes a response processing unit 7, and if the network data packet is an ARP response packet, the response processing unit analyzes the ARP response packet data, extracts address information, refreshes an MAC address mapping table, and writes the newly added entry into the table entry.
In this embodiment, the present invention further includes an analysis determining unit 8, configured to determine whether the network data packet is an ARP request packet.
In this embodiment, the apparatus further includes an end processing unit 9 configured to directly end the processing when it is determined that the request is not a request for resolving the local IP address.
In this embodiment, the apparatus further includes a response processing unit 10, configured to generate a corresponding ARP reply packet when determining that the request for resolving the local IP address is received, fill the local MAC address into the ARP reply packet, and send the ARP reply packet to the target device through the network communication port that receives the ARP request packet.
In this embodiment, the apparatus further includes an aging control unit 11, configured to delete an unused MAC address entry within a preset time at regular time according to a set aging policy.
In this embodiment, the MAC address mapping table is implemented by a RAM and is used for storing MAC address mapping entries.
In this embodiment, a CPU interface unit 12 is further configured to implement communication with the CPU, receive CPU parameter configuration and read/write operations, and access registers and memory spaces of each internal unit module.
In this embodiment, a high-speed communication interface unit 13 is further configured to perform cascade communication among the plurality of FPGAs, convert the interconnection bus into high-speed SerDes communication, and implement processing capacity and function expansion.
In the embodiment, the interconnection of each internal functional module is realized through an interconnection bus; caching the network data packet through the storage unit 14; and the network PHY is connected with the MAC interface to realize the receiving and sending of the network data packet.
The invention can be widely applied to various network communication devices or computer hosts. In an IP network data processing equipment system for realizing an ARP protocol processing device based on an FPGA, the system comprises an FPGA SoC chip, a DDR4 internal memory, a network PHY chip, FLASH storage, a power supply, a clock, a plurality of network interface connectors and the like.
FPGA SoC chip: the method is realized by selecting 1 fusion SoC chip XCZU7EV of Xilinx company, and an FPGA processor core and an ARM processor core are integrated inside. The FPGA realizes the transceiving and processing of network data, and realizes the ARP protocol processing function at the same time; the ARM processor realizes the configuration and management of the FPGA part through an internal AXI bus.
DDR4 memory: 4 MTMT40A256M16 chips are selected as DDR4, and the chips are used as an internal memory part for running an ARM processor of an FPGA SoC chip and are used as a memory for running system software and an application program.
Network PHY chip: a plurality of RTL8211 kilomega network PHY circuits are selected to realize the network PHY circuit, are used for network communication of a physical link layer, are connected with an FPGA SoC chip through an RGMII protocol and receive and transmit network data.
And (4) FLASH storage: 1 MT25QU256ABA chip and a FLASH memory are selected as a persistent storage part for running an ARM processor of the FPGA SoC chip and used for persistently keeping system software, a file system and an application program, and data are guided and read from the persistent storage part after the system is powered on.
It should be noted that, because the contents of information interaction, execution process, and the like between the modules/units of the apparatus are based on the same concept as the method embodiment in embodiment 1 of the present application, the technical effect brought by the contents is the same as the method embodiment of the present application, and specific contents may refer to the description in the foregoing method embodiment of the present application, and are not described herein again.
Example 3
The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device, such as a server, a data center, etc., that incorporates one or more of the available media. The usable medium may be a magnetic medium (e.g., floppy Disk, hard Disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., Solid State Disk (SSD)), among others.
Example 4
An embodiment 4 of the present invention provides an electronic device, including: a memory and a processor;
the processor and the memory are communicated with each other through a bus; the memory stores program instructions executable by the processor, and the processor calls the program instructions to execute the method for implementing the ARP protocol processing based on the FPGA of embodiment 1 or any possible implementation manner thereof.
Specifically, the processor may be implemented by hardware or software, and when implemented by hardware, the processor may be a logic circuit, an integrated circuit, or the like; when implemented in software, the processor may be a general-purpose processor implemented by reading software code stored in a memory, which may be integrated with the processor, located external to the processor, or stand-alone.
In the above embodiments, all or part of the implementation may be realized by software, hardware, firmware, or any combination thereof. When implemented in software, may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When loaded and executed on a computer, cause the processes or functions described in accordance with the embodiments of the invention to occur, in whole or in part. The computer may be a general purpose computer, a special purpose computer, a network of computers, or other programmable device. The computer instructions may be stored in a computer readable storage medium or transmitted from one computer readable storage medium to another, for example, from one website site, computer, server, or data center to another website site, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, Digital Subscriber Line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.).
It will be apparent to those skilled in the art that the modules or steps of the present invention described above may be implemented by a general purpose computing device, they may be centralized in a single computing device or distributed across a network of multiple computing devices, and alternatively, they may be implemented by program code executable by a computing device, such that they may be stored in a memory device and executed by a computing device, and in some cases, the steps shown or described may be executed out of order, or separately as individual integrated circuit modules, or multiple modules or steps thereof may be implemented as a single integrated circuit module. Thus, the present invention is not limited to any specific combination of hardware and software.
Although the invention has been described in detail above with reference to a general description and specific examples, it will be apparent to one skilled in the art that modifications or improvements may be made thereto based on the invention. Accordingly, such modifications and improvements are intended to be within the scope of the invention as claimed.
Claims (10)
1. The method for realizing the ARP protocol processing based on the FPGA is characterized by comprising the following steps of:
s001: resetting and initializing operation parameters of the FPGA module, wherein the operation parameters comprise a network interface, a local address, the number of cache entries, aging time and whether a high-speed expansion interface is started or not of the FPGA;
s002: receiving a network data packet through an initialized MAC interface, performing type identification on the network data packet, and if the network data packet is a normal data communication IP packet, turning to S101 for processing;
s101: analyzing the network data packet into a normal data communication IP packet, and turning to S102;
s102: the address retrieval unit searches a destination MAC address entry of the network data packet in the MAC address mapping table, and goes to S103;
s103: and judging the search result of the S102: if the destination MAC address entry exists, go to S104; otherwise go to S105;
s104: delivering the target MAC address entry and the network data packet to a subsequent processing logic;
s105: the trigger request sending unit generates a corresponding ARP request packet, performs a request process of a destination MAC address, and goes to S106;
s106: and broadcasting an ARP request packet through the communication interface and sending an ARP request to the target equipment.
2. The method for implementing ARP protocol processing based on FPGA of claim 1, wherein in S002, if the network data packet is an ARP reply packet, go to S201 for processing:
s201: receiving the ARP response packet of the target equipment, and turning to S202;
s202: the response processing unit analyzes the ARP response packet data, extracts address information and transfers to S203;
s203: and refreshing the MAC address mapping table and writing the newly added entries into the table entries.
3. The method according to claim 1, wherein in S002, if the network packet is an ARP request packet, the process goes to S301:
s301: receiving an ARP request packet of the target device, and turning to S302;
s302: judging whether the request is a request for resolving the IP address of the local computer: if the IP of the local computer is the IP, the S304 is switched to; otherwise go to S303;
s303: directly ending the treatment;
s304: triggering a response processing unit to generate a corresponding ARP response packet, filling the MAC address of the local machine into the ARP response packet, and turning to S305;
s305: and sending an ARP response packet to the target equipment through the network communication port which receives the ARP request packet.
4. The method for implementing ARP protocol processing based on FPGA of claim 1, wherein in S001, according to a set aging policy, an unused MAC address entry within a preset time is deleted at regular time.
5. The device for realizing the ARP protocol processing based on the FPGA adopts the method for realizing the ARP protocol processing based on the FPGA of any one of claims 1 to 4, and is characterized by comprising the following steps:
the parameter configuration unit is used for resetting and initializing operation parameters of the FPGA module, wherein the operation parameters comprise a network interface, a local address, the number of cache entries, aging time and whether a high-speed expansion interface is started or not of the FPGA;
the data identification unit is used for receiving a network data packet through the initialized MAC interface and identifying the type of the network data packet;
the address retrieval unit is used for searching a target MAC address entry of the network data packet in an MAC address mapping table if the network data packet is a normal data communication IP packet;
the search judging unit is used for judging the search result and judging whether the MAC address mapping table has a target MAC address item;
the first sending unit is used for sending the target MAC address entry and the network data packet to subsequent processing logic when the target MAC address entry exists in the MAC address mapping table;
and the second sending unit is used for generating a corresponding ARP request packet if the MAC address mapping table has no destination MAC address entry, performing a request process of a destination MAC address, broadcasting the ARP request packet through the communication interface, and sending an ARP request to the target equipment.
6. The device according to claim 5, further comprising a response processing unit, wherein if the network packet is an ARP response packet, the response processing unit parses the ARP response packet data, extracts address information, refreshes the MAC address mapping table, and writes the newly added entry into the table entry.
7. The apparatus according to claim 5, further comprising an analysis determining unit, configured to determine whether the network data packet is an ARP request packet, if the network data packet is an ARP request packet, the network data packet is a request for analyzing a local IP address.
8. The apparatus according to claim 7, further comprising an end processing unit configured to directly end the processing when it is determined that the request for resolving the local IP address is not the request for resolving the local IP address.
9. The apparatus according to claim 7, further comprising a response processing unit, configured to generate a corresponding ARP reply packet when determining that the request for resolving the local IP address is received, fill the local MAC address in the ARP reply packet, and send the ARP reply packet to the target device through the network communication port that receives the ARP request packet.
10. The device for realizing ARP protocol processing based on FPGA of claim 5, further comprising an aging control unit for deleting the unused MAC address entries in the preset time at regular time according to the set aging strategy.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115297082A (en) * | 2022-08-03 | 2022-11-04 | 江苏新质信息科技有限公司 | ARP protocol processing method and system based on cooperation of FPGA and eBPF |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20130044754A1 (en) * | 2010-12-21 | 2013-02-21 | Huawei Technologies Co., Ltd. | Method, apparatus and system for acquiring media access control address |
| CN105530330A (en) * | 2015-12-07 | 2016-04-27 | 中国电子科技集团公司第十研究所 | Method for improving operation efficiency of ARP protocol in space information network |
| CN106534168A (en) * | 2016-12-06 | 2017-03-22 | 中国电子科技集团公司第三十二研究所 | TCPIP protocol stack safety processing system based on FPGA |
| CN108243262A (en) * | 2016-12-26 | 2018-07-03 | 大唐移动通信设备有限公司 | Learning method, device and the network three-layer equipment of ARP table |
| CN109951459A (en) * | 2019-03-06 | 2019-06-28 | 山东信天辰信息安全技术有限公司 | A kind of ARP spoofing attack detection method based on local area network |
| CN113872949A (en) * | 2021-09-18 | 2021-12-31 | 山东云海国创云计算装备产业创新中心有限公司 | Response method of address resolution protocol and related device |
-
2022
- 2022-03-07 CN CN202210224897.0A patent/CN114567614B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20130044754A1 (en) * | 2010-12-21 | 2013-02-21 | Huawei Technologies Co., Ltd. | Method, apparatus and system for acquiring media access control address |
| CN105530330A (en) * | 2015-12-07 | 2016-04-27 | 中国电子科技集团公司第十研究所 | Method for improving operation efficiency of ARP protocol in space information network |
| CN106534168A (en) * | 2016-12-06 | 2017-03-22 | 中国电子科技集团公司第三十二研究所 | TCPIP protocol stack safety processing system based on FPGA |
| CN108243262A (en) * | 2016-12-26 | 2018-07-03 | 大唐移动通信设备有限公司 | Learning method, device and the network three-layer equipment of ARP table |
| CN109951459A (en) * | 2019-03-06 | 2019-06-28 | 山东信天辰信息安全技术有限公司 | A kind of ARP spoofing attack detection method based on local area network |
| CN113872949A (en) * | 2021-09-18 | 2021-12-31 | 山东云海国创云计算装备产业创新中心有限公司 | Response method of address resolution protocol and related device |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115297082A (en) * | 2022-08-03 | 2022-11-04 | 江苏新质信息科技有限公司 | ARP protocol processing method and system based on cooperation of FPGA and eBPF |
| CN115297082B (en) * | 2022-08-03 | 2023-08-25 | 江苏新质信息科技有限公司 | ARP protocol processing method and system based on FPGA and eBPF cooperation |
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