[go: up one dir, main page]
More Web Proxy on the site http://driver.im/

CN114552987A - BOOST circuit of self-adaptation slope compensation - Google Patents

BOOST circuit of self-adaptation slope compensation Download PDF

Info

Publication number
CN114552987A
CN114552987A CN202210166171.6A CN202210166171A CN114552987A CN 114552987 A CN114552987 A CN 114552987A CN 202210166171 A CN202210166171 A CN 202210166171A CN 114552987 A CN114552987 A CN 114552987A
Authority
CN
China
Prior art keywords
voltage
differential
circuit
output
slope
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202210166171.6A
Other languages
Chinese (zh)
Inventor
不公告发明人
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shanghai Canrui Technology Co ltd
Original Assignee
Shanghai Canrui Technology Co ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shanghai Canrui Technology Co ltd filed Critical Shanghai Canrui Technology Co ltd
Priority to CN202210166171.6A priority Critical patent/CN114552987A/en
Publication of CN114552987A publication Critical patent/CN114552987A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
    • H02M3/158—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
    • H02M3/1584—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load with a plurality of power processing stages connected in parallel
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/14—Arrangements for reducing ripples from dc input or output
    • H02M1/143—Arrangements for reducing ripples from dc input or output using compensating arrangements
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/14—Arrangements for reducing ripples from dc input or output
    • H02M1/15—Arrangements for reducing ripples from dc input or output using active elements
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Dc-Dc Converters (AREA)

Abstract

The invention relates to a BOOST circuit with adaptive slope compensation, which comprises a basic BOOST circuit and an adaptive slope compensation circuit, wherein the basic BOOST circuit is arranged to receive an input voltage VinAnd provides an output voltage VoutThe adaptive slope compensation circuit comprises a differential circuit and a slope generation circuit, wherein the differential circuit is arranged to generate a current magnitude and an output voltage VoutAnd an input voltage VinIs arranged to produce a differential current having a slope proportional to the output voltage VoutAnd an input voltage VinProportional to the sawtooth voltage. The self-adaptive slope compensation BOOST circuit utilizes the differential circuit and the slope generation circuit to generate a compensation slope voltage signal which is related to the input and output voltage and simultaneously changes along with the duty ratio, and has simple structureThe method is simple and easy to realize, and the compensation performance is good in a wider output voltage range.

Description

BOOST circuit of self-adaptation slope compensation
Technical Field
The invention relates to the technical field of integrated circuits, in particular to a BOOST circuit with adaptive slope compensation.
Background
With the development of the electronic industry in the form of a well-spraying device, a power management chip is widely used in a portable device as an extremely important voltage stabilizing module, which requires the chip to ensure a stable and efficient operating state under a wide input and output voltage variation range. Compared with other kinds of power management chips, the DC-DC converter has great advantages in conversion efficiency, and particularly, the BOOST circuit in the peak current control mode is widely used due to its advantages of fast transient response, large gain bandwidth, excellent EMI characteristics, and the like.
But the peak current control mode will exhibit subharmonic oscillations at duty cycles greater than 50%, Δ I as shown in FIGS. 1A and 1B0For initial perturbation of the inductor current, Δ I1For a perturbation after one cycle, its magnitude can be expressed as:
Figure BDA0003516015480000011
wherein SnAnd SfThe slope of the rise and fall of the inductor current in the BOOST circuit can be expressed as:
Figure BDA0003516015480000012
and
Figure BDA0003516015480000013
thus Δ I1The expression may become:
Figure BDA0003516015480000014
then Δ I0Disturbance Δ I after n cyclesnCan be expressed as:
Figure BDA0003516015480000015
according to the above formula, when D>The equation does not converge at 50%, and subharmonic oscillation occurs. In order to suppress this phenomenon, it is necessary to introduce a slope S by using a slope compensation circuiteOf the compensating ramp, then Δ InThe expression of (c) may become:
Figure BDA0003516015480000021
as long as S is guaranteedeValue of (1)
Figure BDA0003516015480000022
That is, the above formula can be converged, thereby realizing the duty ratio D>The subharmonic oscillation phenomenon does not occur at 50%.
The conventional slope compensation can be divided into primary slope compensation and segmented slope compensation, as shown in fig. 2, a slope signal with a fixed slope is constructed in one clock cycle, so that the subharmonic oscillation phenomenon can be effectively inhibited, but under different duty ratios, the required slope is often not a fixed value, the slope required when the maximum duty ratio is generally adopted when the slope is determined, and the overcompensation condition can occur when the duty ratio is relatively small, so that the gain bandwidth is reduced, and the transient response capability is greatly reduced. The segmented slope compensation is to construct several fixed slope signals at the same time, and the signals are respectively applied to the conditions of different duty ratios, the mode is not an optimal solution for the compensation in the full duty ratio range, and the silicon utilization rate can be greatly reduced due to the introduction of a plurality of charging and discharging capacitors.
Disclosure of Invention
The invention aims to provide a BOOST circuit with adaptive slope compensation, which dynamically modulates the slope of a compensation slope according to the change of input and output voltages, thereby avoiding overcompensation or undercompensation, effectively inhibiting subharmonic oscillation and improving transient response capability.
The invention provides a BOOST circuit with self-adaptive slope compensation, which comprises: a basic BOOST circuit arranged to receive an input voltage V, and an adaptive slope compensation circuitinAnd provides an output voltage VoutThe adaptive slope compensation circuit comprises a differential circuit and a slope generation circuit, wherein the differential circuit is arranged to generate a current magnitude and an output voltage VoutAnd an input voltage VinIs arranged to produce a differential current having a slope proportional to the output voltage VoutAnd an input voltage VinProportional to the sawtooth voltage.
Further, the basic BOOST circuit comprises a power switch tube M1, a synchronous rectifier tube M2 and an energy storage inductor LswA first feedback resistor Rfb1A second feedback resistor Rfb2Inductive current sampling circuit VsenseError amplifier EA, PWM, logic circuit, first driving buffer, second driving buffer, and load resistor RLOutput capacitance COA drain of the power switch tube M1 is connected with a drain of the synchronous rectifier tube M2, and a connection point of the power switch tube M1 and the synchronous rectifier tube M2 is arranged to receive the induced voltage VswEnergy storage inductor LswHas one end connected to a first voltage source for receiving an input voltage VinEnergy storage inductor LswThe other end of which supplies the induced voltage Vsw(ii) a The source of the power switch tube M1 is connected with the reference ground voltage GND, and the source of the synchronous rectifier tube M2 is connected with the output capacitor COOne end of (1), load resistance RLOne terminal and voltage output terminal of, output capacitor COThe other end of the load resistor R is connected with a reference ground voltage GND and a load resistor RLThe other end of the ground voltage reference unit is connected with a reference ground voltage GND; first feedback resistor Rfb1And a second feedback resistor Rfb2Connected and the connection point is arranged to provide a feedback voltage VfbFirst feedback resistance Rfb1The other end of the first and second voltage-sensing units is connected with the voltage output end to receive the output voltage V provided by the voltage output endoutSecond feedback resistor Rfb2The other end of the ground voltage reference unit is connected with a reference ground voltage GND; the positive input terminal of the error amplifier EA is connected to a second voltage source for receiving a reference voltage VrefThe negative input terminal receives a feedback voltage Vfb(ii) a The negative input end of the PWM comparator is connected with the output end of the error amplifier EA, and the output end of the PWM comparator is connected with the input end of the logic circuit; two output ends of the logic circuit are respectively connected with the input ends of a first driving buffer and a second driving bufferThe output end of the rectifier is respectively connected with the control ends of the synchronous rectifier tube M2 and the power switch tube M1; inductive current sampling circuit VsenseInput terminal and energy storage inductor LswProviding the induced voltage VswIs connected to receive an incoming inductor current sampling signal IsenseThe output signal provided by the output end of the pulse width modulation comparator PWM is received by the positive input end of the pulse width modulation comparator PWM after being superposed with the output voltage of the self-adaptive slope compensation circuit; the output voltage of the self-adaptive slope compensation circuit is the sawtooth wave voltage Vslope。
Further, the differential circuit includes first, second, third and fourth differential PMOS transistors MP1, MP2, MP3, MP4, first, second, third and fourth differential NMOS transistors MN1, MN2, MN3, MN4, first current source, second current source, third current source, fourth current source and first resistor R1(ii) a One end of the first current source receives an input voltage VinThe other end of the first differential PMOS tube MP1 is connected with the grid electrode of the second differential PMOS tube MP2 and the drain electrode of the first differential NMOS tube MN 1; a second current source I2One end of which is connected to an input voltage VinThe other end of the first differential NMOS transistor MN1 is connected with the grid electrodes of the third differential PMOS transistor MP3 and the fourth differential PMOS transistor MP4 and the drain electrode of the second differential NMOS transistor MN2, and the grid electrode of the first differential NMOS transistor MN1 is connected with the output voltage VoutProportional voltage, the source of the first differential NMOS transistor MN1 is connected to one end of a third current source, and the other end of the third current source is connected to the ground reference voltage GND; the gate of the second differential NMOS transistor MN2 is connected to the input voltage VinThe source electrode of the second differential NMOS tube MN2 is connected with one end of a fourth current source, and the other end of the fourth current source is connected with a reference ground voltage GND; a first resistor R1One end of the first resistor R is connected with one end of a third current source, the drain electrode of the second differential PMOS tube MP2 and the source electrode of the first differential NMOS tube MN11The other end of the first differential PMOS tube is connected with one end of a fourth current source, the drain electrode of a third differential PMOS tube MP3 and the source electrode of a second differential NMOS tube MN 2; the source electrodes of the first, second, third and fourth differential PMOS transistors MP1, MP2, MP3 and MP4 receive an input voltage VinThe drain of the first differential PMOS transistor MP1 is connectedThe drain and the gate of the third differential NMOS transistor MN3 are connected, and the source of the third differential NMOS transistor MN3 is connected with a reference ground voltage GND; the drain of the fourth differential PMOS transistor MP4 is connected to the drain of the fourth differential NMOS transistor MN4, and the source of the fourth differential NMOS transistor MN4 is connected to the ground reference voltage GND.
Further, the voltage connected to the gate of the first differential NMOS transistor MN1 is Vout/4。
Further, the voltage connected with the gate of the second differential NMOS transistor MN2 is Vin/4。
Further, the first current source provides a first fixed current I1Equal to a second fixed current I provided by the second current source2A third fixed current I provided by the third current source3Equal to a fourth fixed current I provided by the fourth current source4。
Further, the ramp generating circuit comprises a first ramp PMOS tube MP5, a second ramp PMOS tube MP6, a ramp NMOS tube MN5 and a first capacitor C1The sources of the first ramp PMOS transistor MP5 and the second ramp PMOS transistor MP6 receive the input voltage VinThe drain of the first ramp PMOS transistor MP5 is connected to the gate and to the gate of the second ramp PMOS transistor MP6, the drains of the fourth differential PMOS transistor MP4 and the fourth differential NMOS transistor MN4, and the drain of the second ramp PMOS transistor MP6 is connected to the first capacitor C1And a drain of the ramp NMOS transistor MN5, and is configured to output an output voltage of the adaptive ramp compensation circuit, a gate of the ramp NMOS transistor MN5 is connected to the clock signal CLK of the basic BOOST circuit, and a first capacitor C1The other end of the ramp NMOS transistor MN5 is connected to the ground reference voltage GND.
Further, a current mirror with a ratio of 1:1 is respectively formed by the third differential PMOS transistor MP3 and the fourth differential PMOS transistor MP4, the second differential PMOS transistor MP2 and the first differential PMOS transistor MP1, and the third differential NMOS transistor MN3 and the fourth differential NMOS transistor MN 4.
Further, the first slope PMOS transistor MP5 and the second slope PMOS transistor MP6 constitute a current mirror with a ratio of 1: 1.
Further, the first capacitor C1A first resistor R1And an energy storage inductor LswSatisfy the shut-downIs represented by the following formula: 2R1C1＝Lsw。
The self-adaptive slope compensation BOOST circuit utilizes the differential circuit and the slope generation circuit to generate a compensation slope voltage signal which is related to the input and output voltages and changes along with the duty ratio, has a simple structure, is easy to realize, and has good compensation performance in a wider output voltage range. Due to the special structure of the differential circuit, the differential current can be very small, the power consumption is reduced, the area of the capacitor can be correspondingly reduced, and the utilization rate of silicon is greatly improved. The self-adaptive slope compensation function can provide an optimal solution of slope compensation for the BOOST circuit under different duty ratios, overcompensation or undercompensation is avoided, subharmonic oscillation is effectively restrained, and transient response capability is improved.
Drawings
Fig. 1A and 1B are diagrams illustrating the influence of inductor current disturbance on a system when a duty ratio of a conventional peak current mode BOOST circuit is less than 50% and greater than 50%, respectively;
FIG. 2 is a diagram illustrating the effect of inductive current disturbance on a system after a primary slope compensation is introduced into a BOOST circuit in a conventional peak current mode;
FIG. 3 is a block diagram of a BOOST circuit architecture for adaptive slope compensation according to an embodiment of the present invention;
FIG. 4 is a block diagram of an adaptive slope compensation circuit according to an embodiment of the present invention;
FIG. 5A is a graph of a ramp voltage waveform with a constant input voltage and a constant output voltage according to an embodiment of the present invention;
fig. 5B is a diagram of a ramp voltage waveform when the output voltage is fixed and the input voltage is changed according to an embodiment of the invention.
Detailed Description
The preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
As shown in fig. 3, an embodiment of the present invention provides an adaptive slope compensation BOOST circuit, which includes a base BOOST circuit and an adaptive slope compensation circuit 102 electrically connected to each other. The basic BOOST circuit comprises a power switch tube M1, a synchronous rectifier tube M2, and an energy storage inductor LswA first feedback resistor Rfb1A second feedback resistor Rfb2Inductive current sampling circuit VsenseError amplifier EA, pulse width modulation comparator PWM, logic circuit 101, first drive buffer 103, second drive buffer 104, and load resistor RLOutput capacitance COA first voltage source for providing an input voltage V, and a second voltage sourceinA second voltage source for providing a reference voltage Vref。
The drain of the power switch tube M1 is connected with the drain of the synchronous rectifier tube M2, and the connection point of the power switch tube M1 and the synchronous rectifier tube M2 is arranged to receive the induced voltage VswEnergy storage inductor LswHas one end connected to a first voltage source for receiving an input voltage VinEnergy storage inductor LswThe other end of which supplies the induced voltage Vsw(ii) a The source of the power switch tube M1 is connected with the reference ground voltage GND, and the source of the synchronous rectifier tube M2 is simultaneously connected with the output capacitor COOne end of (1), a load resistance RLTo a voltage output terminal to supply an output voltage V to the voltage output terminaloutOutput capacitance COThe other end of the load resistor R is connected with a reference ground voltage GND and a load resistor RLAnd the other end thereof is connected to a reference ground voltage GND. In this embodiment, the power switch M1 is an NMOS transistor, and the synchronous rectifier M2 is a PMOS transistor.
First feedback resistor Rfb1And a second feedback resistor Rfb2Connected to a first feedback resistor Rfb1And a second feedback resistor Rfb2Is arranged to provide a feedback voltage VfbFirst feedback resistance Rfb1The other end of the first and second voltage-sensing units is connected with the voltage output end to receive the output voltage V provided by the voltage output endoutSecond feedback resistor Rfb2And the other end thereof is connected to a reference ground voltage GND.
The positive input terminal of the error amplifier EA is connected to a second voltage source for receiving a reference voltage VrefThe negative input terminal receives a feedback voltage Vfb。
The negative input end of the PWM comparator is connected to the output end of the error amplifier EA, and the output end is connected to the input end of the logic circuit 101.
Two output ends of the logic circuit 101 are respectively connected to the input ends of the first driving buffer 103 and the second driving buffer 104, and the output ends of the first driving buffer 103 and the second driving buffer 104 are respectively connected to the control ends of the synchronous rectifier M2 and the power switch M1.
Inductive current sampling circuit VsenseInput terminal and energy storage inductor LswProviding the induced voltage VswIs connected to receive an incoming inductor current sampling signal IsenseAnd an output signal provided by an output end of the adaptive slope compensation circuit 102 is received by a positive input end of the pulse width modulation comparator PWM after being superposed with the output voltage of the adaptive slope compensation circuit.
As shown in fig. 4, the adaptive slope compensation circuit 102 includes a differential circuit for generating a current magnitude and an output voltage V and a slope generation circuitoutAnd an input voltage VinA ramp generating circuit for generating a slope and an output voltage VoutAnd an input voltage VinProportional to the sawtooth voltage.
The differential circuit comprises a first differential PMOS tube MP1, a second differential PMOS tube MP2, a fourth differential PMOS tube MP3, a first differential NMOS tube MP4, a second differential NMOS tube MN1, a third differential NMOS tube MN2, a third differential NMOS tube MN3, a fourth differential PMOS tube MN4, a first current source, a second current source, a third current source, a fourth current source and a first resistor R1The ramp generating circuit comprises a first ramp PMOS tube MP5, a second ramp PMOS tube MP6, a ramp NMOS tube MN5 and a first capacitor C1。
The first current source and the second current source are respectively used for providing a first fixed current I1And a second fixed current I2And I is1＝I2A third current source and a fourth current source for providing a third fixed current I3And a fourth fixed current I4And I is3＝I4. A first capacitor C1For generating sawtooth wave voltage signal Vslope。
One end of the first current source receives an input voltage VinThe other end is connected with a first differential PMOS tube MThe P1, the grid of the second differential PMOS pipe MP2 and the drain of the first differential NMOS pipe MN 1; one end of the second current source is connected with the input voltage VinAnd the other end is connected with the gates of the MP3 and the MP4 and the drain of the MN 2.
Gate connection and output voltage V of MN1outProportional voltage, V in this exampleoutThe source of the MN1 is connected with one end of a third current source, and the other end of the third current source is connected with the ground reference voltage GND; gate connection of MN2 to input voltage VinProportional voltage, V in this exampleinAnd a source electrode of the MN2 is connected with one end of a fourth current source, and the other end of the fourth current source is connected with the ground reference voltage GND.
A first resistor R1One end of the first resistor is connected with one end of the third current source, the drain electrode of the MP2 and the source electrode of the MN1, and the first resistor R1The other end of the second current source is connected with one end of the fourth current source, the drain of the MP3 and the source of the MN 2.
The sources of MP1, MP2, MP3, and MP4 receive an input voltage VinThe drain of the MP1 is connected with the drain and the gate of the MN3, and the source of the MN3 is connected with the ground reference voltage GND; the drain of the MP4 is connected with the drain of the MN4, and the source of the MN4 is connected with the ground reference voltage GND.
The sources of the PMOS transistors MP5 and MP6 receive the input voltage VinThe drain of MP5 is connected to the gate and to the gate of MP6, MP4 and the drain of MN 4.
The drain of MP6 is connected to the first capacitor C1And the drain of MN5, and is arranged to output the output voltage of the adaptive ramp compensation circuit 102 (i.e., the sawtooth voltage V)slope) The gate of MN5 is connected with the clock signal CLK, C of BOOST circuit1And the other end of the same and the source of MN5 are connected to a ground reference voltage GND.
The control-output transfer function for a BOOST converter can be expressed as (pulse width modulation DC-DC power conversion-circuit, dynamics and control design [ M ]. kindred, mechanical industry publishers, 2018: 472-:
Figure BDA0003516015480000071
where s is the complex frequency domain independent variable, Kvc is the low frequency gain, ωesrTo output the ESR zero point of the capacitor, omegarhpIs the right half plane zero point, omegap1To output a dominant pole, ωnOne half of the switching frequency.
In the control-output transfer function of the current-controlled BOOST circuit, the quality factor Q of the second-order term can be expressed as (A new, connected-time model for current-mode control [ J ]. Ridley R B.IEEE Transactions on Power Electronics,1991,6(2): 271-280):
Figure BDA0003516015480000081
wherein S isnThe slope of the rise of the inductor current in the peak current mode, SeTo compensate for the slope of the ramp, D is the duty cycle, D' is 1-D. To make the system stable and good in transient performance, the quality factor needs to be ensured
Figure BDA0003516015480000082
For peak current mode base BOOST circuit, the inductor current rise slope SnAnd a falling slope SfComprises the following steps:
Figure BDA0003516015480000083
will SnWhen the expression of Q is substituted, it can be found that
Figure BDA0003516015480000084
When the temperature of the water is higher than the set temperature,
Figure BDA0003516015480000085
that is, to make the system stable and the transient performance good, it is necessary to ensure
Figure BDA0003516015480000086
And the circuit is relatively easy to implement at this time.
It can be known from this that the optimal solution of slope compensation is not fixed under different input and output voltages, i.e. different duty ratios, and can be considered as VoutAnd VinThe difference has a linear relationship with respect to the application of a fixed inductance LswThe BOOST circuit of (1) may consider the relation coefficient as a fixed value.
In a differential circuit, because of I1＝I2Therefore, the currents flowing through MN1 and MN2 are equal, and the gates of MN1 and MN2 are respectively connected with Vout/4 and Vin/4, therefore:
Figure BDA0003516015480000087
wherein VRIs a first resistor R1The voltage difference across the terminals.
By analysing the first resistance R1The current network at both ends can obtain:
IX＝I3+IR-I1
IY＝I4+IR-I2
wherein, IX、IY、IRAre both flowing into or out of the first resistor R1Current of the current network at both ends, I1-I4The differential pair MN1 and MN2 control terminal voltage change can affect I for the preset direct current (namely the first, second, third and fourth fixed currents)X、IYCurrent value of (1), thereforeXAnd IYThe difference in (b) can directly reflect the difference between the control ends of the differential pair transistors MN1 and MN 2.
In this embodiment, MP3 and MP4, MP2 and MP1 respectively constitute a mixture in a ratio of 1: a current mirror, and MN3 and MN4 constitute a 1:1 current mirror, when:
Iout1＝AIX
Iout2＝AIY
according to kirchhoff's current law, there are:
Iout＝Iout1-Iout2
where Iout is the output current of the differential circuit.
Due to I1＝I2，I3＝I4It is possible to obtain:
Figure BDA0003516015480000091
in order to generate different charging currents to match with different capacitance values, the difference current is multiplied by a current mirror coefficient A and then multiplied by a current mirror coefficient B. For this reason, in the ramp generation circuit, MP5 and MP6 constitute a ramp in a ratio of 1: b current mirror, then ramp generating current IslopeComprises the following steps:
Figure BDA0003516015480000092
to simplify the formula, in the present embodiment, the current mirror ratios a and B are both set to 1. Of course, a and B may take other suitable values as desired.
By means of IslopeFor the first capacitor C1The clock signal CLK of the BOOST circuit controls the first capacitor C through MN51Thereby forming a sawtooth wave, and the sawtooth wave voltage V output by the adaptive ramp compensation circuit 102slopeComprises the following steps:
Figure BDA0003516015480000093
through the analysis, the slope optimal solution of the slope compensation of the basic BOOST circuit can be found as follows:
Figure BDA0003516015480000094
therefore, only R needs to be set1And C1Is taken to be 2R1C1L, at different duty cyclesAn optimal compensation ramp is provided for the BOOST circuit, where L ═ L in this embodimentsw。
As shown in fig. 5A, when the input voltage is fixed and the output voltage is gradually increased, that is, the duty ratio is increased, the slope of the ramp voltage is gradually increased; as shown in fig. 5B, when the output voltage is fixed and the input voltage is gradually increased, i.e. the duty ratio is decreased, the slope of the ramp voltage is gradually decreased; thereby realizing the adaptive slope compensation function.
The BOOST circuit with the self-adaptive slope compensation, provided by the embodiment of the invention, utilizes the differential circuit and the slope generation circuit to generate a compensation slope voltage signal which is related to the input and output voltages and changes along with the duty ratio, and has the advantages of simple structure, easiness in realization and good compensation performance in a wider output voltage range. Due to the special structure of the differential circuit, the differential current can be very small, the power consumption is reduced, the area of the capacitor can be correspondingly reduced, and the utilization rate of silicon is greatly improved. The self-adaptive slope compensation function can provide an optimal solution of slope compensation for the BOOST circuit under different duty ratios, overcompensation or undercompensation is avoided, subharmonic oscillation is effectively restrained, and transient response capability is improved.
The above embodiments are merely preferred embodiments of the present invention, which are not intended to limit the scope of the present invention, and various changes may be made in the above embodiments of the present invention. All simple and equivalent changes and modifications made according to the claims and the content of the specification of the present application fall within the scope of the claims of the present patent application. The invention has not been described in detail in order to avoid obscuring the invention.

Claims (10)

1. An adaptive slope compensation BOOST circuit, comprising a base BOOST circuit configured to receive an input voltage V and an adaptive slope compensation circuitinAnd provides an output voltage VoutThe adaptive slope compensation circuit comprises a differential circuit and a slope generation circuit, wherein the differential circuit is arranged to generate a current magnitude and an output voltage VoutAnd an input voltage VinIs proportional to the difference ofA current, the ramp generating circuit being arranged to generate a slope and an output voltage VoutAnd an input voltage VinProportional to the sawtooth voltage.
2. The adaptive slope compensated BOOST circuit of claim 1, wherein the basic BOOST circuit comprises a power switch M1, a synchronous rectifier M2, an energy storage inductor LswA first feedback resistor Rfb1A second feedback resistor Rfb2Inductive current sampling circuit VsenseError amplifier EA, PWM, logic circuit, first driving buffer, second driving buffer, and load resistor RLOutput capacitance COA drain of the power switch tube M1 is connected with a drain of the synchronous rectifier tube M2, and a connection point of the power switch tube M1 and the synchronous rectifier tube M2 is arranged to receive the induced voltage VswEnergy storage inductor LswHas one end connected to a first voltage source for receiving an input voltage VinEnergy storage inductor LswThe other end of which supplies the induced voltage Vsw(ii) a The source of the power switch tube M1 is connected with the reference ground voltage GND, and the source of the synchronous rectifier tube M2 is connected with the output capacitor COOne end of (1), load resistance RLOne terminal of (2) and a voltage output terminal, an output capacitor COThe other end of the load resistor R is connected with a reference ground voltage GND and a load resistor RLThe other end of the ground voltage reference unit is connected with a reference ground voltage GND; first feedback resistor Rfb1And a second feedback resistor Rfb2Connected and the connection point is arranged to provide a feedback voltage VfbFirst feedback resistance Rfb1The other end of the first and second voltage-sensing units is connected with the voltage output end to receive the output voltage V provided by the voltage output endoutSecond feedback resistor Rfb2The other end of the ground voltage reference unit is connected with a reference ground voltage GND; the positive input terminal of the error amplifier EA is connected to a second voltage source for receiving a reference voltage VrefThe negative input terminal receives a feedback voltage Vfb(ii) a The negative input end of the PWM comparator is connected with the output end of the error amplifier EA, and the output end of the PWM comparator is connected with the input end of the logic circuit; two output ends of the logic circuit are respectively connected with the first driving bufferThe output ends of the first driving buffer and the second driving buffer are respectively connected with the control ends of the synchronous rectifier tube M2 and the power switch tube M1; inductive current sampling circuit VsenseInput terminal and energy storage inductor LswProviding the induced voltage VswIs connected to receive an incoming inductor current sampling signal IsenseThe output signal provided by the output end of the pulse width modulation comparator PWM is received by the positive input end of the pulse width modulation comparator PWM after being superposed with the output voltage of the self-adaptive slope compensation circuit; the output voltage of the self-adaptive slope compensation circuit is the sawtooth wave voltage Vslope。
3. The adaptive slope compensated BOOST circuit of claim 2, wherein the differential circuit comprises first, second, third and fourth differential PMOS transistors MP1, MP2, MP3, MP4, first, second, third and fourth differential NMOS transistors MN1, MN2, MN3, MN4, a first current source, a second current source, a third current source, a fourth current source and a first resistor R1(ii) a One end of the first current source receives an input voltage VinThe other end of the first differential PMOS tube MP1 is connected with the grid electrode of the second differential PMOS tube MP2 and the drain electrode of the first differential NMOS tube MN 1; a second current source I2One end of which is connected to an input voltage VinThe other end of the first differential NMOS transistor MN1 is connected with the grid electrodes of the third differential PMOS transistor MP3 and the fourth differential PMOS transistor MP4 and the drain electrode of the second differential NMOS transistor MN2, and the grid electrode of the first differential NMOS transistor MN1 is connected with the output voltage VoutProportional voltage, the source of the first differential NMOS transistor MN1 is connected to one end of a third current source, and the other end of the third current source is connected to the ground reference voltage GND; the gate of the second differential NMOS transistor MN2 is connected to the input voltage VinThe source electrode of the second differential NMOS tube MN2 is connected with one end of a fourth current source, and the other end of the fourth current source is connected with a reference ground voltage GND; a first resistor R1One end of the first resistor R is connected with one end of a third current source, the drain electrode of the second differential PMOS tube MP2 and the source electrode of the first differential NMOS tube MN11The other end of the first differential PMOS transistor MP is connected with one end of a fourth current source, the drain electrode of a third differential PMOS transistor MP3 and the second end of the second differential PMOS transistor MPThe source electrode of the two differential NMOS tubes MN 2; the source electrodes of the first, second, third and fourth differential PMOS transistors MP1, MP2, MP3 and MP4 receive an input voltage VinThe drain electrode of the first differential PMOS tube MP1 is connected with the drain electrode and the gate electrode of the third differential NMOS tube MN3, and the source electrode of the third differential NMOS tube MN3 is connected with the reference ground voltage GND; the drain of the fourth differential PMOS transistor MP4 is connected to the drain of the fourth differential NMOS transistor MN4, and the source of the fourth differential NMOS transistor MN4 is connected to the ground reference voltage GND.
4. The adaptive slope compensated BOOST circuit of claim 3, wherein the voltage connected to the gate of the first differential NMOS transistor MN1 is Vout/4。
5. The BOOST circuit with adaptive slope compensation of claim 3, wherein the voltage connected to the gate of the second differential NMOS transistor MN2 is Vin/4。
6. The adaptive slope compensated BOOST circuit of claim 3, wherein the first current source provides a first fixed current I1Equal to a second fixed current I provided by the second current source2A third fixed current I provided by the third current source3Equal to a fourth fixed current I provided by the fourth current source4。
7. The adaptive slope compensation BOOST circuit of claim 3, wherein the slope generation circuit comprises a first slope PMOS transistor MP5, a second slope PMOS transistor MP6, a slope NMOS transistor MN5 and a first capacitor C1The sources of the first ramp PMOS transistor MP5 and the second ramp PMOS transistor MP6 receive the input voltage VinThe drain of the first ramp PMOS transistor MP5 is connected to the gate and to the gate of the second ramp PMOS transistor MP6, the drains of the fourth differential PMOS transistor MP4 and the fourth differential NMOS transistor MN4, and the drain of the second ramp PMOS transistor MP6 is connected to the first capacitor C1And a drain of the slope NMOS transistor MN5, and is set to output the output of the output adaptive slope compensation circuitThe gate of the voltage ramp NMOS transistor MN5 is connected with the clock signal CLK of the basic BOOST circuit and the first capacitor C1The other end of the ramp NMOS transistor MN5 is connected to the ground reference voltage GND.
8. The adaptive slope compensation BOOST circuit according to claim 7, wherein the third and fourth differential PMOS transistors MP3 and MP4, the second and first differential PMOS transistors MP2 and MP1, and the third and fourth differential NMOS transistors MN3 and MN4 respectively constitute a current mirror with a ratio of 1: 1.
9. The adaptive slope compensated BOOST circuit of claim 8, wherein the first ramp PMOS transistor MP5 and the second ramp PMOS transistor MP6 form a current mirror with a ratio of 1: 1.
10. The adaptive slope compensated BOOST circuit of claim 7, wherein said first capacitance C1A first resistor R1And an energy storage inductor LswSatisfy the relation: 2R1C1＝Lsw。
CN202210166171.6A 2022-02-23 2022-02-23 BOOST circuit of self-adaptation slope compensation Pending CN114552987A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202210166171.6A CN114552987A (en) 2022-02-23 2022-02-23 BOOST circuit of self-adaptation slope compensation

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202210166171.6A CN114552987A (en) 2022-02-23 2022-02-23 BOOST circuit of self-adaptation slope compensation

Publications (1)

Publication Number Publication Date
CN114552987A true CN114552987A (en) 2022-05-27

Family

ID=81677512

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202210166171.6A Pending CN114552987A (en) 2022-02-23 2022-02-23 BOOST circuit of self-adaptation slope compensation

Country Status (1)

Country Link
CN (1) CN114552987A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115378258A (en) * 2022-10-26 2022-11-22 苏州浪潮智能科技有限公司 Server and compensation circuit of direct current voltage reduction circuit thereof
CN116667650A (en) * 2023-04-18 2023-08-29 华南理工大学 Single-inductor multi-level direct current converter based on self-adaptive slope calibration mode
CN118659654A (en) * 2024-08-21 2024-09-17 成都市易冲半导体有限公司 Switching power supply and self-adaptive compensation method and device thereof

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115378258A (en) * 2022-10-26 2022-11-22 苏州浪潮智能科技有限公司 Server and compensation circuit of direct current voltage reduction circuit thereof
CN116667650A (en) * 2023-04-18 2023-08-29 华南理工大学 Single-inductor multi-level direct current converter based on self-adaptive slope calibration mode
CN116667650B (en) * 2023-04-18 2024-02-20 华南理工大学 Single-inductor multi-level direct current converter based on self-adaptive slope calibration mode
CN118659654A (en) * 2024-08-21 2024-09-17 成都市易冲半导体有限公司 Switching power supply and self-adaptive compensation method and device thereof

Similar Documents

Publication Publication Date Title
US10355591B2 (en) Multilevel boost DC to DC converter circuit
US11088631B2 (en) Three-level DC-DC converter and voltage balancing circuit thereof
CN114552987A (en) BOOST circuit of self-adaptation slope compensation
US11444537B2 (en) Power converters and compensation circuits thereof
US7633778B2 (en) Switched-capacitor regulators
CN105337500B (en) Power inverter and the method responded for adjusting the linear transient of power inverter
CN106329924B (en) A kind of system improving load transient response performance
US8174250B2 (en) Fixed frequency ripple regulator
CN105207480B (en) The synchronous buck type DC DC converters of output ripple and low during a kind of underloading
US8860395B2 (en) Circuit and method for generating a ramp compensation voltage for a switching regulator
US10447154B2 (en) PWM control scheme for providing minimum on time
CN101295927B (en) Modified oscillator and decompression power converter
JP2013046496A (en) Control circuit, power supply device, and method of controlling power supply
CN106787652A (en) A kind of dynamic suitable for buck converter output DC maladjustment eliminates circuit
CN103178711A (en) Buck-boost direct-current converting circuit
CN116633139B (en) Power converter, ramp signal generator thereof and ramp signal generating method
CN105896972A (en) Self-adaptive secondary slope compensation circuit for BUCK converter
CN108599566A (en) A kind of buck DC-DC converter self-adaptable slop compensation circuit
CN118199404A (en) Dual-mode BOOST circuit
Liu et al. Dynamic performance analysis of 3-level integrated buck converters
CN102882374A (en) Mixed-signal pseudo-three-type compensation circuit with optimized area
WO2023280328A1 (en) Switching converter and control circuit thereof
CN116317558A (en) Self-adaptive slope compensation peak current control circuit, method and DC-DC converter
CN116915047A (en) DC-DC converter circuit and corresponding method of operation
Bouhalli et al. Multiphase coupled converter models dedicated to transient response and output voltage regulation studies

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination