CN114552976B - Full GaN gate drive circuit with high conversion rate - Google Patents

Abstract

The invention belongs to the technical field of power supply management and relates to integrated circuit design technology, in particular to an all-GaN gate drive circuit with high conversion rate. The all-GaN gate drive circuit proposed by the present invention adds a cross-coupled charge pump to the traditional all-GaN bootstrap inverter to realize the rail-to-rail charging voltage of the bootstrap capacitor, and realize A higher matching between the output rising speed and falling speed is achieved. Adding a power boost module to the traditional two-stage structure bootstrap inverter that drives GaN power transistors increases the output voltage of the bias stage to three times the power supply voltage, improves the gate rise speed of GaN power transistors, and reduces the gate rise The mismatch between slope and falling slope realizes high-speed and high-slew-rate driving. A good match between the turn-on delay and turn-off delay of the GaN power transistor is achieved by cascading four-stage bootstrap inverters.

Description

An all-GaN gate drive circuit with high slew rate

technical field

The invention belongs to the technical field of power management, and in particular relates to an all-GaN gate drive circuit with high conversion rate.

Background technique

GaN power devices have smaller on-resistance and parasitic capacitance than Si MOSFET power devices. Compared with Si MOSFET power devices, the application of GaN power devices in power conversion systems can achieve higher operating frequency, higher power density and higher efficiency. Therefore, GaN power devices are considered ideal for improving the performance of power conversion systems. When applied in the system, the enhancement mode GaN device is simpler to drive than the depletion mode GaN device, without the need to generate additional negative voltage, and can achieve less power consumption while reducing the driving complexity. Therefore, enhancement mode GaN devices are usually the first choice in power conversion system applications.

At present, GaN power devices and their driving circuits mostly adopt a discrete structure or a SIP structure, that is, GaN gate driving circuits are integrated on a Si basis, and are connected to GaN power devices on PCB boards or through gold wires before being packaged as a whole. The parasitic inductance of PCB traces or gold wires exists in the gate drive loop. When GaN devices are switched quickly, the large source parasitic series inductance in the gate drive loop will attenuate the switching speed of GaN power devices, thereby limiting the gate drive. Maximum operating frequency; the parasitic series inductance of the gate may easily cause the gate overshoot of the GaN power device during the process of turning on the GaN power device, causing overvoltage on the gate of the device, and it is easy to cause the device to be turned on by mistake after the GaN power device is turned off. In the gate drive circuit of the traditional discrete structure or SIP structure, gate series resistance or programmable drive current is usually used to suppress gate overshoot, but this will increase the switching loss of GaN power devices and limit the maximum operating frequency of the gate drive. Therefore, the large parasitic inductance in the drive loop of the GaN gate drive circuit with discrete structure or SIP structure will limit the operating frequency of the drive circuit and cause reliability problems of GaN power devices.

GaN power devices and GaN gate drivers are monolithically integrated using silicon-based GaN technology, the parasitic inductance in the gate drive loop can be reduced to close to zero, and the trade-off between the gate switching speed and gate reliability of GaN power transistors can be perfectly solved. Realize high frequency and high reliability switching operation. At present, because the mobility of p-type GaN transistors is much smaller than that of n-type GaN transistors, active devices in silicon-based GaN integrated circuits still only use n-type GaN transistors. Figure 1 shows a traditional two-stage structure bootstrap inverter in an all-GaN gate drive integrated circuit, in which the transistors are all n-type enhancement GaN transistors. By cascading the bias stage and the driver stage, the output rise rate is improved. The static power consumption when the output is pulled down is reduced by the resistor R in the bias stage. However, the voltage at both ends of the bootstrap capacitors C _T0 and C _T1 cannot be charged to the power supply voltage VCC, and there is a threshold voltage loss, which attenuates the pull-up capability of _ET2 and _ET6 . When C _T1 charges the gate-source capacitance of E _T6 through E _T9 , E _T9 works in the saturation region, and the on-resistance is relatively large. When the ratio of width and length of E _T6 is large, the output rising rate decreases, and the output rising rate and falling rate will change. A serious mismatch has occurred.

Contents of the invention

The purpose of the present invention is to design an all-GaN gate drive circuit with a high slew rate for the above-mentioned problems existing in the traditional all-GaN gate drive, which can give full play to the high-frequency characteristics of the GaN power tube. Its circuit structure includes a four-stage bootstrap inverter, a cross-coupled charge pump, a power boost circuit, a bias stage and a driver stage.

The technical solution of the present invention is as follows: FIG. 2 is a structural diagram of the full GaN gate drive system of the present invention. Four-level bootstrap inverters are cascaded in the drive chain to achieve highly matched turn-on and turn-off delays. Between the first-stage and second-stage bootstrap inverters, and between the third-stage and fourth-stage bootstrap inverters, cross-coupled charge pumps are used to achieve rail-to-rail switching of the bootstrap capacitors in the bootstrap inverters. charging voltage, thereby increasing the output rise rate of the bootstrap inverter. In the third-stage bootstrap inverter, the bias stage and the driver stage are cascaded. The bias stage provides the driver stage with a bias voltage twice the power supply voltage to increase the output rise rate of the bootstrap inverter. In the fourth-stage bootstrap inverter, on the basis of cascading the bias stage and the driver stage, a power boost circuit is used to increase the power supply voltage of the bias stage to twice the gate drive power supply voltage, thereby providing three times the power supply voltage for the driver stage. The bias voltage of the power supply voltage increases the output rise rate of the fourth-stage bootstrap inverter

Specifically, the first-stage bootstrap inverter includes a first GaN transistor, a second GaN transistor, a third GaN transistor, a fourth GaN transistor, a fifth GaN transistor, a first resistor, a second resistor, and a third resistor , a fourth resistor and a first capacitor, and the second-stage bootstrap inverter includes a sixth GaN transistor, a seventh GaN transistor, an eighth GaN transistor, a ninth GaN transistor, a tenth GaN transistor, a fourth resistor and a sixth GaN transistor. Two capacitors; wherein, the gates of the first GaN tube and the second GaN tube are connected to the PWM signal, the drain of the first GaN tube is connected to the source of the fourth GaN tube through the first resistor, and the source of the first GaN tube is grounded , the drain of the second GaN tube is connected to the source of the third GaN tube, and the source of the second GaN tube is grounded; the drain of the third GaN tube is connected to the power supply, and its gate is connected to the fourth GaN tube through the first resistor source; the drain of the fourth GaN tube is connected to the power supply, and its gate is connected to the source of the ninth GaN tube; the connection point between the source of the fourth GaN tube and the first resistor is connected to one end of the first capacitor, and the connection point of the first capacitor is The other end is connected to the source of the third GaN tube and one end of the second resistor, and the other end of the second resistor is connected to the power supply; the drain of the fifth GaN tube is connected to the PWM signal after passing through the third resistor, and its gate is connected to the second resistor One end, its source is grounded; the drain of the sixth GaN tube is connected to the source of the tenth GaN tube through the fourth resistor, the gate of the sixth GaN tube is connected to one end of the second resistor, and its source is grounded; the seventh GaN tube The drain of the tube is connected to the source of the eighth GaN tube, the gate of the seventh GaN tube is connected to one end of the second resistor, and the source is grounded; the drain of the eighth GaN tube is connected to the power supply, and the gate of the eighth GaN tube is connected to the fourth resistor. Connect the source of the tenth GaN tube; the drain of the ninth GaN tube is connected to the power supply, the gate is connected to the source of the fourth GaN tube, the source of the ninth GaN tube is connected to the source of the tenth GaN tube and the second capacitor One end of the second capacitor, the other end of the second capacitor is connected to the source of the eighth GaN tube; the drain of the tenth GaN tube is connected to the power supply, and its gate and drain are interconnected; the source of the eighth GaN tube is the second stage bootstrap inverter The output terminal of the phase device; wherein the fourth GaN transistor, the eighth GaN transistor, the first capacitor and the second capacitor constitute a cross-coupled charge pump between the first-stage bootstrap inverter and the second-stage bootstrap inverter;

The third-level bootstrap inverter includes an eleventh GaN transistor, a twelfth GaN transistor, a thirteenth GaN transistor, a fourteenth GaN transistor, a fifteenth GaN transistor, a sixteenth GaN transistor, a seventeenth GaN transistor GaN tube, eighteenth GaN tube, nineteenth GaN tube, fifth resistor, sixth resistor, seventh resistor, third capacitor, and fourth capacitor, eleventh GaN tube, twelfth GaN tube, thirteenth GaN tube The GaN tube, the fourteenth GaN tube, the third capacitor and the fifth resistor form a bias stage, the fifteenth GaN tube, the sixteenth GaN tube, the seventeenth GaN tube, the eighteenth GaN tube, and the nineteenth GaN tube , the sixth resistor, the seventh resistor and the fourth capacitor constitute the driving stage; the fourth-stage bootstrap inverter includes a twenty-first GaN tube, a twenty-first GaN tube, a twenty-second GaN tube, a twenty-second GaN tube, and a twenty-second GaN tube. Three GaN tubes, twenty-fourth GaN tubes, twenty-fifth GaN tubes, twenty-sixth GaN tubes, twenty-seventh GaN tubes, twenty-eighth GaN tubes, twenty-ninth GaN tubes, and thirty GaN tubes tube, thirty-first GaN tube, thirty-second GaN tube, thirty-third GaN tube, thirty-fourth GaN tube, thirty-fifth GaN tube, thirty-sixth GaN tube, thirty-seventh GaN tube , the thirty-eighth GaN tube, the thirty-ninth GaN tube, the eighth resistor, the ninth resistor, the tenth resistor, the eleventh resistor, the fifth capacitor, the sixth capacitor, the seventh capacitor and the eighth capacitor, the second Ten GaN tubes, twenty-first GaN tubes, twenty-second GaN tubes, twenty-third GaN tubes, twenty-fourth GaN tubes, twenty-fifth GaN tubes, twenty-sixth GaN tubes, twenty-seventh GaN tubes The GaN tube, the twenty-eighth GaN tube, the twenty-ninth GaN tube, the fifth capacitor, the sixth capacitor, and the eighth resistor form a power booster, the thirty-first GaN tube, the thirty-first GaN tube, and the thirty-second GaN tube tube, the thirty-third GaN tube, the thirty-fourth GaN tube, the ninth resistor, and the seventh capacitor form a bias stage, the thirty-fifth GaN tube, the thirty-sixth GaN tube, the thirty-seventh GaN tube, the The thirty-eighth GaN tube, the thirty-ninth GaN tube, the eighth capacitor, and the eleventh resistor constitute the driving stage; wherein,

The drain of the eleventh GaN tube is connected to the source of the fourteenth GaN tube through the fifth resistor, the gate of the eleventh GaN tube is connected to the source of the eighth GaN tube, and the source of the eleventh GaN tube is grounded; The drain of the twelfth GaN tube is connected to the source of the thirteenth GaN tube, the gate of the twelfth GaN tube is connected to the source of the eighth GaN tube, and the source of the twelfth GaN tube is grounded; the thirteenth GaN tube The drain of the GaN tube is connected to the power supply, and the grid is connected to the source of the fourteenth GaN tube through the fifth resistor; the drain of the fourteenth GaN tube is connected to the power supply, and the connection point between the source and the fifth resistor is connected to the third capacitor One end, the other end of the third capacitor is connected to the source of the thirteenth GaN tube; the drain of the fifteenth GaN tube is connected to the source of the nineteenth GaN tube, and the gate of the fifteenth GaN tube is connected to the thirteenth GaN tube The source of the fifteenth GaN tube is grounded; the drain of the sixteenth GaN tube is connected to the source of the seventeenth GaN tube, the gate of the sixteenth GaN tube is connected to the source of the thirteenth GaN tube, The source of the sixteenth GaN tube is grounded; the drain of the seventeenth GaN tube is connected to the power supply, and the gate is connected to the source of the nineteenth GaN tube; the drain of the eighteenth GaN tube is connected to the power supply, and the gate is connected to the first GaN tube. The source of the twenty-third GaN tube, the source of the eighteenth GaN tube is connected to the drain of the nineteenth GaN tube and one end of the fourth capacitor, and the other end of the fourth capacitor is connected to the source of the seventeenth GaN tube; A sixth resistor is connected between the drain and source of the nineteenth GaN tube; the source of the seventeenth GaN tube is connected to one end of the seventh resistor, and the other end of the seventh resistor is connected to a power supply;

The drain of the twentieth GaN tube is connected to the source of the twenty-fourth GaN tube through the eighth resistor, the gate of the twenty-first GaN tube is connected to one end of the seventh resistor, and the source is grounded; the twenty-first GaN tube The drain of the twenty-second GaN tube is connected to the source of the twenty-second GaN tube, the gate of the twenty-first GaN tube is connected to one end of the seventh resistor, and the source is grounded; the drain of the twenty-second GaN tube is connected to the power supply, and the gate Connect the source of the twenty-fourth GaN tube through the eighth resistor; the drain of the twenty-third GaN tube is connected to the power supply, the grid is connected to the source of the eighteenth GaN tube, and the source of the twenty-third GaN tube is connected to The source of the twenty-fourth GaN tube and one end of the fifth capacitor, the other end of the fifth capacitor is connected to the source of the twenty-second GaN tube; the drain of the twenty-fourth GaN tube is connected to the power supply, and its grid and drain The drain, gate and source of the twenty-fifth GaN tube are all connected to the power supply; the drain and source of the twenty-sixth GaN tube are connected to the power supply, and the gate is connected to the source of the eighteenth GaN tube ; The grid and source of the twenty-seventh GaN tube are connected to the power supply, and the drain is connected to the drain of the twenty-eighth GaN tube; the source of the twenty-eighth GaN tube is connected to the power supply, and its grid is connected to the eighteenth GaN tube. The source of the tube; one end of the sixth capacitor is connected to the power supply, and the other end is connected to the source of the twenty-second GaN tube; the drain of the twenty-ninth GaN tube is connected to the drain of the twenty-eighth GaN tube through the ninth resistor , one end of the seventh capacitor, the grid of the thirty-second GaN tube, the grid of the thirty-third GaN tube, the grid of the twenty-ninth GaN tube is connected to one end of the seventh resistor, and its source is grounded; the third The drain of the tenth GaN tube is connected to the source of the thirty-third GaN tube, the gate of the thirty-third GaN tube is connected to one end of the seventh resistor, and the source is grounded; the drain of the thirty-first GaN tube is connected to the thirty-first GaN tube. The source of the second GaN tube, the gate of the thirty-first GaN tube is connected to one end of the seventh resistor, and the source is grounded; the drain of the thirty-second GaN tube is connected to the power supply, and the drain and the source are connected to the first end of the resistor. Ten resistors; the other end of the seventh capacitor is connected to the source of the thirty-third GaN tube, the drain of the thirty-third GaN tube is connected to the power supply; the drain of the thirty-fourth GaN tube is connected to the source of the thirty-ninth GaN tube pole, the gate of the thirty-fourth GaN tube is connected to one end of the seventh resistor, and its source is grounded; the drain of the thirty-fifth GaN tube is connected to the source of the thirty-sixth GaN tube, and the source of the thirty-fifth GaN tube The gate is connected to one end of the seventh resistor after passing through the eleventh resistor, and its source is grounded; the drain of the thirty-sixth GaN tube is connected to the power supply, and its gate is connected to the source of the thirty-ninth GaN tube; the thirty-seventh GaN tube is connected to the source; The drain of the GaN tube is connected to the power supply, the grid is connected to the source of the eighteenth GaN tube, the drain of the thirty-seventh GaN tube is connected to the source of the thirty-eighth GaN tube and one end of the eighth capacitor; the eighth capacitor The other end of the tube is connected to the source of the thirty-sixth GaN tube; the drain of the thirty-eighth GaN tube is connected to the power supply, and its gate and drain are interconnected; the drain of the thirty-ninth GaN tube is connected to the thirty-eighth GaN tube The source of the tube, the grid of the thirty-ninth GaN tube is connected to the source of the thirty-second GaN tube; the drain of the thirty-sixth GaN tube is the output terminal, connected to the grid of the GaN power tube.

The beneficial effects of the present invention are as follows: the cross-coupled charge pump is used to realize the rail-to-rail charging voltage of the bootstrap capacitor in the traditional bootstrap inverter, and the output rising speed and falling speed are realized while increasing the output rising speed of the bootstrap inverter Higher matching between speeds. Adding a power boost module to the traditional two-stage structure bootstrap inverter driving GaN power transistors increases the output voltage of the bias stage to three times the power supply voltage, increases the output voltage rise speed of the driver stage, and reduces the GaN power transistor The mismatch between the rising slope and falling slope of the gate reduces the delay of the drive chain, which is conducive to realizing a shorter turn-on time of the GaN power transistor. The four-level bootstrap inverter cascade is used to improve the matching between the turn-on delay and turn-off delay of the GaN power tube.

Description of drawings

Fig. 1 Schematic diagram of a traditional two-stage structure bootstrap inverter in an all-GaN gate drive integrated circuit.

FIG. 2 is a block diagram of a high-slew-rate all-GaN gate drive system proposed by the present invention.

FIG. 3 is a structure diagram of a high-slew-rate all-GaN gate drive circuit proposed by the present invention.

Fig. 4 is a working principle diagram when the GaN power tube is turned on by a high-slew-rate full-GaN gate driver proposed by the present invention

FIG. 5 is a working principle diagram of a high-slew-rate all-GaN gate drive proposed by the present invention when the GaN power transistor is turned off.

6 is a simulation diagram of a high-slew-rate full GaN gate-driven switching GaN power tube proposed by the present invention, wherein (a) is a simulation diagram of transmission delay, and (b) is a simulation diagram of GaN power transistor gate-source voltage.

Detailed ways

The working principle of the present invention will be described in detail below in conjunction with the accompanying drawings.

Accompanying drawing 3 has shown the circuit structure diagram of a kind of high slew rate all-GaN gate drive circuit proposed by the present invention, the transistors in this circuit all adopt enhancement mode GaN transistor, wherein GaN power tube is high-voltage tube, and other GaN tubes are low-voltage tube .

In the first-stage and second-stage bootstrap inverters, GaN transistors E ₄ , E ₉ and capacitors C ₁ , C ₂ form a cross-coupled charge pump between the first-stage and second-stage bootstrap inverters. The first-stage bootstrap inverter is composed of GaN tubes E ₁ , E ₂ , E ₃ , E ₄ , E ₅ , resistors R ₁ , R ₂ , R ₃ and capacitor C ₂ ; E ₂ is the output of the bootstrap inverter Pull-down tube, E ₃ is the bootstrap inverter output pull-up tube, E ₁ is used to turn off E ₃ to reduce static power consumption; R ₁ determines the charging voltage at both ends of C ₁ and determines the static power consumption; R ₂ , R ₃ and _E5 provide the initialization state for the first-level input and the second-level input. When the PWM signal is high, _E5 is turned off without consuming additional static power consumption. The second-stage bootstrap inverter is composed of GaN tubes E ₆ , E ₇ , E ₈ , E ₉ , E ₁₀ , resistor R ₄ and capacitor C ₂ ; E ₇ is the output pull-down tube of the bootstrap inverter, and E ₈ is The bootstrap inverter outputs a pull-up tube, E ₆ is used to turn off E ₈ to reduce static power consumption; R ₄ determines the charging voltage at both ends of C ₂ and determines the static power consumption; E ₁₀ provides initialization status for C ₂ , so that The initial voltage across C ₂ is higher than the threshold voltage of the low-voltage GaN tube.

In the third and fourth stage bootstrap inverters, GaN transistors E ₁₄ , E ₁₈ , E ₂₃ , E ₂₆ , E ₂₇ , E ₃₇ and capacitors C ₃ , C ₄ , C ₅ , C ₆ , C ₇ , C ₈ forms the cross-coupled charge pump between the third and fourth stage bootstrap inverters. In the third-stage bootstrap inverter, the bias stage is composed of GaN transistors E ₂₀ , E ₂₁ , E ₂₂ , E ₂₃ , resistor R ₅ and capacitor C ₄ , and the driver stage is composed of GaN transistors E ₂₄ , E ₂₅ , and E ₂₆ , E ₂₇ , E ₂₈ , resistor R ₆ and capacitor C ₅ ; where E ₂₁ , E ₂₅ are the bootstrap inverter output pull-down tubes in the bias stage and the driver stage, and E ₂₂ and E ₂₆ are the bias stage and The bootstrap inverter output pull-up tube in the driver stage, E ₂₀ and E ₂₄ are used to turn off E ₂₂ , E ₂₆ and E ₂₈ to reduce static power consumption; resistors R ₅ and R ₆ determine C ₄ and C ₅ The charging voltage at both ends determines the static power consumption. Resistor R ₇ is the initialization resistor; E ₁₉ is used to accelerate the charging speed of C ₄ to the gate-source capacitance of E ₁₇ , and increase the output rising speed of the third-stage bootstrap inverter. In the fourth-stage bootstrap inverter, the power boosting module consists of GaN tubes E ₂₀ , E ₂₁ , E ₂₂ , E ₂₃ , E ₂₄ , E ₂₅ , E ₂₆ , E ₂₇ , E ₂₈ , resistor R ₈ and capacitor C ₅ , C ₆ ; E ₂₁ and E ₂₂ are the output pull-down tube and output pull-up tube of the bootstrap inverter in the power boost module respectively, and E ₂₀ is used to turn off E ₂₂ to reduce static power consumption; the resistor R ₈ determines the charging voltage at both ends of C ₅ and determines the static power consumption; E ₂₄ , E ₂₅ , and E ₂₈ provide initialization states for C ₅ , C ₆ , and C ₇ respectively, so that the voltages at both ends of C ₅ , C ₆ , and C ₇ are high The threshold voltage of the low-voltage GaN tube; the bias stage is composed of GaN tubes E ₂₉ , E ₃₀ , E ₃₁ , E ₃₂ , E ₃₃ , resistors R ₉ , R ₁₀ and capacitor C ₇ , where E ₃₀ is the bootstrap inverter of the bias stage Inverter output pull-down tube, E ₃₁ is the bias stage bootstrap inverter output pull-up tube, E ₂₉ is used to turn off E ₃₁ and E ₃₃ , E ₃₂ is used to turn off the subsequent charging tube E ₃₉ , reducing the static Power consumption; resistors R ₉ and R ₁₀ determine the charging voltage across C ₇ and determine static power consumption; the driver stage consists of GaN tubes E ₃₄ , E ₃₅ , E ₃₆ , E ₃₇ , E ₃₈ , E ₃₉ , resistor R ₁₁ and capacitor Composed of C ₈ ; where E ₃₅ is the output pull-down tube of the driver stage bootstrap inverter, E ₃₆ is the output pull-up tube of the driver stage bootstrap inverter, and E ₃₄ is used to turn off E ₃₆ to realize zero static power consumption of the driver stage ; Use the GaN tube E ₃₉ working in the linear region to replace the resistor to increase the output rise rate of the driver stage; E ₃₈ provides an initialization state for C ₈ , so that the voltage at both ends of C ₈ is higher than the threshold voltage of the low-voltage GaN tube; R ₁₁ is turned on and off A dead time is generated between _E35 and _E36 to prevent _E35 and _E36 from being turned on at the same time.

The specific working principle of the circuit is shown in accompanying drawing 4 and accompanying drawing 5.

Accompanying drawing 4 is the working principle diagram when a GaN power tube is turned on by a high-slew-rate all-GaN gate driver proposed by the present invention. In the case that the bootstrap capacitors C _1N , C _3N and C _4N have not been charged, when the PWM signal is logic low, the GaN transistors E _10N , E _24N , E _28N and E _38N with the gate-to-drain short circuit will bootstrap The voltage across capacitors C _2N , C _5N , C _6N and C _8N is charged to VCC-V _TH , and the gate-to-source GaN tube E _25N charges the voltage across C _7N to VCC-V _TH (V _TH is a low-voltage GaN tube The threshold voltage of C _2N , C _5N , C _6N , C _7N and C _8N are initialized. When the PWM flips from logic low to logic high, the output V _O1N of the first-stage bootstrap inverter is quickly pulled down to GND by E _2N ; in the second-stage bootstrap inverter, because there is initialization on the bootstrap capacitor C _2N Voltage VCC-V _TH , the output V _O2N is pulled up to VCC by E _8N . Through the cross-coupled charge pump between the first-stage and second-stage bootstrap inverters, the gate potential of E _4N rises to 2VCC-V _TH , and E _4N works in the deep linear region. When R _1N is much larger than that of E _4N When turning on the resistance, the voltage across C _1N is charged to VCC by E _4N . The third-stage bootstrap inverter output V _O3N is quickly pulled down to GND by E _16N . In the fourth-stage bootstrap inverter, there is an initialization voltage VCC-V _TH on C _5N , C _6N , C _7N and C _8N , and the output V _O41N of the bootstrap inverter in the power boost module is pulled up to VCC by E _22N . Through the cross-coupled charge pump between the third-stage and fourth-stage bootstrap inverters, the gate potential of E _14N and E _18N rises to 2VCC-V _TH , E _14N and E _18N work in the deep linear region, when R When _5N and R _6N are much larger than the on-resistance of E _14N and E _18N , the voltages across C _3N and C _4N are charged to VCC by E _14N and E _18N respectively. Through the bootstrap capacitor C _6N , the power rail of the bias stage of the fourth-stage bootstrap inverter is raised to 2VCC-V _TH . The bootstrap inverter output V _O42N in the bias stage is pulled up to 2VCC-V _TH by E _31N , and the upper plate potential of C _7N is 3VCC-2V _TH . E _33N is driven by R _9N , and E _39N is driven by E _33N and R _10N in parallel, and the gate voltage of E _39N finally rises to 3VCC-2V _TH . After E _39N is turned on, it has been working in the linear region, and the on-resistance is small. C _8N drives E _36N through E _39N working in the linear region, which can quickly turn on E _36N and increase the rising speed of V _GN at the gate terminal of the GaN power tube.

When the voltage across the bootstrap capacitors C _1N , C _3N and C _4N has been charged to VCC, when the PWM signal is logic low, the first and second bootstrap inverters and the third and third The cross-coupled charge pump between the fourth-stage bootstrap inverters, the voltages at both ends of C _2N , C _5N , C _6N , C _7N and C _8N are respectively operated in the linear region of E _9N , E _23N , E _27N , E _26N and E _37N are charged to VCC. At this time, the voltage across all bootstrap capacitors in the gate drive is VCC, and there is no loss of threshold voltage. When PWM turns from logic low to logic high, V _O1N can be quickly pulled down to GND by E _2N , V _O2N can be quickly pulled up to VDD by E _8N , and V _O3N can be quickly pulled down to GND by E _16N . In the fourth-stage bootstrap inverter, the power boost module boosts the power rail of the bias stage to 2VCC, and the bias stage boosts the gate voltage of the E _39N to 3VCC. Through step-by-step driving from R _9N through E _33N to E _39N and increasing the gate potential of E _39N , the driving ability of E _39N to E _36N is greatly improved, and the delay from V _O3N falling to V _GN rising hour. In the case that the aspect ratio of E _36N is much higher than that of E _17N , it can ensure that the rising speed of V _GN and V _O3N is close, and improve the matching between the rising edge transmission delay and the falling edge transmission delay of the gate drive.

Accompanying drawing 5 is a working principle diagram of a high-slew-rate all-GaN gate driver of the present invention when the GaN power tube is turned off. When the PWM signal is logic high, C _1F , C _3F and C _4F are charged to VCC through the cross-coupled charge pump. When PWM flips from logic high to logic low, V _O1F is quickly pulled up to VDD by E _3F , V _O2F is quickly pulled down to GND by E _7F , and E _9F working in the deep linear region charges the voltage across C _2F to VCC , E _10F off. The bias stage of the third-stage bootstrap inverter drives E _19F to quickly turn on E _17F to increase the rising speed of V _O3F , and V _O3F is finally pulled up to VCC by E _17F . In the fourth-stage bootstrap inverter, E _23F , E _26F , E _27F and E _37F work in the deep linear region, E _24F , E _25F , E _28F and E _38F are turned off, and C _5F , C _6F , C _7F The voltage across _8F and C is charged to VCC, the bias stage supply voltage is VCC. E _35F can turn off GaN power tube quickly. E _25F and E _26F use the drain to charge C _7F to avoid the risk of gate oxide breakdown of low-voltage GaN devices when the upper plate potential of C _7F is bootstrapped to 3VCC.

Figure 6(a) is a simulation result diagram of the transmission delay of the all-GaN gate drive circuit proposed by the present invention. The delay from PWM input rising 50% to GaN power transistor gate (V _GS ) rising 50% is 12.9ns, and the delay from PWM input falling 50% to GaN power transistor gate falling 50% is 14.1ns. The delay difference between turning on and off the gate terminal of the GaN power transistor is 1.2ns. The turn-on delay from PWM input rising 50% to GaN power transistor drain voltage (V _DS ) falling to 90% is 13.8ns, and the turn-off delay from PWM input falling 50% to GaN power transistor drain voltage rising to 10% The time is 13.6ns. The delay difference between turning on and off the drain of the GaN power transistor is 0.2ns. The all-GaN gate drive circuit proposed by the present invention has low driving delay and good delay matching.

Accompanying drawing 6 (b) is the simulation result diagram of the GaN power tube gate-source voltage in the all-GaN gate drive circuit proposed by the present invention. The time for the gate voltage of the GaN power tube to rise from 10% to 90% is 2.2ns, and the time for the gate voltage to drop from 90% to 10% is 2.3ns. The GaN power transistor gate has high turn-on and turn-off speeds, and the rising slope and falling slope of the gate have good matching.

In summary, the all-GaN gate drive circuit proposed by the present invention adds a cross-coupled charge pump to the traditional all-GaN bootstrap inverter, which realizes the charging voltage of the bootstrap capacitor rail-to-rail and improves the bootstrap inverter. The output rise speed is improved, and the matching of the bootstrap inverter output rise slope and fall slope is improved at the same time. A power boost module is added to the traditional two-stage structure bootstrap inverter that drives the gate terminal of GaN power transistors to increase the output voltage of the bias stage to three times the power supply voltage, which improves the gate rise speed of GaN power transistors and reduces the gate voltage. The mismatch between rising slope and falling slope realizes high-speed and high-slew-rate driving. The even-numbered (four-stage) bootstrap inverter cascading method achieves good matching between the turn-on delay and turn-off delay of the GaN power transistor.

Claims (2)

1. A full GaN gate drive circuit with a high slew rate, characterized in that it comprises a first-stage bootstrap inverter, a second-stage bootstrap inverter, and a third-stage bootstrap inverter cascaded in sequence and the fourth-stage bootstrap inverter, between the first-stage bootstrap inverter and the second-stage bootstrap inverter, between the third-stage bootstrap inverter and the fourth-stage bootstrap inverter Both have cross-coupled charge pumps; among them, the bias stage and driver stage are cascaded in the third stage of the bootstrap inverter, and the bias stage provides the bias voltage of twice the power supply voltage for the driver stage to improve the In the fourth-stage bootstrap inverter, on the basis of cascading the bias stage and the driver stage, a power boost circuit is used to increase the power supply voltage of the bias stage to twice the gate drive power supply voltage, Then provide a bias voltage three times the power supply voltage for the driver stage, and increase the output rise rate of the fourth-stage bootstrap inverter; the input of the first-stage bootstrap inverter is a PWM signal, and the fourth-stage bootstrap inverter The output of the GaN power transistor is connected to the gate; all transistors in the circuit are enhancement GaN transistors. 2. A full GaN gate drive circuit with a high slew rate according to claim 1, wherein the first-stage bootstrap inverter comprises a first GaN transistor, a second GaN transistor, a third GaN transistor tube, a fourth GaN tube, a fifth GaN tube, a first resistor, a second resistor, a third resistor and a first capacitor, and the second stage bootstrap inverter includes a sixth GaN tube, a seventh GaN tube, a Eight GaN tubes, a ninth GaN tube, a tenth GaN tube, a fourth resistor and a second capacitor; wherein, the gates of the first GaN tube and the second GaN tube are connected to the PWM signal, and the drain of the first GaN tube passes through the first The resistor is connected to the source of the fourth GaN tube, the source of the first GaN tube is grounded, the drain of the second GaN tube is connected to the source of the third GaN tube, and the source of the second GaN tube is grounded; The drain is connected to the power supply, and its gate is connected to the source of the fourth GaN tube through the first resistor; the drain of the fourth GaN tube is connected to the power supply, and its gate is connected to the source of the ninth GaN tube; the source of the fourth GaN tube The connection point between the electrode and the first resistor is connected to one end of the first capacitor, the other end of the first capacitor is connected to the source of the third GaN tube and one end of the second resistor, and the other end of the second resistor is connected to the power supply; The drain is connected to the PWM signal after passing through the third resistor, its gate is connected to one end of the second resistor, and its source is grounded; the drain of the sixth GaN tube is connected to the source of the tenth GaN tube through the fourth resistor, and the sixth GaN The gate of the tube is connected to one end of the second resistor, and its source is grounded; the drain of the seventh GaN tube is connected to the source of the eighth GaN tube, and the gate of the seventh GaN tube is connected to one end of the second resistor, and its source is grounded The drain of the eighth GaN tube is connected to the power supply, and its grid is connected to the source of the tenth GaN tube after passing through the fourth resistor; the drain of the ninth GaN tube is connected to the power supply, and its grid is connected to the source of the fourth GaN tube, The source of the ninth GaN tube is connected to the source of the tenth GaN tube and one end of the second capacitor, and the other end of the second capacitor is connected to the source of the eighth GaN tube; the drain of the tenth GaN tube is connected to the power supply, and the gate It is interconnected with the drain; the source of the eighth GaN transistor is the output terminal of the second-stage bootstrap inverter; the fourth GaN transistor, the ninth GaN transistor, the first capacitor and the second capacitor constitute the first-stage bootstrap inverter A cross-coupled charge pump between the phaser and the second-stage bootstrap inverter; The third-level bootstrap inverter includes an eleventh GaN transistor, a twelfth GaN transistor, a thirteenth GaN transistor, a fourteenth GaN transistor, a fifteenth GaN transistor, a sixteenth GaN transistor, a seventeenth GaN transistor GaN tube, eighteenth GaN tube, nineteenth GaN tube, fifth resistor, sixth resistor, seventh resistor, third capacitor, and fourth capacitor, eleventh GaN tube, twelfth GaN tube, thirteenth GaN tube The GaN tube, the fourteenth GaN tube, the third capacitor and the fifth resistor form a bias stage, the fifteenth GaN tube, the sixteenth GaN tube, the seventeenth GaN tube, the eighteenth GaN tube, and the nineteenth GaN tube , the sixth resistor, the seventh resistor and the fourth capacitor constitute the driving stage; the fourth-stage bootstrap inverter includes a twenty-first GaN tube, a twenty-first GaN tube, a twenty-second GaN tube, a twenty-second GaN tube, and a twenty-second GaN tube. Three GaN tubes, twenty-fourth GaN tubes, twenty-fifth GaN tubes, twenty-sixth GaN tubes, twenty-seventh GaN tubes, twenty-eighth GaN tubes, twenty-ninth GaN tubes, and thirty GaN tubes tube, thirty-first GaN tube, thirty-second GaN tube, thirty-third GaN tube, thirty-fourth GaN tube, thirty-fifth GaN tube, thirty-sixth GaN tube, thirty-seventh GaN tube , the thirty-eighth GaN tube, the thirty-ninth GaN tube, the eighth resistor, the ninth resistor, the tenth resistor, the eleventh resistor, the fifth capacitor, the sixth capacitor, the seventh capacitor and the eighth capacitor, the second Ten GaN tubes, twenty-first GaN tubes, twenty-second GaN tubes, twenty-third GaN tubes, twenty-fourth GaN tubes, twenty-fifth GaN tubes, twenty-sixth GaN tubes, twenty-seventh GaN tubes The GaN tube, the twenty-eighth GaN tube, the fifth capacitor, the sixth capacitor, and the eighth resistor form a power booster, the twenty-ninth GaN tube, the thirty-first GaN tube, the thirty-first GaN tube, and the thirty-second GaN tube The 33rd GaN tube, the 9th resistor, and the 7th capacitor form a bias stage, the 34th GaN tube, the 35th GaN tube, the 36th GaN tube, the 37th GaN tube, the 37th GaN tube The thirty-eighth GaN tube, the thirty-ninth GaN tube, the eighth capacitor, and the eleventh resistor constitute the driving stage; wherein, The drain of the eleventh GaN tube is connected to the source of the fourteenth GaN tube through the fifth resistor, the gate of the eleventh GaN tube is connected to the source of the eighth GaN tube, and the source of the eleventh GaN tube is grounded; The drain of the twelfth GaN tube is connected to the source of the thirteenth GaN tube, the gate of the twelfth GaN tube is connected to the source of the eighth GaN tube, and the source of the twelfth GaN tube is grounded; the thirteenth GaN tube The drain of the GaN tube is connected to the power supply, and the grid is connected to the source of the fourteenth GaN tube through the fifth resistor; the drain of the fourteenth GaN tube is connected to the power supply, and the connection point between the source and the fifth resistor is connected to the third capacitor One end, the other end of the third capacitor is connected to the source of the thirteenth GaN tube; the drain of the fifteenth GaN tube is connected to the source of the nineteenth GaN tube, and the gate of the fifteenth GaN tube is connected to the eighth GaN tube source, the source of the fifteenth GaN tube is grounded; the drain of the sixteenth GaN tube is connected to the source of the seventeenth GaN tube, the gate of the sixteenth GaN tube is connected to the source of the eighth GaN tube, and the drain of the sixteenth GaN tube is connected to the source of the eighth GaN tube. The source of the sixth GaN tube is grounded; the drain of the seventeenth GaN tube is connected to the power supply, and the gate is connected to the source of the nineteenth GaN tube; the drain of the eighteenth GaN tube is connected to the power supply, and the gate is connected to the twenty The sources of the three GaN tubes, the source of the eighteenth GaN tube is connected to the drain of the nineteenth GaN tube and one end of the fourth capacitor, and the other end of the fourth capacitor is connected to the source of the seventeenth GaN tube; the nineteenth A sixth resistor is connected between the drain and the source of the GaN tube; the source of the seventeenth GaN tube is connected to one end of the seventh resistor, and the other end of the seventh resistor is connected to a power supply; The drain of the twentieth GaN tube is connected to the source of the twenty-fourth GaN tube through the eighth resistor, the gate of the twenty-first GaN tube is connected to one end of the seventh resistor, and the source is grounded; the twenty-first GaN tube The drain of the twenty-second GaN tube is connected to the source of the twenty-second GaN tube, the gate of the twenty-first GaN tube is connected to one end of the seventh resistor, and the source is grounded; the drain of the twenty-second GaN tube is connected to the power supply, and the gate Connect the source of the twenty-fourth GaN tube through the eighth resistor; the drain of the twenty-third GaN tube is connected to the power supply, the grid is connected to the source of the eighteenth GaN tube, and the source of the twenty-third GaN tube is connected to The source of the twenty-fourth GaN tube and one end of the fifth capacitor, the other end of the fifth capacitor is connected to the source of the twenty-second GaN tube; the drain of the twenty-fourth GaN tube is connected to the power supply, and its grid and drain The gate and source of the twenty-fifth GaN tube are connected to the power supply, the drain of the twenty-fifth GaN tube is connected to the drain of the twenty-sixth GaN tube; the source of the twenty-sixth GaN tube is connected to the power supply , the gate of which is connected to the source of the eighteenth GaN tube; the gate of the twenty-seventh GaN tube is connected to the gate of the twenty-sixth GaN tube, and the drain of the twenty-seventh GaN tube is connected to the power supply; The source of the GaN tube is connected to the source of the twenty-eighth GaN tube; the drain and gate of the twenty-eighth GaN tube are connected to the power supply; one end of the sixth capacitor is connected to the source of the twenty-seventh GaN tube, and the sixth The other end of the capacitor is connected to the source of the twenty-second GaN tube; the drain of the twenty-ninth GaN tube is connected to the grid of the thirty-first GaN tube, the grid of the thirty-third GaN tube, and the gate of the twenty-ninth GaN tube The drain of the 26th GaN tube is connected to the drain of the 26th GaN tube, one end of the seventh capacitor, and the drain of the 33rd GaN tube through the ninth resistor, and the gate of the 29th GaN tube is connected to the 7th resistor. One end, its source is grounded; the drain of the 30th GaN tube is connected to the source of the 31st GaN tube, the gate of the 30th GaN tube is connected to one end of the seventh resistor, and its source is grounded; the 31st GaN tube is connected to the source of the seventh resistor; The drain of the GaN tube is connected to the source of the 28th GaN tube, the source of the 31st GaN tube is connected to the drain of the 30th GaN tube; the drain of the 32nd GaN tube is connected to the drain of the 33rd GaN tube The source of the thirty-ninth GaN tube and the grid of the thirty-ninth GaN tube, the grid of the thirty-second GaN tube is connected to the grid of the thirty-second GaN tube, the source of the thirty-second GaN tube is grounded; the thirty-third GaN tube There is a tenth resistor between the drain and the source of the capacitor; the other end of the seventh capacitor is connected to the source of the thirty-first GaN tube and the drain of the thirty-first GaN tube; the drain of the thirty-fourth GaN tube is connected to the The source of the thirty-ninth GaN tube, the gate of the thirty-fourth GaN tube is connected to one end of the seventh resistor, and the source is grounded; the drain of the thirty-fifth GaN tube is connected to the source of the thirty-sixth GaN tube, The gate of the thirty-fifth GaN tube is connected to one end of the seventh resistor through the eleventh resistor, and its source is grounded; the drain of the thirty-sixth GaN tube is connected to the power supply, and its grid is connected to the terminal of the thirty-ninth GaN tube source; the drain of the thirty-seventh GaN tube is connected to the power supply, the grid is connected to the source of the eighteenth GaN tube, the source of the thirty-seventh GaN tube is connected to the source of the thirty-eighth GaN tube and the eighth One end of the capacitor, the grid of the thirty-seventh GaN tube is connected to the grid of the twenty-seventh GaN tube; the other end of the eighth capacitor is connected to the source of the thirty-sixth GaN tube; the drain of the thirty-eighth GaN tube connected to the power supply, and its gate and drain are interconnected; the drain of the thirty-ninth GaN tube is connected to the source of the thirty-eighth GaN tube, and the gate of the thirty-ninth GaN tube is connected to the source of the thirty-second GaN tube pole; the source of the thirty-sixth GaN tube is the output terminal, which is connected to the gate of the GaN power tube.

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