CN114531156A - Clock generating circuit and interleaved sampling device - Google Patents
Clock generating circuit and interleaved sampling device Download PDFInfo
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- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
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Abstract
The application comprises a clock generating circuit and an interleaving sampling device, and particularly relates to the technical field of signal sampling. In the circuit, a phase-locked loop clock unit is connected with a first clock distributor to convert a generated first differential signal into a first clock signal and a second clock signal; the first phase-locked loop converts the first clock signal into a second differential signal; the second clock distributor converts the second differential signal into a third clock signal and a fourth clock signal with a phase difference of 180 degrees and transmits the third clock signal and the fourth clock signal to the analog-to-digital conversion chip; the second phase-locked loop converts the second clock signal into a third differential signal, and the third clock distributor converts the third differential signal into a fifth clock signal and a sixth clock signal with a phase difference of 180 degrees and transmits the fifth clock signal and the sixth clock signal to the analog-to-digital conversion chip. The scheme can accurately control the interleaved sampling of the four analog-to-digital conversion chips, avoids the sampling time interval mismatch of the sampling of a plurality of ADC chips, and improves the sampling precision of the four analog-to-digital conversion chips during the interleaved sampling.
Description
Technical Field
The invention relates to the technical field of signal sampling, in particular to a clock generation circuit and an interleaving sampling device.
Background
High-speed Analog-to-Digital Converters (ADCs) have a wide range of applications and prospects, and at present, ADCs are the next very popular field.
Due to the limitations of semiconductor processing techniques and technology levels, the development speed of ADCs is correspondingly limited. Based on the development of the current CMOS process, the minimum size of the process is continuously reduced, the power supply voltage is continuously reduced, and the allowable amplitude of the input signal is smaller and smaller, resulting in a reduction in the signal-to-noise ratio. Resolution and sampling frequency are two important performance indicators of the ADC; the speed and the precision of the ADC are in a pair of contradiction, so that the development of the ADC to a high-speed high-precision direction is limited, the resolution of the ADC is inevitably reduced by increasing the sampling rate of the ADC, and therefore, the signals can be interleaved and sampled by controlling the clocks of a plurality of ADC chips, for example, when the two ADC chips are used for interleaved and sampled, a differential clock signal can be directly split into two paths of independent clock signals, so that the phase difference of the two ADC chips is ensured to be 180 degrees.
In the above scheme, when signals need to be interleaved and sampled by a plurality of ADC chips, it is difficult to accurately control clock phases of the plurality of ADC chips.
Disclosure of Invention
The application provides a clock generating circuit and an interleaved sampling device, which can accurately control the clock phase of a plurality of ADC chips.
In one aspect, the present application provides a clock generation circuit, which includes a phase-locked loop clock unit, a first phase-locked loop, a second phase-locked loop, a first clock distributor, a second clock distributor, and a third clock distributor;
the phase-locked loop clock unit is connected with the first clock distributor so as to convert the first differential signal generated by the phase-locked loop clock unit into a first clock signal and a second clock signal, and distribute the first clock signal and the second clock signal to the first phase-locked loop and the second phase-locked loop;
the first phase-locked loop converts the first clock signal into a second differential signal and transmits the second differential signal to a second clock distributor, so that the second clock distributor converts the second differential signal into a third clock signal and a fourth clock signal with a phase difference of 180 degrees;
the second phase-locked loop converts the second clock signal into a third differential signal and transmits the third differential signal to a third clock distributor, so that the third clock distributor converts the third differential signal into a fifth clock signal and a sixth clock signal with a phase difference of 180 degrees;
the second differential signal is 90 ° out of phase with the third differential signal;
and the third clock signal, the fourth clock signal, the fifth clock signal and the sixth clock signal are respectively connected to the four analog-to-digital conversion chips so as to control the interleaved sampling of the four analog-to-digital conversion chips.
In a possible implementation manner, the phase-locked loop clock unit is further configured to send the reference clock to the first phase-locked loop and the second phase-locked loop, respectively, so as to control the operating states of the first phase-locked loop and the second phase-locked loop.
In one possible implementation, the phase-locked loop clock unit includes a clock chip and a target phase-locked loop;
and the clock chip transmits the generated reference clock to a target phase-locked loop, and the target phase-locked loop generates the first differential signal according to the reference clock.
In a possible implementation manner, the first phase-locked loop further includes a first D flip-flop and a first internal oscillator; the second phase-locked loop also comprises a second D trigger and a second internal oscillator;
the first phase locked loop converts the first clock signal to a second differential signal, comprising:
after the first internal oscillator generates a first candidate differential signal according to the first clock signal, transmitting the first candidate differential signal to the first D flip-flop to output the second differential signal;
the second phase locked loop converts the second clock signal into a third differential signal, including:
and after the second internal oscillator generates a second candidate differential signal according to the second clock signal, transmitting the second candidate differential signal to the second D flip-flop through an NOT gate so as to output the third differential signal.
In a possible implementation manner, the first phase-locked loop includes a third internal oscillator, a third D flip-flop, and a fourth D flip-flop; the second phase-locked loop also comprises a fourth internal oscillator, a fifth D trigger and a sixth D trigger;
the third internal oscillator is connected with the third D trigger;
the third internal oscillator is connected with the fourth D trigger through a NOT gate;
the fourth internal oscillator is connected with the fifth D trigger;
the fourth internal oscillator is connected with the fifth D flip-flop through a NOT gate;
the first phase-locked loop and the second phase-locked loop also comprise chip registers; and the chip register is used for controlling the conduction state of each D trigger according to the data in the chip register.
On the other hand, the application also provides an interleaving sampling device, which comprises any one of the above selectable modes of the clock generation circuit;
the interleaving sampling device also comprises various sampling and holding chips; and each sampling and holding chip is respectively connected with the four analog-to-digital conversion chips so as to carry out sampling and holding processing on the acquired data and then send the data to the four analog-to-digital conversion chips.
In a possible implementation manner, the third clock signal, the fourth clock signal, the fifth clock signal, and the sixth clock signal are respectively connected to a sample-and-hold chip to which four analog-to-digital conversion chips are connected, so as to control data processing of the sample-and-hold chip.
In a possible implementation manner, the interleaved sampling apparatus further includes delay chips;
the third clock signal, the fourth clock signal, the fifth clock signal and the sixth clock signal are respectively transmitted to the four analog-to-digital conversion chips after being processed by the delay chips; and the third clock signal, the fourth clock signal, the fifth clock signal and the sixth clock signal are respectively transmitted to the sampling holding chips respectively connected with the four analog-to-digital conversion chips after being processed by the delay chips.
In a possible implementation manner, the interleaving and sampling device further includes a sampling control chip; the sampling control chip is connected with the delay chip through a digital-to-analog conversion chip.
In a possible implementation manner, the sampling control chip further includes an interleaving calibration module, and the interleaving calibration module is configured to calibrate the digital signals generated by the four analog-to-digital conversion chips, so as to obtain a target sampling result.
The technical scheme provided by the application can comprise the following beneficial effects:
when the four analog-to-digital conversion chips are needed to perform interleaved sampling, a phase-locked loop clock unit in the circuit generates a first differential signal, the first differential signal can be transmitted to a clock distributor, the clock distributor splits the first differential signal into a first clock signal and a second clock signal with a phase difference of 180 degrees, the first clock signal and the second clock signal are processed by the first phase-locked loop and the second phase-locked loop respectively to generate a second differential signal and a third differential signal with a phase difference of 90 degrees, the second clock distributor and the third clock distributor split the second differential signal and the third differential signal into clock signals with a phase difference of 180 degrees, the third clock signal, the fourth clock signal, the fifth clock signal and the sixth clock signal obtained by splitting at the moment have a phase difference of 90 degrees, and therefore the third clock signal, the fourth clock signal, the fifth clock signal and the sixth clock signal are obtained by the third clock signal, The fourth clock signal, the fifth clock signal and the sixth clock signal can accurately control the interleaved sampling of the four analog-to-digital conversion chips, thereby avoiding the sampling time interval mismatch of the sampling of a plurality of ADC chips and improving the sampling precision of the four analog-to-digital conversion chips during the interleaved sampling.
Drawings
In order to more clearly illustrate the detailed description of the present application or the technical solutions in the prior art, the drawings needed to be used in the detailed description of the present application or the prior art description will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.
Fig. 1 is a schematic diagram illustrating a structure of a clock generation circuit according to an exemplary embodiment of the present application.
Fig. 2 shows a schematic diagram of a clock link according to an embodiment of the present application.
Fig. 3 is a schematic diagram illustrating a structure of an interleaved sampling device according to an exemplary embodiment.
Fig. 4 shows a frequency output diagram of a phase-locked loop according to an embodiment of the present application.
Fig. 5 is a schematic diagram illustrating another phase-locked loop frequency output according to an embodiment of the present application.
Fig. 6 shows a schematic diagram of a variable delay limit structure according to an embodiment of the present application.
Detailed Description
The technical solutions of the present application will be described clearly and completely with reference to the accompanying drawings, and it should be understood that the described embodiments are only some embodiments of the present application, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
It should be understood that "indication" mentioned in the embodiments of the present application may be a direct indication, an indirect indication, or an indication of an association relationship. For example, a indicates B, which may mean that a directly indicates B, e.g., B may be obtained by a; it may also mean that a indicates B indirectly, for example, a indicates C, and B may be obtained by C; it can also mean that there is an association between a and B.
In the description of the embodiments of the present application, the term "correspond" may indicate that there is a direct correspondence or an indirect correspondence between the two, may also indicate that there is an association between the two, and may also indicate and be indicated, configure and configured, and so on.
In the embodiment of the present application, "predefining" may be implemented by saving a corresponding code, table, or other manners that may be used to indicate related information in advance in a device (for example, including a terminal device and a network device), and the present application is not limited to a specific implementation manner thereof.
Fig. 1 is a schematic diagram illustrating a structure of a clock generation circuit according to an exemplary embodiment of the present application. As shown in fig. 1, the clock generation circuit includes a phase-locked loop clock unit, a first phase-locked loop, a second phase-locked loop, a first clock distributor, a second clock distributor, and a third clock distributor;
the phase-locked loop clock unit is connected with the first clock distributor so as to convert the first differential signal generated by the phase-locked loop clock unit into a first clock signal and a second clock signal and distribute the first clock signal and the second clock signal to the first phase-locked loop and the second phase-locked loop;
the first phase-locked loop converts the first clock signal into a second differential signal and transmits the second differential signal to a second clock distributor, so that the second clock distributor converts the second differential signal into a third clock signal and a fourth clock signal with a phase difference of 180 degrees;
the second phase-locked loop converts the second clock signal into a third differential signal and transmits the third differential signal to a third clock distributor, so that the third clock distributor converts the third differential signal into a fifth clock signal and a sixth clock signal with a phase difference of 180 degrees;
the second differential signal is 90 ° out of phase with the third differential signal;
the third, fourth, fifth and sixth clock signals are used to control the interleaved sampling of the four analog-to-digital conversion chips (i.e., ADCs).
In order to implement ADC interleaved sampling, a clock chain (i.e., a clock generation circuit as shown in fig. 1) is first constructed to provide sampling clocks to four ADC chips. Considering the synchronous and equal-interval sampling of the four-way ADC, a phase-locked loop and a crystal oscillator are required to jointly generate a clock signal such as 3 Ghz. At present, two paths of ADC interweaving are carried out on a traditional ADC board card, and a sampling clock with a phase difference of 180 degrees can be obtained only by generating a differential signal by a clock chip.
Referring to fig. 2, a schematic diagram of a clock link according to an embodiment of the present application is shown. As shown in fig. 2, the clock divider is a chip for clock distribution, and the first clock divider divides the differential signal generated by the pll 1 chip (i.e., the pll clock unit) into two paths to provide clocks to the two pll 2 chips (i.e., the first pll and the second pll in fig. 1). The clock generated by the phase-locked loop 1 is generated by a reference clock, and the clock chip provides the phase-locked loop 1 with a reference clock to generate a subsequent required clock signal. The 3Ghz differential signal output generated by the first pll 2 chip (i.e., the first pll) is converted into two signals with a phase difference of 180 degrees by the clock buffer1 (i.e., the second clock divider), so that the two signals respectively provide sampling clocks for the first and third ADCs (i.e., ADC0 and ADC 3). Wherein the second pll 2 chip (i.e. the second pll) may generate signals with a phase difference of 90 degrees with respect to the output.
At this time, the differential signal generated by the phase-locked loop 2 is also passed through the clock buffer (i.e., the third clock distributor) to generate two signals with a phase difference of 180 °, i.e., 90 ° and 270 ° to the second and fourth ADCs (i.e., ADC1 and ADC 3). Therefore, the four ADCs can generate 90-degree sampling clock phases, and the four ADCs perform time-interleaved alternate sampling to achieve the purpose of initial design.
In a possible implementation manner of the embodiment of the present application, the phase-locked loop clock unit is formed by a phase-locked loop circuit and a clock chip, and after the clock chip generates the reference clock, the phase-locked loop circuit generates the first differential signal.
At this time, after the phase-locked loop circuit generates the first differential signal, the first differential signal may be input to a first clock distributor, and the first clock distributor (i.e., a clock buffer) may distribute the first differential signal, for example, by converting the first differential signal into two single-ended circuits through PN inversion, i.e., generate the first clock signal and the second clock signal, where a phase difference between the first clock signal and the second clock signal is 180 °. Assuming that the phase of the first clock signal at a given time is 0 deg., the phase of the second clock signal at a given time is 180 deg..
At this time, the first clock signal is transmitted to the first phase-locked loop, the first phase-locked loop generates a second differential signal according to the first clock signal, and transmits the second differential signal to the second clock distributor, and at this time, the second clock distributor converts the second differential signal into a third clock signal and a fourth clock signal having a phase difference of 180 °. At this time, if the phase of the third clock signal at the predetermined time is 0 °, the phase of the fourth clock signal at the predetermined time is 180 °.
And the second clock signal is transmitted to a second phase-locked loop, the second phase-locked loop generates a third differential signal according to the first clock signal, the phase difference between the third differential signal and the second differential signal is 90 degrees, and the third differential signal is converted into a fifth clock signal and a sixth clock signal with a phase difference of 180 degrees, namely, the phase of the fifth clock signal at a specified time is 90 degrees and the phase of the sixth clock signal at the specified time is 270 degrees, or the phase of the fifth clock signal at the specified time is 270 degrees and the phase of the sixth clock signal at the specified time is 90 degrees.
Therefore, the third clock signal, the fourth clock signal, the fifth clock signal and the sixth clock signal form four clock signals with a phase difference of 90 degrees, the four analog-to-digital conversion chips are controlled through the four clock signals, the four analog-to-digital conversion chips can have the same sampling time and sampling time interval, the sampling time interval mismatch of sampling of a plurality of ADC chips is avoided, and the sampling precision of the four analog-to-digital conversion chips in interleaved sampling is improved.
In summary, when the four analog-to-digital conversion chips are required to perform interleaved sampling, after a phase-locked loop clock unit in the circuit generates a first differential signal, the first differential signal may be transmitted to a clock distributor, the clock distributor splits the first differential signal into a first clock signal and a second clock signal with a phase difference of 180 °, at this time, the first clock signal and the second clock signal are processed by the first phase-locked loop and the second phase-locked loop, respectively, to generate a second differential signal and a third differential signal with a phase difference of 90 °, at this time, the second clock distributor and the third clock distributor split the second differential signal and the third differential signal into clock signals with a phase difference of 180 °, at this time, the split third clock signal, the fourth clock signal, the fifth clock signal and the sixth clock signal have a phase difference of 90 °, so that the third clock signal, the fourth clock signal, the fifth clock signal, the sixth clock signal, and the clock signal are obtained by the third clock signal, The fourth clock signal, the fifth clock signal and the sixth clock signal can accurately control the interleaved sampling of the four analog-to-digital conversion chips, thereby avoiding the sampling time interval mismatch of the sampling of a plurality of ADC chips and improving the sampling precision of the four analog-to-digital conversion chips during the interleaved sampling.
Fig. 3 is a schematic diagram illustrating a structure of an interleaved sampling device according to an exemplary embodiment. As shown in fig. 3, the interleaved sampling apparatus includes a phase-locked loop clock unit, a first phase-locked loop, a second phase-locked loop, a first clock distributor, a second clock distributor and a third clock distributor;
the phase-locked loop clock unit comprises a clock chip and a target phase-locked loop;
the clock chip transmits the generated reference clock to a target phase-locked loop, and the target phase-locked loop generates a first differential signal according to the reference clock.
The phase-locked loop clock unit is connected with the first clock distributor so as to convert the first differential signal generated by the phase-locked loop clock unit into a first clock signal and a second clock signal and distribute the first clock signal and the second clock signal to the first phase-locked loop and the second phase-locked loop;
the first phase-locked loop converts the first clock signal into a second differential signal and transmits the second differential signal to a second clock distributor, so that the second clock distributor converts the second differential signal into a third clock signal and a fourth clock signal with a phase difference of 180 degrees;
the second phase-locked loop converts the second clock signal into a third differential signal and transmits the third differential signal to a third clock distributor, so that the third clock distributor converts the third differential signal into a fifth clock signal and a sixth clock signal with a phase difference of 180 degrees;
the second differential signal is 90 ° out of phase with the third differential signal.
The principle of the clock generation circuit is similar to that of the clock generation circuit shown in fig. 1, and is not described herein again.
In the embodiment of the present application, as shown in fig. 3, the interleaved sampling apparatus further includes the four analog-to-digital conversion chips; the four analog-to-digital conversion chips are respectively connected with the third clock signal, the fourth clock signal, the fifth clock signal and the sixth clock signal.
In order to realize the accurate control of the phase difference of the signals output by the first phase-locked loop and the second phase-locked loop at 90 °, in one possible implementation manner, the first phase-locked loop further comprises a first D flip-flop and a first internal oscillator; the second phase-locked loop also comprises a second D trigger and a second internal oscillator;
after the first internal oscillator generates a first candidate differential signal according to the first clock signal, transmitting the first candidate differential signal to the first D flip-flop to output the second differential signal;
and after the second internal oscillator generates a second candidate differential signal according to the second clock signal, transmitting the second candidate differential signal to the second D flip-flop through an NOT gate so as to output the third differential signal.
A phase detector, a filter, a frequency divider, etc. (not shown in the figure) are further present in the first phase-locked loop and the second phase-locked loop, so as to control the internal oscillator to generate a signal with a corresponding frequency according to an input frequency.
Fig. 4 shows a frequency output schematic diagram of a phase-locked loop according to an embodiment of the present application. As shown in fig. 4, a first internal oscillator (not shown in the figure) in the first phase-locked loop 401 may be connected to the first D flip-flop, and in this case, assuming that the first internal oscillator of the first phase-locked loop outputs a clock signal with a frequency of 2f, the first phase-locked loop divides the clock signal into f through the first D flip-flop; and the second internal oscillator (not shown) of the second phase locked loop 402 is connected to the second D flip-flop through the not gate, when the second internal oscillator of the second phase locked loop outputs the clock signal with the frequency of 2f, the signal generated by the second phase locked loop is inverted through the not gate to generate a phase difference of 180 °, and then is divided by the first D flip-flop, so that the phase difference of 180 ° is converted to 90 °.
In the embodiment of the present application, the phase difference between the signals received by the first phase-locked loop and the second phase-locked loop is 180 °, so after the signals are processed by the first phase-locked loop and the second phase-locked loop having the structure shown in fig. 3, the phase difference between the signals output by the first phase-locked loop and the second phase-locked loop should be 90 ° or 270 °, that is, the first phase-locked loop leads the second phase-locked loop by 90 ° or the first phase-locked loop lags the second phase-locked loop by 90 °, so that the phase difference between the first phase-locked loop and the second phase-locked loop is 90 °.
In another possible implementation manner, the first phase-locked loop includes a third internal oscillator, a third D flip-flop, and a fourth D flip-flop; the second phase-locked loop also comprises a fourth internal oscillator, a fifth D trigger and a sixth D trigger;
the third internal oscillator is connected with the third D trigger;
the third internal oscillator is connected with the fourth D trigger through a NOT gate;
the fourth internal oscillator is connected with the fifth D trigger;
the fourth internal oscillator is connected with the fifth D flip-flop through a NOT gate;
the first phase-locked loop and the second phase-locked loop also comprise chip registers; and the chip register is used for controlling the conduction state of each D trigger according to the data in the chip register.
Fig. 5 is a schematic diagram illustrating a frequency output of a phase-locked loop according to an embodiment of the present application. As shown in fig. 5, before the differential signals are generated by the first phase-locked loop and the second phase-locked loop, chip registers inside the first phase-locked loop and the second phase-locked loop may be configured, so as to control one of the first phase-locked loop and the second phase-locked loop to be directly frequency-divided by the D flip-flop, and the other of the first phase-locked loop and the second phase-locked loop to be frequency-divided by the D flip-flop after passing through the not gate, so that the output of the phase-locked loop 2 and the input of the phase-locked loop 1 generate a phase difference of 90 degrees.
In a possible implementation manner, the phase-locked loop clock unit is further configured to send the reference clock to the first phase-locked loop and the second phase-locked loop, respectively, so as to control the operating states of the first phase-locked loop and the second phase-locked loop.
The reference clock is also an important loop in the clock chain in order to guarantee synchronous operation of the ADC. The phase-locked loop clock unit generates two paths of sysref (reference clock) to two phase-locked loop 2 chips (namely a first phase-locked loop and a second phase-locked loop), and the phase-locked loop 2 chips can correspondingly generate phase synchronization signals to the ADC only when receiving the sysref reference clock sent by the phase-locked loop clock unit. Therefore, when the phase synchronization clock of the phase-locked loop 2 chip is transmitted to the ADC chip, the four ADCs start to sample alternately, and the synchronization of the four ADCs is ensured.
In this embodiment, the third clock signal, the fourth clock signal, the fifth clock signal, and the sixth clock signal are respectively connected to the four analog-to-digital conversion chips to control the interleaved sampling of the four analog-to-digital conversion chips.
In a possible implementation manner of the embodiment of the present application, as shown in fig. 3, each of the sample-and-hold chips (TH0 to TH3) is further included in the interleaved sampling apparatus; and each sampling and holding chip is respectively connected with the four analog-to-digital conversion chips so as to carry out sampling and holding processing on the acquired data and then send the data to the four analog-to-digital conversion chips.
In the data acquisition of the ADC, the sample-and-hold circuit is usually located at the frontmost end of the ADC, which is a very important loop in the system. The sample-and-hold circuit is used to sample and hold the input signal, and errors occur because any analog-to-digital converter requires a short period of time to perform the quantization and coding operations, while the analog value is still changing during this short period of time. The accuracy with which the sample and hold circuit takes the signal determines the maximum accuracy and the maximum resolution of the ADC. In a possible implementation manner of the embodiment of the application, in order to adapt to the precision and the sampling speed of the ADC, the selected sample-and-hold chip is manufactured by using a SiGe-BiCMOS process, has an analog signal bandwidth of 8GHz and a performance that the maximum sampling rate supports 4Gs/s sampling, and meets the requirement of the ADC on a 3Gs/s sampling rate.
And the third clock signal, the fourth clock signal, the fifth clock signal and the sixth clock signal are respectively connected to the sample-hold chips connected with the four analog-to-digital conversion chips so as to control the data processing of the sample-hold chips.
In a possible implementation manner, the interleaved sampling device further includes delay chips;
the third clock signal, the fourth clock signal, the fifth clock signal and the sixth clock signal are respectively transmitted to the four analog-to-digital conversion chips after being processed by the delay chips; and the third clock signal, the fourth clock signal, the fifth clock signal and the sixth clock signal are respectively transmitted to the sampling holding chips respectively connected with the four analog-to-digital conversion chips after being processed by the delay chips.
In a possible implementation manner, the interleaving and sampling device further comprises a sampling control chip; the sampling control chip is connected with the delay chip through a digital-to-analog conversion chip.
Ideally, time interleaving requires four ADCs to sample alternately and uniformly, with the same sampling clock interval between adjacent channels. In actual time interleaving, the frequency division of the sampling clock and the asymmetry of the driving circuit cause a deviation of the sampling time, which also affects the quantization result. In fact, the four ADCs do not completely sample alternately according to the phase difference of 90 °, and there is a sampling time mismatch, so that a function of adjusting the phases of the four ADCs is required. Please refer to fig. 6, which illustrates a schematic diagram of a variable delay bound structure according to an embodiment of the present application. As shown in fig. 6, the ADC is fine-tuned in phase by generating a delay through a digital-to-analog converter (DAC) and a delay chip connection. And sending a digital signal from the FPGA to the DAC chip to enable the DAC to generate adjustable voltage within a certain range. The broadband delay chip has a delay adjustment range of 0-70ps, the delay time can be changed according to the magnitude of the input voltage, and the delay control is linearly changed relative to the magnitude of the input voltage. And a clock signal generated by the clock buffer is input into the delay chip, voltage control is delayed, and then the clock signal enters the next clock buffer, and two clocks are distributed to the sample hold chip and the ADC respectively. Thus, the four ADCs have controllable delay functions.
In a possible implementation manner, the sampling control chip further includes an interleaving calibration module, and the interleaving calibration module is configured to calibrate the digital signals generated by the four analog-to-digital conversion chips, so as to obtain a target sampling result.
Namely, in the data acquisition stage, the embodiment of the application samples data by using a time interleaving technology. The principle of the time interleaving technology is that a plurality of sub-channels are alternately sampled on the premise that the conversion performance of a single channel is not changed.
The time interleaving method breaks through the limitations of chip circuit design and process conditions, and can greatly improve the sampling rate. However, time interleaving techniques naturally have some disadvantages, such as mismatch, gain mismatch, and sample time offset. These mismatches can severely affect the performance of the ADC board, and the expected performance of the ADC can only be obtained by calibrating the errors to a certain range.
In a possible implementation manner of the embodiment of the present application, calibration is performed in the FPGA through the calibration module after the ADC data is acquired. After data sampled from the ADC passes through the JESD204B interface, calibration is carried out through an interleaving calibration module, and the calibrated data are stored in the BRAM. The error can be eliminated to a certain extent after the calibration of the calibration module, and the performance of the ADC board card can be greatly improved.
In summary, when the four analog-to-digital conversion chips are required to perform interleaved sampling, after a phase-locked loop clock unit in the circuit generates a first differential signal, the first differential signal may be transmitted to a clock distributor, the clock distributor splits the first differential signal into a first clock signal and a second clock signal with a phase difference of 180 °, at this time, the first clock signal and the second clock signal are processed by the first phase-locked loop and the second phase-locked loop, respectively, to generate a second differential signal and a third differential signal with a phase difference of 90 °, at this time, the second clock distributor and the third clock distributor split the second differential signal and the third differential signal into clock signals with a phase difference of 180 °, at this time, the split third clock signal, the fourth clock signal, the fifth clock signal and the sixth clock signal have a phase difference of 90 °, so that the third clock signal, the fourth clock signal, the fifth clock signal, the sixth clock signal, and the clock signal are obtained by the third clock signal, The fourth clock signal, the fifth clock signal and the sixth clock signal can accurately control the interleaved sampling of the four analog-to-digital conversion chips, thereby avoiding the sampling time interval mismatch of the sampling of a plurality of ADC chips and improving the sampling precision of the four analog-to-digital conversion chips during the interleaved sampling.
In addition, the sampling hold circuit is used in the device related to the embodiment of the application, so that the sampling rate and the precision of the acquired data can be ensured, four clock links with 90-degree phase difference are generated, and four ADCs can be synchronously and sequentially sampled alternately. The four sub-channels are respectively provided with corresponding variable delay limit functions, so that the sampling time of the four ADCs can be finely adjusted to realize the final sampling time calibration function. The ADC board card also applies the time interleaving calibration technology inside the ADC chip to the board card, and the gain error calibration and the sampling interval mismatch calibration are realized among the four ADC chips. After calibration, the board card performance of the ADC can be greatly improved.
Other embodiments of the present application will be apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the invention following, in general, the principles of the application and including such departures from the present disclosure as come within known or customary practice within the art to which the invention pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the application being indicated by the following claims.
It will be understood that the present application is not limited to the precise arrangements described above and shown in the drawings and that various modifications and changes may be made without departing from the scope thereof. The scope of the application is limited only by the appended claims.
Claims (10)
1. A clock generation circuit is characterized by comprising a phase-locked loop clock unit, a first phase-locked loop, a second phase-locked loop, a first clock distributor, a second clock distributor and a third clock distributor;
the phase-locked loop clock unit is connected with the first clock distributor so as to convert the first differential signal generated by the phase-locked loop clock unit into a first clock signal and a second clock signal, and distribute the first clock signal and the second clock signal to the first phase-locked loop and the second phase-locked loop;
the first phase-locked loop converts the first clock signal into a second differential signal and transmits the second differential signal to a second clock distributor, so that the second clock distributor converts the second differential signal into a third clock signal and a fourth clock signal with a phase difference of 180 degrees;
the second phase-locked loop converts the second clock signal into a third differential signal and transmits the third differential signal to a third clock distributor, so that the third clock distributor converts the third differential signal into a fifth clock signal and a sixth clock signal with a phase difference of 180 degrees;
the second differential signal is 90 ° out of phase with the third differential signal;
the third clock signal, the fourth clock signal, the fifth clock signal and the sixth clock signal are respectively used for controlling the interleaved sampling of the four analog-to-digital conversion chips.
2. The clock generation circuit of claim 1, wherein the phase-locked loop clock unit is further configured to send the reference clock to a first phase-locked loop and a second phase-locked loop, respectively, to control the operating states of the first phase-locked loop and the second phase-locked loop.
3. The clock generation circuit of claim 2, wherein the phase-locked loop clock unit comprises a clock chip and a target phase-locked loop;
and the clock chip transmits the generated reference clock to a target phase-locked loop, and the target phase-locked loop generates the first differential signal according to the reference clock.
4. The clock generation circuit of claim 3, further comprising a first D flip-flop, a first internal oscillator; the second phase-locked loop also comprises a second D trigger and a second internal oscillator;
the first phase locked loop converts the first clock signal to a second differential signal, comprising:
after the first internal oscillator generates a first candidate differential signal according to the first clock signal, transmitting the first candidate differential signal to the first D flip-flop to output the second differential signal;
the second phase locked loop converts the second clock signal into a third differential signal, including:
and after the second internal oscillator generates a second candidate differential signal according to the second clock signal, transmitting the second candidate differential signal to the second D flip-flop through an NOT gate so as to output the third differential signal.
5. The clock generation circuit of claim 3, wherein the first phase locked loop comprises a third internal oscillator, a third D flip-flop, and a fourth D flip-flop; the second phase-locked loop also comprises a fourth internal oscillator, a fifth D trigger and a sixth D trigger;
the third internal oscillator is connected with the third D trigger;
the third internal oscillator is connected with the fourth D trigger through a NOT gate;
the fourth internal oscillator is connected with the fifth D trigger;
the fourth internal oscillator is connected with the fifth D flip-flop through a NOT gate;
the first phase-locked loop and the second phase-locked loop also comprise chip registers; and the chip register is used for controlling the conduction state of each D trigger according to the data in the chip register.
6. An interleaved sampling arrangement comprising the clock generation circuit of any of claims 1 to 5;
the interleaving sampling device also comprises the four analog-to-digital conversion chips; the four analog-to-digital conversion chips are respectively accessed to the third clock signal, the fourth clock signal, the fifth clock signal and the sixth clock signal;
the interleaving sampling device also comprises various sampling and holding chips; and each sampling and holding chip is respectively connected with the four analog-to-digital conversion chips so as to carry out sampling and holding processing on the acquired data and then send the data to the four analog-to-digital conversion chips.
7. The interleaved sampling device of claim 6, wherein the third clock signal, the fourth clock signal, the fifth clock signal and the sixth clock signal are respectively connected to a sample-and-hold chip to which four analog-to-digital conversion chips are connected, so as to control data processing of the sample-and-hold chip.
8. The interleaved sampling device of claim 7 further comprising a respective delay chip;
the third clock signal, the fourth clock signal, the fifth clock signal and the sixth clock signal are respectively transmitted to the four analog-to-digital conversion chips after being processed by the delay chips; and the third clock signal, the fourth clock signal, the fifth clock signal and the sixth clock signal are respectively transmitted to the four paths of sampling holding chips which are respectively connected with the analog-to-digital conversion chips after being processed by the time delay chips.
9. The interleaved sampling device of claim 8 further comprising a sampling control chip; the sampling control chip is connected with the delay chip through a digital-to-analog conversion chip.
10. The interleaved sampling device according to claim 9, wherein the sampling control chip further comprises an interleaved calibration module, and the interleaved calibration module is configured to calibrate the digital signals generated by the four analog-to-digital conversion chips, so as to obtain a target sampling result.
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| CN118018025A (en) * | 2024-04-08 | 2024-05-10 | 中国科学技术大学 | Multimode waveform digitizing circuit based on SCA chip and control method |
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| CN118018025A (en) * | 2024-04-08 | 2024-05-10 | 中国科学技术大学 | Multimode waveform digitizing circuit based on SCA chip and control method |
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