CN114512411B - Fan-out type packaging method - Google Patents
Fan-out type packaging method Download PDFInfo
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- CN114512411B CN114512411B CN202111671828.6A CN202111671828A CN114512411B CN 114512411 B CN114512411 B CN 114512411B CN 202111671828 A CN202111671828 A CN 202111671828A CN 114512411 B CN114512411 B CN 114512411B
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- 238000000034 method Methods 0.000 title claims abstract description 45
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 17
- 238000007789 sealing Methods 0.000 claims abstract description 34
- 230000004888 barrier function Effects 0.000 claims abstract description 30
- 230000000903 blocking effect Effects 0.000 claims abstract description 25
- 239000010410 layer Substances 0.000 claims description 222
- 239000012790 adhesive layer Substances 0.000 claims description 41
- 229920002120 photoresistant polymer Polymers 0.000 claims description 33
- 239000004020 conductor Substances 0.000 claims description 5
- 238000000227 grinding Methods 0.000 claims description 3
- 238000005530 etching Methods 0.000 claims description 2
- 239000000463 material Substances 0.000 abstract description 6
- 238000010586 diagram Methods 0.000 description 12
- 239000003292 glue Substances 0.000 description 10
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 5
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 5
- 229910052802 copper Inorganic materials 0.000 description 5
- 239000010949 copper Substances 0.000 description 5
- 239000005022 packaging material Substances 0.000 description 5
- 239000010936 titanium Substances 0.000 description 5
- 229910052719 titanium Inorganic materials 0.000 description 5
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 4
- 238000000465 moulding Methods 0.000 description 4
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 230000009286 beneficial effect Effects 0.000 description 3
- 229910052804 chromium Inorganic materials 0.000 description 3
- 239000011651 chromium Substances 0.000 description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 3
- 229910052737 gold Inorganic materials 0.000 description 3
- 239000010931 gold Substances 0.000 description 3
- 150000001875 compounds Chemical class 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000000670 limiting effect Effects 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- 229910052715 tantalum Inorganic materials 0.000 description 2
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 1
- 239000002390 adhesive tape Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 150000002894 organic compounds Chemical class 0.000 description 1
- 230000002633 protecting effect Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
The application discloses a fan-out type packaging method, which comprises the following steps: a dielectric layer is arranged on the first carrier plate, and a groove is arranged on one side, away from the first carrier plate, of the dielectric layer; forming a plurality of first through holes on the dielectric layer positioned on the side wall of the groove, and simultaneously forming a plurality of second through holes on the dielectric layer positioned at the bottom of the groove; forming a conductive post within the first via and a barrier within the second via; removing the dielectric layer and arranging a first chip in a range surrounded by a plurality of blocking pieces; forming a plastic sealing layer on one side of the first carrier plate, on which the first chip is arranged; and removing the first carrier plate. By the mode, the method and the device can reduce the warping probability of the first chip, reduce the height of the fan-out type packaging device and effectively save the material cost.
Description
Technical Field
The application relates to the technical field of chip packaging, in particular to a fan-out type packaging method.
Background
In the existing chip packaging method, the chip is packaged into a complete chip packaging structure through the plastic packaging material, but the plastic packaging material is easy to deform due to shrinkage in the subsequent use process, so that the chip is deviated in the packaging structure, and the service life of the chip is shortened.
Disclosure of Invention
The application mainly solves the technical problem of providing a fan-out type packaging method which can reduce the deformation amount of plastic packaging materials caused by shrinkage and ensure the stability of chips.
In order to solve the technical problems, the application adopts a technical scheme that: there is provided a fan-out method comprising: a dielectric layer is arranged on the first carrier plate, and a groove is arranged on one side, away from the first carrier plate, of the dielectric layer; forming a plurality of first through holes on the dielectric layer positioned on the side wall of the groove, and simultaneously forming a plurality of second through holes on the dielectric layer positioned at the bottom of the groove; the first through holes are arranged around the periphery of the second through holes, and the height of the first through holes is larger than that of the second through holes; forming a conductive post within the first via and a barrier within the second via; removing the dielectric layer, and arranging a first chip in a range surrounded by a plurality of blocking pieces; forming a plastic sealing layer on one side of the first carrier plate, where the first chip is arranged, so that the first chip, the blocking piece and the conductive column form an integral structure; and removing the first carrier plate.
Wherein the barrier has conductive properties, the steps of forming a conductive pillar in the first via and forming a barrier in the second via include: and filling conductive materials in the first via hole and the second via hole simultaneously to form the conductive column and the barrier.
The method for manufacturing the semiconductor device comprises the steps of arranging a dielectric layer on a first carrier plate, arranging a groove on one side of the dielectric layer away from the first carrier plate, and the steps of: providing a second carrier plate provided with an adhesive layer; a stop block is arranged on the adhesive layer, and the orthographic projection of the stop block on the adhesive layer is positioned in the adhesive layer; forming a dielectric layer on one side of the second carrier plate, on which the adhesive layer is arranged, wherein the dielectric layer at least covers the side surface of the stop block exposed from the adhesive layer; removing the stop block, the adhesive layer and the second carrier plate, and arranging the dielectric layer to face the first carrier plate away from the surface of one side of the second carrier plate; the dielectric layer is arranged at a position corresponding to the stop block to form the groove.
The cross section of the stop block exposed from the adhesive layer is the same in the direction away from the second carrier plate; when a dielectric layer is formed on one side of the second carrier plate, which is provided with the adhesive layer, the dielectric layer covers the side surface of the stop block exposed from the adhesive layer and one side of the stop block, which is away from the second carrier plate; the dielectric layer on one side of the stop block, which is away from the second carrier plate, forms the bottom of the groove, and the dielectric layers on the other positions form the side walls of the groove.
Wherein the stop block exposed from the adhesive layer comprises a main body part and a convex part which are arranged in a stacked manner; the main body part is close to the second carrier relative to the convex part, the orthographic projection of the convex part on the main body part is positioned in the main body part, and a step part is formed on the side surface of the stop block exposed from the adhesive layer; when the second carrier plate is provided with the adhesive layer, a dielectric layer is formed on one side of the adhesive layer, the dielectric layer covers the main body part and the side surface of the convex part, and one side of the convex part, which is away from the second carrier plate, is exposed from the dielectric layer; wherein, a third via hole is formed at the position of the dielectric layer corresponding to the convex part, the dielectric layer located at the step portion forms the bottom of the groove, and the dielectric layer located at the rest positions forms the side walls of the groove.
Wherein the step of forming a plurality of first vias on the dielectric layer located on the sidewall of the recess and simultaneously forming a plurality of second vias on the dielectric layer located at the bottom of the recess includes: forming a photoresist layer on one side of the dielectric layer, which is away from the first carrier plate; exposing and developing at least part of the photoresist layer to form a plurality of first through holes and a plurality of second through holes on the photoresist layer; the orthographic projection of the first through hole on the dielectric layer is positioned on the side wall of the groove, and the orthographic projection of the second through hole on the dielectric layer is positioned at the bottom of the groove; etching to remove the dielectric layer at the first through hole and the second through hole to form the first through hole and the second through hole; removing all photoresist layers except the area surrounded by the plurality of second through holes; the removing the dielectric layer before or after further comprises: and removing the residual photoresist layer.
Before the step of forming the plastic sealing layer on the side, provided with the first chip, of the first carrier plate, insulating glue is formed at least on the periphery of the plurality of blocking pieces.
The first chip comprises a first functional surface and a first nonfunctional surface which are arranged in opposite directions, and the first functional surface of the first chip faces the first carrier plate; the step of forming a plastic sealing layer on one side of the first carrier plate, where the first chip is arranged, includes: forming a plastic sealing layer on one side of the first carrier plate, where the first chip is arranged, wherein the plastic sealing layer covers the conductive column and a gap in a space surrounded by the conductive column; the plastic sealing layer is flush with the surface of one side of the conductive column, which faces away from the carrier plate.
The first chip comprises a first functional surface and a first nonfunctional surface which are arranged in opposite directions, and the first nonfunctional surface of the first chip faces the first carrier plate; before the step of forming the plastic sealing layer on the side, where the first chip is arranged, of the first carrier plate, the method further comprises: at least one second chip is arranged on one side, away from the first carrier plate, of the first functional surface of the first chip, underfill is formed at least between the second functional surface of the second chip and the carrier plate, and the blocking piece is positioned in the underfill; wherein a second functional surface of the second chip faces a first functional surface of the first chip, the second chip spans at least part of the first chip and at least part of the barrier adjacent to at least part of the first chip, and a second bonding pad on the second functional surface of the second chip is electrically connected with a first bonding pad on the first functional surface of the first chip and the barrier at a corresponding position; the step of forming a plastic sealing layer on one side of the first carrier plate, where the first chip is arranged, includes: forming a plastic sealing layer on one side of the first carrier plate, where the first chip is arranged, and the plastic sealing layer covers the conductive column, the second chip and a gap in a space surrounded by the conductive column; and grinding the plastic sealing layer from one side of the plastic sealing layer, which is away from the first carrier plate, so that the plastic sealing layer, the conductive piece and the second chip are flush with one side surface of the plastic sealing layer, which is away from the first carrier plate.
Wherein, after removing the first carrier plate, the method further comprises: forming a first rewiring layer and a second rewiring layer on two sides of the conductive column in the length direction respectively; wherein the first rewiring layer is electrically connected with at least the conductive pillars and the first chip, and the second rewiring layer is electrically connected with the conductive pillars; a first electrical connector is disposed on a side of the first rewiring layer facing away from the conductive post, and a second electrical connector is disposed on a side of the second rewiring layer facing away from the conductive post.
The beneficial effects of the application are as follows: different from the prior art, the application is characterized in that a dielectric layer with grooves is arranged on a carrier plate, and a plurality of blocking pieces and a plurality of conductive columns are formed by utilizing the dielectric layer; the plurality of blocking pieces and the plurality of conductive columns are equivalent to cofferdam retaining walls, and can limit the movement of plastic packaging materials in the plastic packaging layers so as to reduce the deformation amount of the plastic packaging materials caused by shrinkage and reduce the warping probability of the first chip; in addition, the conductive column can also realize a three-dimensional vertical interconnection structure, which is beneficial to reducing the height of the fan-out type device; in addition, the design of the blocking piece and the conductive column with different heights can also effectively save the material cost.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art. Wherein:
FIG. 1 is a flow chart of a fan-out package method according to an embodiment of the present application;
FIG. 2 is a schematic cross-sectional view of an embodiment corresponding to step S101;
Fig. 3 is a schematic cross-sectional structure of another embodiment corresponding to step S101;
Fig. 4 is a flow chart corresponding to the step S102;
FIG. 5 is a schematic cross-sectional view of an embodiment corresponding to step S201;
FIG. 6 is a schematic cross-sectional view of an embodiment corresponding to step S202;
fig. 7 is a flowchart corresponding to the step S102 in yet another embodiment;
FIG. 8 is a schematic cross-sectional view of an embodiment corresponding to step S301;
FIG. 9 is a schematic cross-sectional view of an embodiment corresponding to step S302;
Fig. 10 is a flow chart corresponding to the step S103;
FIG. 11 is a schematic cross-sectional view of an embodiment corresponding to step S401;
FIG. 12 is a schematic cross-sectional view of an embodiment corresponding to step S402;
fig. 13 is a schematic cross-sectional structure diagram of step S403 corresponding to an embodiment;
fig. 14 is a schematic cross-sectional structure diagram corresponding to an embodiment after step S403;
FIG. 15 is a schematic cross-sectional view of step S104 according to an embodiment;
Fig. 16 is a schematic cross-sectional structure diagram of step S105 according to an embodiment;
FIG. 17 is a schematic cross-sectional view of a fan-out package method according to yet another embodiment of the present application;
Fig. 18 is a schematic cross-sectional view of a fan-out package according to another embodiment of the present application.
Detailed Description
The following description of the embodiments of the present application will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present application, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
Referring to fig. 1, fig. 1 is a flow chart of a fan-out package method according to an embodiment of the application, and the method includes:
S101: a dielectric layer is arranged on the first carrier plate, and a groove is formed in one side, away from the first carrier plate, of the dielectric layer.
Referring to fig. 2, a schematic cross-sectional structure of step S101 in fig. 2 corresponds to an embodiment, and the implementation process of step S101 includes: referring to fig. 2a, a second carrier 50 with an adhesive layer 60 is provided. The material of the second carrier 50 may be one of silicon, glass, metal, organic compound, and the like. A stop 10 is then provided on the glue layer 60, and the orthographic projection of the stop 10 on the glue layer 60 is located in the glue layer 60. The stop block 10 has a cylindrical structure, that is, the cross section of the stop block 10 exposed from the adhesive layer 60 in the direction away from the second carrier 50 is rectangular, and the stop block 10 may be made of copper, aluminum, gold, chromium, titanium, etc. and has the same size. A dielectric layer 70 is formed on the second carrier 50 at a side where the adhesive layer 60 is disposed, and the dielectric layer 70 covers at least a side surface of the stopper 10 exposed from the adhesive layer 60. Specifically, when the dielectric layer 70 is formed on the side of the second carrier 50 where the adhesive layer 60 is disposed, the dielectric layer 70 covers the side of the stopper 10 exposed from the adhesive layer 60 and the side of the stopper 10 facing away from the second carrier 50. Wherein the dielectric layer 70 on the side of the stopper 10 facing away from the second carrier 50 forms the bottom of the recess, and the dielectric layers on the rest positions form the sidewalls of the recess. Step S102 is facilitated by forming a fluted dielectric layer.
Further, referring to fig. 2b, after forming the dielectric layer 70, the method further includes: removing the stop block 10, the adhesive layer 60 and the second carrier 50, and arranging the dielectric layer 70 facing the first carrier 80 away from the surface of one side of the second carrier 50; wherein, the dielectric layer 70 forms a groove corresponding to the position of the stop block 10. Step S102 is facilitated by forming a fluted dielectric layer. Alternatively, after forming the dielectric layer 70, the first carrier plate 80 may be disposed on a side of the dielectric layer 70 facing away from the second carrier plate 50, and then the stopper 10, the adhesive layer 60, and the second carrier plate 50 may be removed. Alternatively, the stop 10, the adhesive layer 60 and the second carrier 50 may be removed first, and then the first carrier 80 is disposed on one side of the dielectric layer 70.
In another application, the stopper 10 may also be a boss structure, referring to fig. 3, fig. 3 is a schematic cross-sectional view of step S101 corresponding to another embodiment. In this embodiment, referring to fig. 3a, the stopper 10 exposed from the adhesive layer 60 includes a main body 12 and a protrusion 11 stacked; the main body is close to the second carrier 50 with respect to the protruding portion, and the orthographic projection of the protruding portion on the main body is located in the main body, and a step is formed on the side surface of the stopper 10 exposed from the adhesive layer 60. When the dielectric layer 70 is formed on the second carrier 50 on the side where the adhesive layer 60 is disposed, the dielectric layer 70 covers the main body and the side surfaces of the protruding portions, and the protruding portions are exposed from the dielectric layer 70 on the side facing away from the second carrier 50. Wherein, the dielectric layer 70 forms a third via hole corresponding to the position of the convex part, the dielectric layer at the step part forms the bottom of the groove, and the dielectric layers at the rest positions form the side walls of the groove.
Further, referring to fig. 3b, after forming the dielectric layer 70, the method further includes: removing the stop block 10, the adhesive layer 60 and the second carrier 50, and arranging the dielectric layer 70 facing the first carrier 80 away from the surface of one side of the second carrier 50; wherein, the dielectric layer 70 forms a groove corresponding to the position of the stop block 10.
S102: a plurality of conductive pillars is formed and a plurality of barriers is formed.
In response to the block 10 having the cylindrical structure in the step S101, referring to fig. 4, fig. 4 is a flow chart corresponding to an embodiment of the step S102, and specifically, the implementation process of the step S102 includes:
S201: a plurality of first through holes are formed on the dielectric layer positioned on the side wall of the groove, and a plurality of second through holes are formed on the dielectric layer positioned at the bottom of the groove.
Referring to fig. 5, fig. 5 is a schematic cross-sectional structure diagram of an embodiment corresponding to step S201, specifically referring to fig. 5a, before implementation of step S201, the method includes: forming a photoresist layer 90 on a side of the dielectric layer 70 facing away from the first carrier 80; exposing and developing at least part of the photoresist layer 90 to form a plurality of first through holes 901 and a plurality of second through holes 903 on the photoresist layer 90; wherein, the orthographic projection of the first through hole 901 on the dielectric layer 70 is located at the sidewall of the groove, and the orthographic projection of the second through hole 903 on the dielectric layer 70 is located at the bottom of the groove. Specifically, before exposing and developing a portion of the photoresist layer 90, a film 100 is disposed on a side of the photoresist layer 90 away from the first carrier 80, and a plurality of openings 101 are disposed on the film 100; the photoresist layer 90 at the position corresponding to the plurality of openings 101 can be removed by exposing and developing the side of the film 100 away from the first carrier 80, so as to form a plurality of first through holes 901 and a plurality of second through holes 903, and the photoresist layer 90 at the position corresponding to the position outside the openings 101 on the film 100 cannot be exposed and developed due to the shielding of the film 100, so that the photoresist layer 90 at the position outside the openings 101 plays a certain role in protection. Forming the plurality of first vias 901 and the plurality of second vias 903 on the photoresist layer 90 facilitates forming the first vias 701 and the second vias 703 at corresponding locations of the dielectric layer 70.
Further, referring to fig. 5b, the dielectric layer 70 at the locations of the first via 901 and the second via 903 is etched away to form a first via 701 and a second via 703.
Further, referring to fig. 5c, all the photoresist layers 90 outside the area surrounded by the second vias 703 are removed to help to execute step S202, and the photoresist layers 90 in the area surrounded by the second vias 703 can shield and protect the dielectric layer 70 at the corresponding positions.
S202: a conductive post is formed in the first via and a barrier is formed in the second via.
Referring to fig. 6, fig. 6 is a schematic cross-sectional structure diagram of an embodiment of step S202, where the implementation process of step S202 includes: the first via 701 and the second via 703 are filled with a conductive material simultaneously to form the conductive post 30 and the barrier 20. The three-dimensional vertical interconnection structure of the fan-out device is facilitated through the conductive pillars 30, and the barrier 20 helps to improve stability of the fan-out device. The conductive material may be one or more of titanium, tantalum, chromium, tungsten, copper, aluminum, nickel, gold, etc., preferably titanium or copper.
In response to the block 10 being in the bump structure in the step S101, referring to fig. 7, fig. 7 is a schematic flow chart of a further embodiment of the step S102, and specifically, the implementation process of the step S102 includes:
s301: a plurality of first vias and a plurality of second vias are formed on the dielectric layer.
Referring to fig. 8, fig. 8 is a schematic cross-sectional structure diagram of an embodiment of step S301, referring to fig. a of fig. 8, before implementing step S301, the method includes: forming a photoresist layer 90 on a side of the dielectric layer 70 facing away from the first carrier 80; exposing and developing at least part of the photoresist layer 90 to form a plurality of first through holes 901 and a plurality of second through holes 903 on the photoresist layer 90; the step portion of the dielectric layer 70 is taken as the bottom of the groove, and the rest portion of the dielectric layer 70 is taken as the side wall of the groove, wherein the orthographic projection of the first through hole 901 on the dielectric layer 70 is positioned on the side wall of the groove, and the orthographic projection of the second through hole 903 on the dielectric layer 70 is positioned on the bottom of the groove. Specifically, before exposing and developing a portion of the photoresist layer 90, a film 100 is disposed on a side of the photoresist layer 90 away from the first carrier 80, and a plurality of openings 101 are disposed on the film 100; the photoresist layer 90 at the position corresponding to the plurality of openings 101 can be removed by exposing and developing the side of the film 100 away from the first carrier 80, so as to form a plurality of first through holes 901 and a plurality of second through holes 903, and the photoresist layer 90 at the position corresponding to the position outside the openings 101 on the film 100 cannot be exposed and developed due to the blocking of the film 100.
Further, referring to fig. 8 b, the dielectric layer 70 at the locations of the first via 901 and the second via 903 is etched away to form a first via 701 and a second via 703.
Further, referring to fig. 8 c, all the photoresist layers 90 except the area surrounded by the second vias 703 are removed to execute step S302, and the remaining photoresist layers can protect the area surrounded by the second vias 703.
S302: a conductive post is formed in the first via and a barrier is formed in the second via.
Referring to fig. 9, fig. 9 is a schematic cross-sectional structure diagram of the step S302 corresponding to an embodiment, where the implementation process of the step S302 includes: the first via 701 and the second via 703 are filled with a conductive material simultaneously to form the conductive post 30 and the barrier 20. Wherein the conductive metal can be one or more of titanium, tantalum, chromium, tungsten, copper, aluminum, nickel and gold, and is preferably titanium or copper.
S103: and removing the dielectric layer and arranging the first chip in the range surrounded by the plurality of blocking pieces.
Referring to fig. 10, fig. 10 is a flow chart corresponding to an embodiment of step S103, where the implementation process of step S103 includes:
S401: the dielectric layer is removed.
Referring to fig. 11, fig. 11 is a schematic cross-sectional structure diagram of the step S401 corresponding to an embodiment. Specifically, the step S401 includes exposing the conductive pillars 30 and the barriers 20 by removing the dielectric layer 70. This step S103 further includes removing the remaining photoresist layer 90 to facilitate the execution of step S403. Alternatively, the remaining photoresist layer 90 may be removed before the dielectric layer 70 is removed, or the remaining photoresist layer 90 may be removed after the dielectric layer 70 is removed.
S402: an insulating paste is formed at least at the periphery of the plurality of stoppers.
Referring to fig. 12, fig. 12 is a schematic cross-sectional structure of an embodiment corresponding to step S402, in which step S402 forms an insulating glue 40 at least on the periphery of the plurality of blocking members 20 by way of glue dripping, and the surface of the insulating glue 40 is arc-shaped based on the tension of the glue surface. Forming the insulating glue 40 on the periphery of the plurality of barriers 20 may provide a certain limiting and protecting effect to the barriers 20. Alternatively, the insulating paste 40 may be formed on the periphery of the plurality of blocking members 20 by dispensing, and the insulating paste 40 may be cylindrical, tapered, etc., which is not limited herein.
S403: the first chip is arranged in a range surrounded by the plurality of blocking pieces.
In response to the first chip 300 including the first functional surface 3001 and the first nonfunctional surface 3002 disposed opposite to each other, when the first nonfunctional surface 3002 of the first chip 300 faces the first carrier 80, refer to fig. 13, and fig. 13 is a schematic cross-sectional structure corresponding to an embodiment in the step S403. Specifically, the first chip 300 is disposed within a range enclosed by the plurality of blocking members 20, and the first nonfunctional surface 3002 of the first chip 300 is attached to the side of the first carrier 80 where the blocking members 20 are disposed. A plurality of first pads 3003 (only two are shown in the figure) are disposed on the first functional surface 3001 of the first chip 300 to receive and/or transmit signals.
Optionally, the first nonfunctional surface 3002 of the first chip 300 may be fixed with the first carrier 80 by bonding glue; it is also possible to attach double-sided tape to the first carrier plate 80. The first chip 300 is adhered to the double-sided adhesive tape. The first chip 300 is disposed on the first carrier 80, which can play a certain limiting role on the first chip 300.
Further, disposing the first chip 300 within the range enclosed by the plurality of blocking members 20 further includes disposing at least one second chip 500 on a side of the first functional surface 3001 of the first chip 300 facing away from the first carrier 80. Specifically, referring to fig. 14, fig. 14 is a schematic cross-sectional structure of an embodiment after step S403, fig. 14 is only schematic, and for convenience of understanding, fig. 14 only shows two second chips 500, and in practical application, one or more second chips 500 may be disposed on the first functional surface 3001 side of the first chip 300. The second chip 500 includes a second functional surface 5001 and a second non-functional surface 5002 disposed opposite to each other, and a plurality of second pads 5003 (only two are shown in the drawing) are disposed on the second functional surface 5001 to receive and/or transmit signals. Wherein the second functional surface 5001 of the second chip 500 faces the first functional surface 3001 of the first chip 300 and the second chip 500 spans at least a portion of the first chip 300 and at least a portion of the barrier 20 at least partially adjacent to the first chip 300. In this application, in response to the end of the blocking member 20 facing away from the first carrier 80 being flush with the first functional surface 3001 of the first chip 300, the second pad 5003 on the second functional surface 5001 of the second chip 500 is electrically connected to the first pad 3003 on the first functional surface 3001 of the first chip 300 at the corresponding position and the blocking member 20, i.e. the blocking member 20 may be electrically connected to the first chip 300 through the second chip 500. By providing at least one second chip 500 on the first functional surface 3001 side of the first chip 300, packaging of a plurality of chips can be achieved and the reduction in the height of the fan-out device is facilitated. In another application mode, if one end of the blocking member 20 facing away from the first carrier plate 80 is not flush with the first functional surface 3001 of the first chip 300, the conductive bump may be set to ensure that the blocking member 20 is flush with the first functional surface 3001 of the first chip 300, and the second chip 500 is set to ensure that the second chip 500 does not incline, thereby ensuring the stability of the chip.
Further, with continued reference to fig. 14, after the second chip 500 is disposed, the method further includes: at least an underfill 45 is formed between the second functional surface 5001 of the second chip 500 and the carrier 80, and the barrier 20 is located in the underfill 45 to fix and protect the first chip 300, the second chip 500, and the barrier 20. Specifically, in the application mode, the vertical section of the underfill 45 is trapezoid, so that the stability of the fan-out type device can be improved; in other applications, the underfill 45 may have a rectangular vertical cross section. Alternatively, the side of the underfill 45 facing away from the carrier 80 may be flush with the second functional surface 5001 of the second chip 500, or may be higher than the second functional surface 5001 of the second chip 500, which is not limited in the present application. In addition, in other embodiments, the underfill 45 may not be disposed, that is, the step S104 may be directly performed after the second chip 500 is disposed.
S104: and forming a plastic sealing layer on one side of the first carrier plate, on which the first chip is arranged.
Referring to fig. 15, fig. 15 is a schematic cross-sectional structure diagram of the step S104 corresponding to an embodiment, and the implementation process of the step S104 includes: a plastic layer 110 is formed on the first carrier 80 at the side where the first chip 300 is disposed, and the plastic layer 110 covers the conductive pillars 30 and the gaps in the space enclosed by the conductive pillars 30. Further, the plastic sealing layer 110 is ground from the side of the plastic sealing layer 110 facing away from the first carrier 80, so that the plastic sealing layer 110, the conductive pillars 30 and the second chip 500 are flush with the surface facing away from the first carrier 80. The conductive pillars 30, and the devices within the conductive pillars 30, can be secured and protected by forming the molding layer 110. Specifically, the material of the plastic layer 110 may be epoxy, which may be formed by a lamination process. The overall thickness of the packaged device is reduced by grinding the plastic layer 110, and the heat dissipation effect is improved.
S105: and removing the first carrier plate.
Referring to fig. 16, fig. 16 is a schematic cross-sectional structure diagram of the step S105 corresponding to an embodiment. In an application mode, the specific implementation process of the step S105 includes: the first carrier plate 80 is removed. Further, the first rewiring layer 120 and the second rewiring layer 130 are formed on both sides in the length direction of the conductive pillars 30, respectively. Wherein the first rewiring layer 120 is electrically connected to at least the conductive pillars 30 and the first chip 300, and the second rewiring layer 130 is electrically connected to the conductive pillars 30. Specifically, the first rewiring layer 120 is located on the first nonfunctional surface 3002 side of the first chip 300, and the second rewiring layer 130 is located on the second nonfunctional surface 5002 side of the second chip 500; based on the barrier 20 being electrically connected to the first chip 300 through the second chip 500, the first rewiring layer 120 may be electrically connected to at least the conductive pillars 30 and the first chip 300.
Further, a first electrical connector 150 is disposed on a side of the first rewiring layer 120 facing away from the conductive post 30, and a second electrical connector 160 is disposed on a side of the second rewiring layer 130 facing away from the conductive post 30, so as to facilitate subsequent connection to a substrate or other integrated chip. Optionally, a plurality of solder balls 170 may be disposed between the first rewiring layer 120 and the first electrical connector 150, and between the second rewiring layer 130 and the second electrical connector 160 to facilitate connection between the first rewiring layer 120 and the first electrical connector 150, and between the second rewiring layer 130 and the second electrical connector 160.
The application is characterized in that a dielectric layer 70 with grooves is arranged on a first carrier plate 80, and a plurality of barriers 20 and a plurality of conductive posts 30 are formed by utilizing the dielectric layer 70; the plurality of blocking members 20 and the plurality of conductive columns 30 are equivalent to cofferdam retaining walls, which can limit the movement of the molding compound in the molding layer 110, so as to reduce the deformation amount of the molding compound caused by shrinkage and reduce the warpage probability of the first chip 300; in addition, the conductive posts 30 can also realize a three-dimensional vertical interconnection structure, which is beneficial to reducing the height of the fan-out type device; in addition, the different height of the barrier 20 and conductive post 30 designs can also be effective in saving material costs.
Of course, in other embodiments, before step S104, the first functional surface 3001 of the first chip 300 faces the first carrier 80; referring to fig. 17, fig. 17 is a schematic cross-sectional structure diagram of a fan-out package method according to another embodiment of the application, in which, in response to the first chip 300 including the first functional surface 3001 and the first non-functional surface 3002 disposed opposite to each other, in this embodiment, the first functional surface 3001 of the first chip 300 is oriented towards the first carrier 80 to protect the first functional surface 3001 of the first chip 300 to a certain extent, and a plastic layer 110 is formed on a side of the first carrier 80 where the first chip 300 is disposed, where the plastic layer 110 covers the conductive pillars 30 and gaps in the space enclosed by the conductive pillars 30; wherein, the plastic layer 110 is flush with the surface of the side of the conductive post 30 facing away from the first carrier 80. In another application, in response to the side of the plastic layer 110 facing away from the first carrier plate 80 being higher than the side of the conductive pillars 30 facing away from the first carrier plate 80, the plastic layer 110 may be ground such that the plastic layer 110 is flush with the surface of the side of the conductive pillars 30 facing away from the first carrier plate 80. By providing the plastic layer 110, a certain protection effect can be achieved on the conductive post 30 and the devices within the range enclosed by the conductive post 30.
Further, referring to fig. 18, fig. 18 is a schematic cross-sectional structure diagram of a fan-out package method according to another embodiment of the present application, after forming the plastic layer 110, the method includes: the first carrier 80 is removed, and a first rewiring layer 120 and a second rewiring layer 130 are formed on both sides of the conductive pillar 30 in the length direction, respectively. The first rewiring layer 120 is located on the first functional surface 3001 side of the first chip 300, and the second rewiring layer 130 is located on the first functional surface 3001 side of the plastic sealing layer 110 facing away from the first chip 300. The first electrical connector 150 is then disposed on the side of the first rewiring layer 120 facing away from the conductive stud, and the second electrical connector 160 is disposed on the side of the second rewiring layer 130 facing away from the conductive stud 30. Alternatively, a plurality of solder balls 170 may be formed between the first rewiring layer 120 and the first electrical connector 150, and between the second rewiring layer 130 and the second electrical connector 160.
In the above embodiment, the first functional surface 3001 of the first chip 300 is oriented to the first carrier 80, and then the fan-out packaging method provided by the application packages the first chip, so that the probability of warping of the first chip 300 can be reduced, the conductive columns 30 can also realize a three-dimensional vertical interconnection structure, and the height of the fan-out device can be reduced; in addition, the different height of the barrier 20 and conductive post 30 designs can also be effective in saving material costs.
The foregoing description is only of embodiments of the present application, and is not intended to limit the scope of the application, and all equivalent structures or equivalent processes using the descriptions and the drawings of the present application or directly or indirectly applied to other related technical fields are included in the scope of the present application.
Claims (8)
1. A fan-out package method, comprising:
a dielectric layer is arranged on the first carrier plate, and a groove is arranged on one side, away from the first carrier plate, of the dielectric layer;
forming a plurality of first through holes on the dielectric layer positioned on the side wall of the groove, and simultaneously forming a plurality of second through holes on the dielectric layer positioned at the bottom of the groove; the first through holes are arranged around the periphery of the second through holes, and the height of the first through holes is larger than that of the second through holes;
forming a conductive post within the first via and a barrier within the second via;
Removing the dielectric layer, and arranging a first chip in a range surrounded by a plurality of blocking pieces;
forming a plastic sealing layer on one side of the first carrier plate, where the first chip is arranged, so that the first chip, the blocking piece and the conductive column form an integral structure;
Removing the first carrier plate;
before the step of forming the plastic sealing layer on the side, where the first carrier plate is provided with the first chip, the method comprises the following steps: forming an insulating paste at least on the periphery of the plurality of the barriers;
the first chip comprises a first functional surface and a first nonfunctional surface which are arranged in opposite directions, and the first nonfunctional surface of the first chip faces the first carrier plate;
Before the step of forming the plastic sealing layer on the side, where the first chip is arranged, of the first carrier plate, the method further comprises: at least one second chip is arranged on one side, away from the first carrier plate, of the first functional surface of the first chip, underfill is formed at least between the second functional surface of the second chip and the carrier plate, and the blocking piece is positioned in the underfill; wherein a second functional surface of the second chip faces a first functional surface of the first chip, the second chip spans at least part of the first chip and at least part of the barrier adjacent to at least part of the first chip, and a second bonding pad on the second functional surface of the second chip is electrically connected with a first bonding pad on the first functional surface of the first chip and the barrier at a corresponding position;
The step of forming a plastic sealing layer on one side of the first carrier plate, where the first chip is arranged, includes: forming a plastic sealing layer on one side of the first carrier plate, where the first chip is arranged, and the plastic sealing layer covers the conductive column, the second chip and a gap in a space surrounded by the conductive column; and grinding the plastic sealing layer from one side of the plastic sealing layer, which is away from the first carrier plate, so that the plastic sealing layer, the conductive column and the second chip are flush with one side surface of the plastic sealing layer, which is away from the first carrier plate.
2. The fan-out package method of claim 1, wherein the barrier has conductive properties, the steps of forming conductive pillars within the first vias, and forming barriers within the second vias, comprising:
and filling conductive materials in the first via hole and the second via hole simultaneously to form the conductive column and the barrier.
3. The fan-out packaging method according to claim 1, wherein the step of providing a dielectric layer on the first carrier, and providing a recess on a side of the dielectric layer facing away from the first carrier, includes:
Providing a second carrier plate provided with an adhesive layer;
A stop block is arranged on the adhesive layer, and the orthographic projection of the stop block on the adhesive layer is positioned in the adhesive layer;
forming a dielectric layer on one side of the second carrier plate, on which the adhesive layer is arranged, wherein the dielectric layer at least covers the side surface of the stop block exposed from the adhesive layer;
Removing the stop block, the adhesive layer and the second carrier plate, and arranging the dielectric layer to face the first carrier plate away from the surface of one side of the second carrier plate; the dielectric layer is arranged at a position corresponding to the stop block to form the groove.
4. The fan-out package method of claim 3, wherein,
The cross section of the stop block exposed from the adhesive layer is the same in size in the direction away from the second carrier plate; when a dielectric layer is formed on one side of the second carrier plate, which is provided with the adhesive layer, the dielectric layer covers the side surface of the stop block exposed from the adhesive layer and one side of the stop block, which is away from the second carrier plate;
The dielectric layer on one side of the stop block, which is away from the second carrier plate, forms the bottom of the groove, and the dielectric layers on the other positions form the side walls of the groove.
5. The fan-out package method of claim 3, wherein,
The stop block exposed from the adhesive layer comprises a main body part and a convex part which are arranged in a stacked manner; the main body part is close to the second carrier plate relative to the convex part, the orthographic projection of the convex part on the main body part is positioned in the main body part, and a step part is formed on the side surface of the stop block exposed from the adhesive layer;
When the second carrier plate is provided with the adhesive layer, a dielectric layer is formed on one side of the adhesive layer, the dielectric layer covers the main body part and the side surface of the convex part, and one side of the convex part, which is away from the second carrier plate, is exposed from the dielectric layer;
wherein, a third via hole is formed at the position of the dielectric layer corresponding to the convex part, the dielectric layer located at the step portion forms the bottom of the groove, and the dielectric layer located at the rest positions forms the side walls of the groove.
6. The fan-out type packaging method according to claim 4 or 5, wherein,
The step of forming a plurality of first vias on the dielectric layer located on the sidewall of the recess and simultaneously forming a plurality of second vias on the dielectric layer located at the bottom of the recess includes: forming a photoresist layer on one side of the dielectric layer, which is away from the first carrier plate; exposing and developing at least part of the photoresist layer to form a plurality of first through holes and a plurality of second through holes on the photoresist layer; the orthographic projection of the first through hole on the dielectric layer is positioned on the side wall of the groove, and the orthographic projection of the second through hole on the dielectric layer is positioned at the bottom of the groove; etching to remove the dielectric layer at the first through hole and the second through hole to form the first through hole and the second through hole; removing all photoresist layers except the area surrounded by the plurality of second through holes;
The removing the dielectric layer before or after further comprises: and removing the residual photoresist layer.
7. The fan-out packaging method of claim 1, wherein,
The first chip comprises a first functional surface and a first nonfunctional surface which are arranged in opposite directions, and the first functional surface of the first chip faces the first carrier plate;
the step of forming a plastic sealing layer on one side of the first carrier plate, where the first chip is arranged, includes:
Forming a plastic sealing layer on one side of the first carrier plate, where the first chip is arranged, wherein the plastic sealing layer covers the conductive column and a gap in a space surrounded by the conductive column; the plastic sealing layer is flush with the surface of one side of the conductive column, which faces away from the carrier plate.
8. The fan-out packaging method of claim 1, wherein after removing the first carrier, further comprising:
Forming a first rewiring layer and a second rewiring layer on two sides of the conductive column in the length direction respectively; wherein the first rewiring layer is electrically connected with at least the conductive pillars and the first chip, and the second rewiring layer is electrically connected with the conductive pillars;
A first electrical connector is disposed on a side of the first rewiring layer facing away from the conductive post, and a second electrical connector is disposed on a side of the second rewiring layer facing away from the conductive post.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101170088A (en) * | 2006-10-27 | 2008-04-30 | 台湾积体电路制造股份有限公司 | Semiconductor package structure and its forming method |
| CN111554617A (en) * | 2020-04-30 | 2020-08-18 | 通富微电子股份有限公司 | Chip packaging method |
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| TWI531283B (en) * | 2012-10-26 | 2016-04-21 | 臻鼎科技股份有限公司 | Connecting substrate and package on package structure |
| KR102586890B1 (en) * | 2019-04-03 | 2023-10-06 | 삼성전기주식회사 | Semiconductor package |
| CN111554629A (en) * | 2020-04-30 | 2020-08-18 | 通富微电子股份有限公司 | Chip packaging method |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101170088A (en) * | 2006-10-27 | 2008-04-30 | 台湾积体电路制造股份有限公司 | Semiconductor package structure and its forming method |
| CN111554617A (en) * | 2020-04-30 | 2020-08-18 | 通富微电子股份有限公司 | Chip packaging method |
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