CN114510104B

CN114510104B - Band gap reference starting circuit

Info

Publication number: CN114510104B
Application number: CN202210111393.8A
Authority: CN
Inventors: 李雪民
Original assignee: Suzhou Linghui Lixin Technology Co ltd
Current assignee: Suzhou Linghui Lixin Technology Co ltd
Priority date: 2022-01-29
Filing date: 2022-01-29
Publication date: 2023-10-20
Anticipated expiration: 2042-01-29
Also published as: CN114510104A

Abstract

The invention discloses a band gap reference starting circuit, which comprises: a bandgap reference circuit module and a start circuit module; the band gap reference circuit module is connected with a power supply; the starting circuit module is respectively connected with the band gap reference circuit module and the power supply, and when the band gap reference circuit module is at a zero working point, the starting circuit module enables the band gap reference circuit module to recover to normal work; the starting circuit module comprises a first PMOS tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a first NMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube and a fifth NMOS tube, wherein the first NMOS tube, the fourth NMOS tube and the fifth NMOS tube are respectively connected with the band gap reference circuit module. The invention ensures that the output voltage can restore the band-gap reference circuit to work under any condition, so that the band-gap reference starting circuit has better robustness.

Description

Band gap reference starting circuit

Technical Field

The invention belongs to the technical field of electronic circuits, and particularly relates to a band gap reference starting circuit.

Background

A Bandgap reference (Bandgap) circuit provides a voltage to the chip that does not change with temperature and process variations. The bandgap circuit typically has two reasonable operating points, one being a normal operating point and the other being a zero voltage operating point. In actual operation, the occurrence of zero operation point is avoided as much as possible, so that the starting circuit is required for the common bandgap circuit.

The bandgap start-up circuit typically mirrors one current generated by the bandgap circuit with a non-zero current in the other. If the bandgap circuit is at the zero working point, the starting circuit pulls the grid electrode of the NMOS tube high or the grid electrode of the PMOS tube low through the output of the current operational amplifier so as to lead the circuit to be separated from the zero working point. If the bandgap circuit is in the normal mode of operation, the start-up circuit is not active.

FIG. 1 is a schematic diagram of a bandgap circuit and its start-up circuit. The virtual short nature of the op-amp in normal operation is such that vn=vp, and therefore dvbe=vtln (m), where m is the area ratio of Q2 to Q1, is added across R1 to produce PTAT current, assuming r2=r3, vref=vbe2+dvbe/r1 (r3+2r4), the first term is a negative temperature Coefficient (CTAT) term, and the second term is a positive temperature coefficient (PTAT) term. At this time, the current of PM4 mirrored to NM3 is larger than the current flowing through the transistors in the linear region formed by the series connection of PMa1 to PMaN, so VCOMP is 0, the transistor NM_clamp is not conductive, and the start-up circuit does not operate. At zero operating point, the current flowing through R1/R2/R3/R4 is 0, VREF is a voltage smaller than that of transistor VEB, and PM 1-PM 4 have no current, at this time, the current of PM4 mirror image to NM3 is smaller than that flowing through the transistors in the linear region formed by connecting PMa 1-PMaN in series, VCOMP is high level, so that the transistor NM_clamp is conducted, and the grid voltage VAMP of NM1 is pulled high so as to deviate from zero operating point.

The starting scheme only detects the current generated by the circuit to judge whether the circuit is started successfully or not. However, in some cases a single detected current may not guarantee that the output Voltage (VREF) outputs a normal value. For example, during slow power-up of the power supply, there is a current that may be NM3 just equal to or slightly greater than the current of PMa 1-PMaN, VCOMP goes low, transistor nm_clamp is off, and the start-up circuit is no longer functional. But at this time, the VREF voltage still does not reach around 1.2V because the current in the circuit is small (e.g., tens of nA). Whereas the op-amp has an offset due to the finite gain, the difference between vp=vn is not negligible (because the voltage difference across R1 is small), so dvbe=vt ln (m) is no longer true. On the other hand, since the bias current of the operational amplifier is also from the circuit, the operational amplifier may not work normally at this time. In this way, the negative feedback loop is broken, and the output VREF cannot be set to about 1.2V. VREF is typically much less than 0.7V due to the small current.

Therefore, there is a particular need for a robust start-up circuit that can restore operation of a bandgap reference circuit at a variety of voltage values for the output voltage of the bandgap reference circuit.

Disclosure of Invention

The invention aims to provide a starting circuit with good robustness, and the band gap reference circuit can be recovered to work under various voltage values of the output voltage of the band gap reference circuit.

In order to achieve the above object, the present invention provides a bandgap reference start-up circuit comprising: a bandgap reference circuit module and a start circuit module; the band gap reference circuit module is connected with a power supply; the starting circuit module is respectively connected with the band gap reference circuit module and the power supply, and the starting circuit module enables the band gap reference circuit module to recover normal operation; the starting circuit module comprises a linear region transistor, a fourth PMOS tube, a first NMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube and a fifth NMOS tube which are formed by connecting a plurality of PMOS tubes in series, wherein the number of the PMOS tubes connected in series in the linear region transistor is more than three, the first PMOS tube in the plurality of PMOS tubes connected in series is a first PMOS tube, and the last PMOS tube is a third PMOS tube; the first PMOS tube is connected with the power supply, and the third PMOS tube is connected with the first NMOS tube and the third NMOS tube respectively; the first NMOS tube is connected with the band gap reference circuit module, the third PMOS tube and the third NMOS tube respectively, the second NMOS tube is connected with the fourth PMOS tube, the third NMOS tube and the fourth NMOS tube respectively, the third NMOS tube is connected with the third PMOS tube, the first NMOS tube, the second NMOS tube and the fifth NMOS tube respectively, the fourth NMOS tube is connected with the second NMOS tube, the fifth NMOS tube and the band gap reference circuit module respectively, and the fifth NMOS tube is connected with the third NMOS tube, the fourth NMOS tube and the band gap reference circuit module respectively.

Preferably, the source electrode of the first PMOS transistor is connected with the positive electrode of the power supply, the gate electrode of each PMOS transistor in the linear region transistor is connected with the negative electrode of the power supply, and the source electrode of the latter PMOS transistor is connected with the drain electrode of the former PMOS transistor in any two adjacent PMOS transistors in the linear region transistor; the drain electrode of the third PMOS tube is respectively connected with the drain electrode, the grid electrode and the drain electrode of the third NMOS tube; the source electrode of the fourth PMOS tube is connected with the positive electrode of the power supply, the drain electrode of the fourth PMOS tube is respectively connected with the grid electrode and the drain electrode of the second NMOS tube and the grid electrode of the third NMOS tube, and the grid electrode of the fourth PMOS tube is connected with the band gap reference circuit module; the drain electrode of the first NMOS tube is respectively connected with the grid electrode of the first NMOS tube, the drain electrode of the third PMOS tube and the drain electrode of the third NMOS tube, the grid electrode of the first NMOS tube is respectively connected with the drain electrode of the first NMOS tube, the drain electrode of the third PMOS tube and the drain electrode of the third NMOS tube, and the source electrode of the first NMOS tube is connected with the band gap reference circuit module; the drain electrode of the second NMOS tube is respectively connected with the grid electrode of the second NMOS tube, the grid electrode of the third NMOS tube and the drain electrode of the fourth PMOS tube, the grid electrode of the second NMOS tube is respectively connected with the drain electrode of the second NMOS tube, the grid electrode of the third NMOS tube and the drain electrode of the fourth PMOS tube, and the source electrode of the second NMOS tube is connected with the drain electrode of the fourth NMOS tube; the drain electrode of the third NMOS tube is respectively connected with the drain electrode, the grid electrode and the drain electrode of the third PMOS tube, the grid electrode of the third NMOS tube is respectively connected with the grid electrode, the drain electrode and the drain electrode of the fourth PMOS tube, and the source electrode of the third NMOS tube is connected with the drain electrode of the fifth NMOS tube.

Preferably, the grid electrode of the fourth NMOS tube is connected with the grid electrode of the fifth NMOS tube and the band gap reference circuit module respectively, the drain electrode of the fourth NMOS tube is connected with the source electrode of the second NMOS tube, and the source electrode of the fourth NMOS tube is connected with the negative electrode of the power supply; the grid electrode of the fifth NMOS tube is respectively connected with the grid electrode of the fourth NMOS tube and the band gap reference circuit module, the drain electrode of the fifth NMOS tube is connected with the source electrode of the third NMOS tube, and the source electrode of the fifth NMOS tube is connected with the negative electrode of the power supply.

Preferably, the bandgap reference circuit module includes: the third PMOS transistor is connected with the first resistor and the second resistor, and is connected with the second resistor and the third resistor; the source electrode of the fifth PMOS tube is connected with the positive electrode of the power supply, the grid electrode of the fifth PMOS tube is respectively connected with the grid electrode of the fourth PMOS tube, the grid electrode of the sixth PMOS tube and the grid electrode of the seventh PMOS tube, and the drain electrode of the fifth PMOS tube is connected with one end of the fourth resistor, the grid electrode of the fifth NMOS tube and the grid electrode of the fourth NMOS tube; the source electrode of the sixth PMOS tube is connected with the positive electrode of the power supply, the grid electrode of the sixth PMOS tube is respectively connected with the grid electrode of the fourth PMOS tube, the grid electrode of the fifth PMOS tube and the grid electrode of the seventh PMOS tube, and the drain electrode of the sixth PMOS tube is connected with the first end of the operational amplifier; the source electrode of the seventh PMOS tube is connected with the positive electrode of the power supply, the grid electrode of the seventh PMOS tube is respectively connected with the grid electrode of the fourth PMOS tube, the grid electrode of the fifth PMOS tube and the grid electrode of the sixth PMOS tube, and the drain electrode of the seventh PMOS tube is connected with the drain electrode of the sixth NMOS tube.

Preferably, the other end of the fourth resistor is connected with one end of the second resistor and one end of the third resistor respectively, the other end of the second resistor is connected with one end of the first resistor and the negative phase input end of the operational amplifier respectively, the other end of the first resistor is connected with the emitter of the first triode, and the other end of the third resistor is connected with the positive phase input end of the operational amplifier and the emitter of the second triode respectively; the emitter of the first triode is connected with the other end of the first resistor, and the base electrode and the collector electrode of the first triode are connected with the negative electrode of the power supply; and the emitter of the second triode is connected with the other end of the third resistor, and the base electrode and the collector electrode of the second triode are both connected with the negative electrode of the power supply.

Preferably, the negative phase input end of the operational amplifier is connected with the other end of the second resistor and one end of the first resistor respectively, the positive input end of the operational amplifier is connected with the other end of the third resistor and the emitter of the second amplifier respectively, the first end of the operational amplifier is connected with the drain electrode of the sixth PMOS tube, and the output end of the operational amplifier is connected with the grid electrode of the sixth NMOS tube and the source electrode of the first NMOS tube respectively; the grid electrode of the sixth NMOS tube is respectively connected with the output end of the operational amplifier and the source electrode of the first NMOS tube, the drain electrode of the sixth NMOS tube is connected with the drain electrode of the seventh PMOS tube, and the source electrode of the sixth NMOS tube is connected with the negative electrode of the power supply.

Preferably, the voltage at the junction of the drain electrode of the fifth PMOS, one end of the fourth resistor, the gate electrode of the fifth NMOS and the gate electrode of the fourth NMOS is the output voltage of the bandgap reference circuit module.

The invention has the beneficial effects that: the starting circuit module in the band-gap reference starting circuit enables the band-gap reference circuit module to recover to work normally, and the band-gap reference circuit can recover to work under the condition that the output voltage of the band-gap reference circuit module is various voltage values, so that the band-gap reference starting circuit has better robustness.

The device of the present invention has other features and advantages which will be apparent from or are set forth in detail in the accompanying drawings and the following detailed description, which are incorporated herein, and which together serve to explain certain principles of the invention.

Drawings

The foregoing and other objects, features and advantages of the invention will be apparent from the following more particular descriptions of exemplary embodiments of the invention as illustrated in the accompanying drawings wherein like reference numbers generally represent like parts throughout the exemplary embodiments of the invention.

Fig. 1 shows a schematic diagram of a prior art bandgap reference start-up.

Fig. 2 shows a schematic diagram of a bandgap reference start-up circuit according to the invention.

Reference numerals illustrate:

102. starting a circuit module; 104. a bandgap reference circuit module; PMa1, a first PMOS tube; PMa2, a second PMOS tube; PMaN, third PMOS tube; PM4, a fourth PMOS tube; PM3, a fifth PMOS tube; PM2, a sixth PMOS tube; PM1, a seventh PMOS tube; NM-clamp, first NMOS tube; NM1, a sixth NMOS tube; NM2, a second NMOS tube; NM3, third NMOS tube; NM4, a fourth NMOS tube; NM5, a fifth NMOS tube; r1, a first resistor; r2, a second resistor; r3, a third resistor; r4, a fourth resistor; q1, a first triode; q2, a second triode; u1, an operational amplifier; AVDD, positive pole of the power supply; AGND, negative pole of power supply; VREF, output voltage.

Detailed Description

Preferred embodiments of the present invention will be described in more detail below. While the preferred embodiments of the present invention are described below, it should be understood that the present invention may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.

A bandgap reference start-up circuit according to the present invention comprises: a bandgap reference circuit module and a start circuit module; the band gap reference circuit module is connected with a power supply; the starting circuit module is respectively connected with the band gap reference circuit module and the power supply, and the starting circuit module is respectively connected with the band gap reference circuit module and the power supply, so that the band gap reference circuit module can recover to work normally; the starting circuit module comprises a linear region transistor, a fourth PMOS tube, a first NMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube and a fifth NMOS tube which are formed by connecting a plurality of PMOS tubes in series, wherein the number of the PMOS tubes connected in series in the linear region transistor is more than three, the first PMOS tube in the plurality of PMOS tubes connected in series is a first PMOS tube, and the last PMOS tube is a third PMOS tube; the first PMOS tube is connected with a power supply, and the third PMOS tube is respectively connected with the first NMOS tube, the second NMOS tube and the third NMOS tube; the first NMOS tube is respectively connected with the band gap reference circuit module, the third PMOS tube and the third NMOS tube, the second NMOS tube is respectively connected with the fourth PMOS tube, the third NMOS tube and the fourth NMOS tube, the third NMOS tube is respectively connected with the third PMOS tube, the first NMOS tube and the fifth NMOS tube, the fourth NMOS tube is respectively connected with the second NMOS tube, the fifth NMOS tube and the band gap reference circuit module, and the fifth NMOS tube is respectively connected with the third NMOS tube, the fourth NMOS tube and the band gap reference circuit module.

Specifically, when the band gap reference circuit is at zero point, the combined action of the linear region transistor, the fourth PMOS transistor, the first NMOS transistor, the second NMOS transistor and the third NMOS transistor enables the band gap reference circuit to resume normal operation, and when the band gap reference circuit is not at zero point and the output voltage of the band gap reference circuit is smaller than the threshold voltage, the combined action of the linear region transistor, the fourth PMOS transistor, the first NMOS transistor, the second NMOS transistor, the third NMOS transistor, the fourth NMOS transistor and the fifth NMOS transistor enables the band gap reference circuit to resume normal operation, and the threshold voltage is preferably 0.7V.

According to the exemplary embodiment, the starting circuit module in the band-gap reference starting circuit enables the band-gap reference circuit module to recover to work, and the band-gap reference circuit can be recovered to work under the condition that the output voltage of the band-gap reference circuit module is various voltage values, so that the band-gap reference starting circuit has better robustness.

As a preferred scheme, the source electrode of the first PMOS tube is connected with the positive electrode of the power supply, the grid electrode of each PMOS tube in the linear region transistor is connected with the negative electrode of the power supply, and the source electrode of the latter PMOS tube is connected with the drain electrode of the former PMOS tube in any two adjacent PMOS tubes in the linear region transistor; the drain electrode of the third PMOS tube is respectively connected with the drain electrode, the grid electrode and the drain electrode of the third NMOS tube; the source electrode of the fourth PMOS tube is connected with the positive electrode of the power supply, the drain electrode of the fourth PMOS tube is respectively connected with the grid electrode and the drain electrode of the second NMOS tube and the grid electrode of the third NMOS tube, and the grid electrode of the fourth PMOS tube is connected with the band gap reference circuit module; the drain electrode of the first NMOS tube is respectively connected with the grid electrode of the first NMOS tube, the drain electrode of the third PMOS tube and the drain electrode of the third NMOS tube, the grid electrode of the first NMOS tube is respectively connected with the drain electrode of the first NMOS tube, the drain electrode of the third PMOS tube and the drain electrode of the third NMOS tube, and the source electrode of the first NMOS tube is connected with the band gap reference circuit module; the drain electrode of the second NMOS tube is respectively connected with the grid electrode of the second NMOS tube, the grid electrode of the third NMOS tube and the drain electrode of the fourth PMOS tube, the grid electrode of the second NMOS tube is respectively connected with the drain electrode of the second NMOS tube, the grid electrode of the third NMOS tube and the drain electrode of the fourth PMOS tube, and the source electrode of the second NMOS tube is connected with the drain electrode of the fourth NMOS tube; the drain electrode of the third NMOS tube is respectively connected with the drain electrode of the first NMOS tube, the gate electrode of the third NMOS tube and the drain electrode of the third PMOS tube, the gate electrode of the third NMOS tube is respectively connected with the gate electrode of the second NMOS tube, the drain electrode of the third NMOS tube and the drain electrode of the fourth PMOS tube, and the source electrode of the third NMOS tube is connected with the drain electrode of the fifth NMOS tube.

Specifically, when the output voltage is higher than 0.7V, the current mirrored from the fourth PMOS transistor to the third NMOS transistor is smaller than the current flowing through the linear region transistor formed by the series connection of the first PMOS transistor to the third PMOS transistor, and VCOMP is at a high level, so that the first NMOS transistor is turned on, and the gate voltage VAMP of the sixth NMOS transistor is pulled high so as to be separated from the zero operating point.

As a preferred scheme, the grid electrode of the fourth NMOS tube is respectively connected with the grid electrode of the fifth NMOS tube and the band-gap reference circuit module, the drain electrode of the fourth NMOS tube is connected with the source electrode of the second NMOS tube, and the source electrode of the fourth NMOS tube is connected with the negative electrode of the power supply; the grid electrode of the fifth NMOS tube is respectively connected with the grid electrode of the fourth NMOS tube and the band gap reference circuit module, the drain electrode of the fifth NMOS tube is connected with the source electrode of the third NMOS tube, and the source electrode of the fifth NMOS tube is connected with the negative electrode of the power supply.

Specifically, when the output voltage is less than 0.7V, a fourth NMOS transistor and a fifth NMOS transistor are added in the starting circuit, and the gates of the fourth NMOS transistor and the fifth NMOS transistor are connected to VREF, so that no current flows in the second NMOS transistor and the third NMOS transistor, VCOMP is pulled high, and therefore the gate of the first NMOS transistor is pulled high, and the circuit finally enters a normal working mode through negative feedback.

Specifically, the current flowing through the fifth PMOS transistor is split and flows into the operational amplifier.

As a preferred scheme, the other end of the fourth resistor is respectively connected with one end of the second resistor and one end of the third resistor, the other end of the second resistor is respectively connected with one end of the first resistor and the negative phase input end of the operational amplifier, the other end of the first resistor is connected with the emitter of the first triode, and the other end of the third resistor is respectively connected with the positive phase input end of the operational amplifier and the emitter of the second triode; the emitter of the first triode is connected with the other end of the first resistor, and the base electrode and the collector electrode of the first triode are connected with the negative electrode of the power supply; the emitter of the second triode is connected with the other end of the third resistor, and the base electrode and the collector electrode of the second triode are both connected with the negative electrode of the power supply.

Specifically, the first resistor, the second resistor and the third resistor are used for shunting, and the shunted current flows into the non-inverting input end and the inverting input end of the operational amplifier respectively.

As a preferred scheme, the negative phase input end of the operational amplifier is respectively connected with the other end of the second resistor and one end of the first resistor, the positive phase input end of the operational amplifier is respectively connected with the other end of the third resistor and the emitter of the second amplifier, the first end of the operational amplifier is connected with the drain electrode of the sixth PMOS tube, and the output end of the operational amplifier is respectively connected with the grid electrode of the sixth NMOS tube and the source electrode of the first NMOS tube; the grid electrode of the sixth NMOS tube is respectively connected with the output end of the operational amplifier and the source electrode of the first NMOS tube, the drain electrode of the sixth NMOS tube is connected with the drain electrode of the seventh PMOS tube, and the source electrode of the sixth NMOS tube is connected with the negative electrode of the power supply.

Specifically, when the output voltage is greater than 0.7V, the output voltage of the operational amplifier is high, the operational amplifier works normally, and the output of the operational amplifier pulls the gate of the sixth NMOS high, so that the circuit is separated from the zero operating point.

As a preferable scheme, the voltage at the junction of the drain electrode of the fifth PMOS tube, one end of the fourth resistor, the grid electrode of the fifth NMOS tube and the grid electrode of the fourth NMOS tube is the output voltage of the band-gap reference circuit module.

Examples

As shown in fig. 2, the bandgap reference start-up circuit includes: a bandgap reference circuit block 104 and a start-up circuit block 102; the band gap reference circuit module 104 is connected with a power supply; the starting circuit module 102 is respectively connected with the band-gap reference circuit module 104 and the power supply, and when the output voltage of the band-gap reference circuit module 104 is zero, the starting circuit module 102 enables the band-gap reference circuit module 104 to resume normal operation; the starting circuit module 102 comprises a linear region transistor, a fourth PMOS tube PM4, a first NMOS tube NM-clamp, a second NMOS tube NM2, a third NMOS tube NM3, a fourth NMOS tube NM4 and a fifth NMOS tube NM5 which are formed by connecting a plurality of PMOS tubes in series; the number of PMOS tubes connected in series in the linear region transistor is greater than three, the first PMOS tube in the plurality of PMOS tubes connected in series is a first PMOS tube PMa1, the second PMOS tube is PMa2, and the last PMOS tube is a third PMOS tube PMaN. The first PMOS tube PMa1 is connected with a power supply, and the third PMOS tube PMaN is respectively connected with a first NMOS tube NM-clamp, a second NMOS tube NM2 and a third NMOS tube NM 3; the first NMOS tube NM-clamp is respectively connected with the band-gap reference circuit module 104, the third PMOS tube PMaN and the third NMOS tube NM3, the second NMOS tube NM2 is respectively connected with the fourth PMOS tube PM4, the third NMOS tube NM3 and the fourth NMOS tube NM4, the third NMOS tube NM3 is respectively connected with the third PMOS tube PMaN, the first NMOS tube NM-clamp, the second NMOS tube NM2 and the fifth NMOS tube NM5, the fourth NMOS tube NM4 is respectively connected with the second NMOS tube NM2, the fifth NMOS tube NM5 and the band-gap reference circuit module 104, and the fifth NMOS tube NM5 is respectively connected with the third NMOS tube NM3, the fourth NMOS tube NM4 and the band-gap reference circuit module 104.

The source electrode of the first PMOS tube PMa1 is connected with the positive electrode of the power supply, the grid electrode of each PMOS tube in the linear region transistor is connected with the negative electrode of the power supply, and the source electrode of the latter PMOS tube is connected with the drain electrode of the former PMOS tube in any two adjacent PMOS tubes in the linear region transistor; the drain electrode of the third PMOS tube PMaN is respectively connected with the drain electrode and the grid electrode of the first NMOS tube NM-clamp and the drain electrode of the third NMOS tube NM 3; the source electrode of the fourth PMOS tube PM4 is connected with the positive electrode of the power supply, the drain electrode of the fourth PMOS tube PM4 is respectively connected with the grid electrode and the drain electrode of the second NMOS tube NM2 and the grid electrode of the third NMOS tube NM3, and the grid electrode of the fourth PMOS tube PM4 is connected with the band gap reference circuit module 104; the drain electrode of the first NMOS tube NM-clamp is respectively connected with the drain electrode of the third PMOS tube PMaN and the drain electrode of the third NMOS tube NM3, the gate electrode of the first NMOS tube NM-clamp is respectively connected with the drain electrode of the first NMOS tube NM-clamp, the drain electrode of the third PMOS tube PMaN and the drain electrode of the third NMOS tube NM3, and the source electrode of the first NMOS tube NM-clamp is connected with the band gap reference circuit module 104; the drain electrode of the second NMOS tube NM2 is respectively connected with the grid electrode of the second NMOS tube NM2, the grid electrode of the third NMOS tube NM3 and the drain electrode of the fourth PMOS tube PM4, the grid electrode of the second NMOS tube NM2 is respectively connected with the drain electrode of the second NMOS tube NM2, the grid electrode of the third NMOS tube NM3 and the drain electrode of the fourth PMOS tube PM4, and the source electrode of the second NMOS tube NM2 is connected with the drain electrode of the fourth NMOS tube NM 4; the drain electrode of the third NMOS tube NM3 is respectively connected with the drain electrode, the grid electrode and the drain electrode of the first NMOS tube NM-clamp, the grid electrode of the third NMOS tube NM3 is respectively connected with the grid electrode, the drain electrode and the drain electrode of the fourth PMOS tube PM4 of the second NMOS tube NM2, and the source electrode of the third NMOS tube NM3 is connected with the drain electrode of the fifth NMOS tube NM 5.

The gate of the fourth NMOS transistor NM4 is connected to the gate of the fifth NMOS transistor NM5 and the bandgap reference circuit module 104, the drain of the fourth NMOS transistor NM4 is connected to the source of the second NMOS transistor NM2, and the source of the fourth NMOS transistor NM4 is connected to the negative electrode AGND of the power supply; the gate of the fifth NMOS transistor NM5 is connected to the gate of the fourth NMOS transistor NM4 and the bandgap reference circuit module 104, the drain of the fifth NMOS transistor NM5 is connected to the source of the third NMOS transistor NM3, and the source of the fifth NMOS transistor NM5 is connected to the negative electrode AGND of the power supply.

Wherein the bandgap reference circuit module 104 comprises: the third PMOS transistor PM3, the fourth PMOS transistor PM2, the fifth PMOS transistor PM1, the first resistor R1, the second resistor R2, the third resistor R3, the first triode Q1, the second triode Q2, the operational amplifier U1 and the fourth NMOS transistor NM1; the source electrode of the fifth PMOS tube PM3 is connected with the positive pole AVDD of the power supply, the grid electrode of the fifth PMOS tube PM3 is respectively connected with the grid electrode of the fourth PMOS tube PM4, the grid electrode of the sixth PMOS tube PM2 and the grid electrode of the seventh PMOS tube PM1, and the drain electrode of the fifth PMOS tube PM3 is connected with one end of the fourth resistor R4, the grid electrode of the fifth NMOS tube NM5 and the grid electrode of the fourth NMOS tube NM 4; the source electrode of the sixth PMOS tube PM2 is connected with the positive pole AVDD of the power supply, the grid electrode of the sixth PMOS tube PM2 is respectively connected with the grid electrode of the fourth PMOS tube PM4, the grid electrode of the fifth PMOS tube PM3 and the grid electrode of the seventh PMOS tube PM1, and the drain electrode of the sixth PMOS tube PM2 is connected with the first end of the operational amplifier U1; the source electrode of the seventh PMOS tube PM1 is connected with the positive electrode AVDD of the power supply, the grid electrode of the seventh PMOS tube PM1 is respectively connected with the grid electrode of the fourth PMOS tube PM4, the grid electrode of the fifth PMOS tube PM3 and the grid electrode of the sixth PMOS tube PM2, and the drain electrode of the seventh PMOS tube PM1 is connected with the drain electrode of the sixth NMOS tube NM 1.

The other end of the fourth resistor R4 is respectively connected with one end of the second resistor R2 and one end of the third resistor R3, the other end of the second resistor R2 is respectively connected with one end of the first resistor R1 and the negative phase input end of the operational amplifier U1, the other end of the first resistor R1 is connected with the emitter of the first triode Q1, and the other end of the third resistor R3 is respectively connected with the positive phase input end of the operational amplifier U1 and the emitter of the second triode Q2; the emitter of the first triode Q1 is connected with the other end of the first resistor R1, and the base electrode and the collector electrode of the first triode Q1 are connected with the negative electrode AGND of the power supply; the emitter of the second triode Q2 is connected with the other end of the third resistor R3, and the base electrode and the collector electrode of the second triode Q2 are connected with the negative electrode AGND of the power supply.

The positive and negative phase input ends of the operational amplifier U1 are respectively connected with the other end of the second resistor R2 and one end of the first resistor R1, the positive input end of the operational amplifier U1 is respectively connected with the other end of the third resistor R3 and the emitter of the second amplifier, the first end of the operational amplifier U1 is connected with the drain electrode of the sixth PMOS tube PM2, and the output end of the operational amplifier U1 is respectively connected with the grid electrode of the sixth NMOS tube NM1 and the source electrode of the first NMOS tube NM-clamp; the grid electrode of the sixth NMOS tube NM1 is respectively connected with the output end of the operational amplifier U1 and the source electrode of the first NMOS tube NM-clamp, the drain electrode of the sixth NMOS tube NM1 is connected with the drain electrode of the seventh PMOS tube PM1, and the source electrode of the sixth NMOS tube NM1 is connected with the negative electrode AGND of the power supply.

The voltage at the junction of the drain of the fifth PMOS PM3, one end of the fourth resistor R4, the gate of the fifth NMOS NM5, and the gate of the fourth NMOS NM4 is the output voltage VREF of the bandgap reference circuit module 104.

The foregoing description of embodiments of the invention has been presented for purposes of illustration and description, and is not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the various embodiments described.

Claims

1. A bandgap reference start-up circuit, comprising: a bandgap reference circuit module and a start circuit module;

the band gap reference circuit module is connected with a power supply;

the starting circuit module is respectively connected with the band gap reference circuit module and the power supply, and the starting circuit module enables the band gap reference circuit module to recover normal operation;

the starting circuit module comprises a linear region transistor, a fourth PMOS tube, a first NMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube and a fifth NMOS tube which are formed by connecting a plurality of PMOS tubes in series, wherein the number of the PMOS tubes connected in series in the linear region transistor is more than three, the first PMOS tube in the plurality of PMOS tubes connected in series is a first PMOS tube, and the last PMOS tube is a third PMOS tube;

the first PMOS tube is connected with the power supply, and the third PMOS tube is connected with the first NMOS tube and the third NMOS tube respectively;

the first NMOS tube is respectively connected with the band gap reference circuit module, the third PMOS tube and the third NMOS tube, the second NMOS tube is respectively connected with the fourth PMOS tube, the third NMOS tube and the fourth NMOS tube, the third NMOS tube is respectively connected with the third PMOS tube, the first NMOS tube, the second NMOS tube and the fifth NMOS tube, the fourth NMOS tube is respectively connected with the second NMOS tube, the fifth NMOS tube and the band gap reference circuit module, and the fifth NMOS tube is respectively connected with the third NMOS tube, the fourth NMOS tube and the band gap reference circuit module;

the grid electrode of the fourth NMOS tube and the grid electrode of the fifth NMOS tube are connected with the output voltage of the band gap reference circuit module, the drain electrode of the fourth NMOS tube is connected with the source electrode of the second NMOS tube, and the source electrode of the fourth NMOS tube is connected with the negative electrode of the power supply;

the grid electrode of the fifth NMOS tube is respectively connected with the grid electrode of the fourth NMOS tube and the band gap reference circuit module, the drain electrode of the fifth NMOS tube is connected with the source electrode of the third NMOS tube, and the source electrode of the fifth NMOS tube is connected with the negative electrode of the power supply;

the source electrode of the first PMOS tube is connected with the positive electrode of the power supply, the grid electrode of each PMOS tube in the linear region transistor is connected with the negative electrode of the power supply, and the source electrode of the latter PMOS tube is connected with the drain electrode of the former PMOS tube in any two adjacent PMOS tubes in the linear region transistor;

the drain electrode of the third PMOS tube is respectively connected with the drain electrode, the grid electrode and the drain electrode of the third NMOS tube;

the source electrode of the fourth PMOS tube is connected with the positive electrode of the power supply, the drain electrode of the fourth PMOS tube is respectively connected with the grid electrode and the drain electrode of the second NMOS tube and the grid electrode of the third NMOS tube, and the grid electrode of the fourth PMOS tube is connected with the grid electrode of a transistor connected with the positive electrode of the power supply in the band gap reference circuit module;

the drain electrode of the first NMOS tube is respectively connected with the grid electrode of the first NMOS tube, the drain electrode of the third PMOS tube and the drain electrode of the third NMOS tube, the grid electrode of the first NMOS tube is respectively connected with the drain electrode of the first NMOS tube, the drain electrode of the third PMOS tube and the drain electrode of the third NMOS tube, and the source electrode of the first NMOS tube is connected with the output end of the operational amplifier in the band gap reference circuit module;

the drain electrode of the second NMOS tube is respectively connected with the grid electrode of the second NMOS tube, the grid electrode of the third NMOS tube and the drain electrode of the fourth PMOS tube, the grid electrode of the second NMOS tube is respectively connected with the drain electrode of the second NMOS tube, the grid electrode of the third NMOS tube and the drain electrode of the fourth PMOS tube, and the source electrode of the second NMOS tube is connected with the drain electrode of the fourth NMOS tube;

the drain electrode of the third NMOS tube is respectively connected with the drain electrode, the grid electrode and the drain electrode of the third PMOS tube, the grid electrode of the third NMOS tube is respectively connected with the grid electrode, the drain electrode and the drain electrode of the fourth PMOS tube, and the source electrode of the third NMOS tube is connected with the drain electrode of the fifth NMOS tube.

2. The bandgap reference start-up circuit of claim 1, wherein said bandgap reference circuit module comprises: the third PMOS transistor is connected with the first resistor and the second resistor, and is connected with the second resistor and the third resistor;

the source electrode of the fifth PMOS tube is connected with the positive electrode of the power supply, the grid electrode of the fifth PMOS tube is respectively connected with the grid electrode of the fourth PMOS tube, the grid electrode of the sixth PMOS tube and the grid electrode of the seventh PMOS tube, and the drain electrode of the fifth PMOS tube is connected with one end of the fourth resistor, the grid electrode of the fifth NMOS tube and the grid electrode of the fourth NMOS tube;

the source electrode of the sixth PMOS tube is connected with the positive electrode of the power supply, the grid electrode of the sixth PMOS tube is respectively connected with the grid electrode of the fourth PMOS tube, the grid electrode of the fifth PMOS tube and the grid electrode of the seventh PMOS tube, and the drain electrode of the sixth PMOS tube is connected with the first end of the operational amplifier;

the source electrode of the seventh PMOS tube is connected with the positive electrode of the power supply, the grid electrode of the seventh PMOS tube is respectively connected with the grid electrode of the fourth PMOS tube, the grid electrode of the fifth PMOS tube and the grid electrode of the sixth PMOS tube, the drain electrode of the seventh PMOS tube is connected with the drain electrode of the sixth NMOS tube, and the grid electrode of the seventh PMOS tube is connected with the drain electrode.

3. The bandgap reference start-up circuit according to claim 2, wherein the other end of the fourth resistor is connected to one end of the second resistor and one end of a third resistor, respectively, the other end of the second resistor is connected to one end of the first resistor and the negative input terminal of the operational amplifier, respectively, the other end of the first resistor is connected to the emitter of the first triode, and the other end of the third resistor is connected to the positive input terminal of the operational amplifier and the emitter of the second triode, respectively;

the emitter of the first triode is connected with the other end of the first resistor, and the base electrode and the collector electrode of the first triode are connected with the negative electrode of the power supply;

and the emitter of the second triode is connected with the other end of the third resistor, and the base electrode and the collector electrode of the second triode are both connected with the negative electrode of the power supply.

4. A bandgap reference start-up circuit according to claim 3, wherein the negative phase input terminal of the operational amplifier is connected to the other end of the second resistor and one end of the first resistor, the positive input terminal of the operational amplifier is connected to the other end of the third resistor and the emitter of the second amplifier, the first end of the operational amplifier is connected to the drain of the sixth PMOS transistor, and the output terminal of the operational amplifier is connected to the gate of the sixth NMOS transistor and the source of the first NMOS transistor, respectively;

the grid electrode of the sixth NMOS tube is respectively connected with the output end of the operational amplifier and the source electrode of the first NMOS tube, the drain electrode of the sixth NMOS tube is connected with the drain electrode of the seventh PMOS tube, and the source electrode of the sixth NMOS tube is connected with the negative electrode of the power supply.

5. The bandgap reference start-up circuit of claim 4, wherein the voltage at the junction of the drain of said fifth PMOS transistor, one end of said fourth resistor, the gate of said fifth NMOS transistor and the gate of said fourth NMOS transistor is the output voltage of said bandgap reference circuit module.