CN114490474A - System for realizing extension of multi-path UART (universal asynchronous receiver/transmitter) interface through CPLD (complex programmable logic device) - Google Patents
System for realizing extension of multi-path UART (universal asynchronous receiver/transmitter) interface through CPLD (complex programmable logic device) Download PDFInfo
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Abstract
A system for realizing multi-path UART interface extension through a CPLD comprises a CPU module and a CPLD module, wherein the CPLD module comprises a CPU port UART module, a channel selection and control module and 8 service port UART modules as service UART interfaces, the CPU port UART module is in communication connection with the UART interfaces of the CPU module, the CPU port UART module is connected with the channel selection and control module, the 8 service port UART modules are all connected with the CPU module for performing parameter configuration on the service port UART modules, and the 8 service port UART modules are all connected with the channel selection and control module for selecting the service port UART modules according to requirements to realize corresponding UART interface data communication. The invention realizes the extension function of the UART interface accessed by the CPU module through the CPLD module.
Description
Technical Field
The invention belongs to the technical field of highway tunnel detection, and particularly relates to a system for realizing multi-path UART interface extension through a CPLD.
Background
The UART interface is a common low-speed communication interface, provides a convenient and cheap communication channel for equipment, and can realize common communication interfaces such as RS232, RS485, RS422 and the like by accessing different interface chips.
The existing scheme I is as follows: by means of a bus sharing mode, the transmission of the transmitted data of the UART interface is simply realized by one and the processing of the data in one to many directions is realized.
The existing scheme is as follows: the single chip microcomputer can generally provide access of 2-4 UART interfaces, and the extension function of the UART interfaces is realized through a plurality of single chip microcomputer chips.
The existing scheme is three: the extension function of the UART interface is realized through a UART chip with a multipath interface, such as the model SC16C 554.
The first existing scheme has the following disadvantages: the bus sharing mode is suitable for one-master multi-slave communication, namely, the master device initiates communication and the slave device responds. At a certain moment, only one end device on the network initiates communication, and no conflict exists between the end devices. However, if a plurality of devices in the network initiate communication at the same time, data will interfere with the network, and normal communication cannot be performed.
The second existing scheme has the following defects: the UART is expanded by adopting a mode of singlechip cascading, and the cascading port possibly occupies a UART interface, so that the number of actually provided UART interfaces is relatively small, the number of the singlechips is relatively large, each singlechip has an independent program, and the product is relatively troublesome to maintain.
The third existing scheme has the following defects: the integrated chip of the special multi-path UART can meet the requirement of the multi-path UART, but the mode can only provide multi-path service interfaces, and because of the bandwidth limitation of the CPU interface, the actual transmission bandwidth of each path of UART is relatively low, and the full-speed communication function can not be realized. Due to the relatively high selling price of such professional chips, the cost of implementation is not low.
Disclosure of Invention
In order to solve the problems in the prior art, the invention provides a system for realizing multi-path UART interface extension through a CPLD, which has the advantages of reasonable design, simple structure, fewer peripheral components and low cost, solves the problem of reliability of one-to-many serial port communication, meets the requirement of serial port extension, and ensures that the full duplex transceiving of each extended serial port is not influenced mutually.
The technical scheme adopted by the invention is as follows:
a system for realizing multi-path UART interface extension through a CPLD is characterized in that: the CPLD module comprises a CPU port UART module, a channel selection and control module and 8 service port UART modules as service UART interfaces, wherein the CPU port UART module is in communication connection with the UART interfaces of the CPU module, the CPU port UART module is connected with the channel selection and control module, the 8 service port UART modules are all connected with the CPU module for performing parameter configuration on the service port UART modules, and the 8 service port UART modules are all connected with the channel selection and control module for selecting the service port UART modules according to requirements to realize corresponding UART interface data communication. The invention realizes the extension function of the UART interface accessed by the CPU module through the CPLD module.
Furthermore, the CPLD module adopts a GW1N-LV4LQ144 chip, and 10 on-chip block memories of 18Kbit for on-chip storage of data are arranged in the CPLD module.
Further, the CPU module is connected with the UART module through an IIC interface.
Further, the parameter setting of the service port UART module includes baud rate of data transmission, data bit width, parity check bit type, and stop bit length.
Further, data communication is carried out between the CPU module and the CPU port UART module by adopting an agreed transmission baud rate, a data bit width, an odd-even check bit type and a stop bit length, wherein the agreed transmission baud rate is greater than the sum of the transmission baud rates of the 8-path service port UART, so that packet loss caused by congestion due to bandwidth can be avoided in the transmission process.
Further, the CPU port UART module includes a CPU port UART receiving module and a CPU port UART transmitting module.
Further, when the service port UART module transmits data, the specific steps are as follows:
s11, the CPU module configures parameters of the corresponding service port UART module according to requirements;
s12, framing by the CPU module according to the frame structure, and sending data to the UART receiving module of the CPU port;
s13, the CPU port UART module analyzes specific data content according to the standard UART interface time sequence requirement and transmits the data content to the channel selection and control module;
s14, the channel selection and control module removes the frame identification, determines the data to be sent to the corresponding service port UART module from the channel number identification byte, and simultaneously checks whether the transmission process has errors;
and S15, after determining that the data is output to the corresponding service port UART module, the channel selection and control module sends the data to the corresponding service port UART module, and the service port UART module sends the data out according to the configured parameters.
Further, when the service port UART module receives data, the specific steps are as follows:
s21, 8 service port UART modules receive data and buffer memory at the same time according to respective configured parameters;
s22, when data exist in the buffer interval, the 8 service port UART modules respectively send request signals to the channel selection and control module, which indicate that the data need to be sent;
s23, the channel selection and control module adopts a mode that the state machine carries out round-robin detection on the request signal, when the state machine is idle and a certain path of service port UART module sends a request, a confirmation signal is given out to inform the module that the data can be sent;
s24, when sending, the channel selection and control module adds frame head identification, channel identification, check and frame tail identification information, and the sent data is sent to the CPU module according to the baud rate of the UART module of the CPU port;
and S25, after the data is sent, the corresponding service port UART module cancels the sending request signal, and the channel selection and control module re-cycles other ports.
Further, the frame format of the data transmission of the CPU module and the CPLD module includes: the 1 st byte is the frame start, and data 0x5E is adopted; the second byte is a channel number and corresponds to a service port 1-8; the middle of the frame is transmitted data content with variable length; the last byte is the sum check of the frame valid data; the last 1 byte is a frame end identifier, and data 0x5E is adopted; if the transmitted data appears 0x5E, the data is decomposed into two data of 0x55 and 0xEE, and if the transmitted data appears 0x55, the data is decomposed into two numbers of 0x55 and 0xE 5. In this way, the same 0x5E as the frame identification does not appear in the data stream, thereby avoiding errors in reception.
Further, when receiving the data of the CPU module and the CPLD module, first locate the frame start identifier 0x5E data, and if receiving 1 piece of 0x5E data, then locate the data according to the frame structure as described above with the data as the start; if a plurality of 0x5E data are received consecutively, the last 10 x5E is used as the frame start identifier; if the receiver receives 0x55 data, the data is restored to the original 0x5E or 0x55 data according to whether the following data is 0xEE or 0xE 5.
The invention has the beneficial effects that: the design is reasonable, the structure is simple, the number of peripheral components is small, the cost is low, the UART interface expansion and management are performed by adopting the CPLD, the problem of one-to-many serial port communication reliability is solved, the requirement of serial port expansion is met, the full duplex transceiving of each expanded serial port is not influenced, namely each serial port is completely independent, the baud rate can be set independently, the speed cannot be reduced, and the number of the required serial ports can be freely customized by selecting the reasonable CPLD according to the resource utilization condition.
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Fig. 1 is a schematic block diagram of the present invention.
Detailed Description
The present invention is further illustrated by the following examples, which are not intended to limit the invention to these embodiments. It will be appreciated by those skilled in the art that the present invention encompasses all alternatives, modifications and equivalents as may be included within the scope of the claims.
In the description of the present invention, it is to be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "clockwise", "counterclockwise", and the like, indicate orientations and positional relationships based on those shown in the drawings, and are used only for convenience of description and simplicity of description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, are not to be considered as limiting the present invention. Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, unless otherwise specified, "a plurality" means two or more unless explicitly defined otherwise.
In the present invention, unless otherwise expressly specified or limited, the terms "mounted," "connected," "secured," and the like are to be construed broadly and can, for example, be fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.
In the present invention, unless otherwise expressly stated or limited, "above" or "below" a first feature means that the first and second features are in direct contact, or that the first and second features are not in direct contact but are in contact with each other via another feature therebetween. Also, the first feature being "on," "above" and "over" the second feature includes the first feature being directly on and obliquely above the second feature, or merely indicating that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature includes the first feature being directly under and obliquely below the second feature, or simply meaning that the first feature is at a lesser elevation than the second feature.
Referring to fig. 1, the present embodiment provides a system for implementing multi-channel UART interface expansion through a CPLD, including a CPU module 101 and a CPLD module 102, where the CPLD module 102 includes a CPU port UART module 103, a channel selection and control module 104, and 8 service port UART modules 105 and 112 as service UART interfaces, the CPU port UART module 103 is in communication connection with a UART interface of the CPU module 101, and the CPU port UART module 103 includes a CPU port UART receiving module and a CPU port UART transmitting module; the CPU port UART module 103 is connected to the channel selection and control module 104, 8 of the service port UART modules 105 and 112 are connected to the CPU module 101 performing parameter configuration thereon through an IIC interface, and 8 of the service port UART modules 105 and 112 are connected to the channel selection and control module 104 selecting them as needed to implement corresponding UART interface data communication. The invention realizes the extension function of the UART interface accessed by the CPU module 101 through the CPLD module 102. Compared with the prior processing mode, the invention can provide the expansion function of the completely independent multi-path UART interface, can conveniently and flexibly expand the function, effectively controls the cost and simplifies the circuit.
The CPU module described in this embodiment adopts a common single chip, and provides 1 path of UART interface for communication, and 1 path of IIC interface for parameter configuration of the service UART port. The CPLD module adopts a GW1N-LV4LQ144 chip, and 10 on-chip block memories of 18Kbit for on-chip storage of data are arranged in the CPLD module.
After the device of this embodiment is powered on or when the parameters of the service port need to be changed, the CPU module 101 configures the parameters of the specific port in the service port UART module 105 and 112 that need to communicate according to the requirements. The configuration content of the parameters comprises the baud rate of data transmission, the data bit width, the parity check bit type, the stop bit length and other information. The working states of the 8 channels are independent, that is, the service port UART module 105 and 112 can work under completely different configuration parameters.
In this embodiment, data communication is performed between the CPU module 101 and the CPU port UART module 103 by using an agreed transmission baud rate, a data bit width, a parity check bit type, and a stop bit length, where the agreed transmission baud rate is greater than the sum of the transmission baud rates of the 8-way service port UART, so as to ensure that packet loss due to congestion caused by bandwidth in a transmission process is avoided.
The frame format for data transmission of the CPU module 101 and the CPLD module 102 in this embodiment includes: the 1 st byte is the frame start, and data 0x5E is adopted; the second byte is a channel number corresponding to a service port 1-8; the middle of the frame is transmitted data content with variable length; the last byte is the sum check of the frame valid data; the last 1 byte is a frame end identifier, and data 0x5E is adopted; if the transmitted data appears 0x5E, the data is decomposed into two data of 0x55 and 0xEE, and if the transmitted data appears 0x55, the data is decomposed into two numbers of 0x55 and 0xE 5. In this way, the same 0x5E as the frame identification does not appear in the data stream, thereby avoiding errors in reception.
In this embodiment, when receiving data from the CPU module 101 and the CPLD module 102, first locate frame start identifier 0x5E data, and if receiving 1 piece of 0x5E data, then locate data according to the frame structure as described above with the data as a start; if a plurality of 0x5E data are received consecutively, the last 10 x5E is used as the frame start identifier; normally, only two consecutive 0x5E data streams are present in the data stream, respectively the end of frame and the start of frame. If the receiver receives 0x55 data, it reverts to the original 0x5E or 0x55 data according to whether the following data is 0xEE or 0xE 5.
In this embodiment, when any one of the service port UART modules 105 and 112 transmits data, the specific steps are as follows:
s11, the CPU module 101 determines which service port UART module is to be used for data transmission, and configures parameters of the corresponding service port UART module according to requirements, and determines the baud rate, data bit width, parity check bit type, stop bit length and other information of data transmission of the service port;
s12, framing by the CPU module 101 according to the frame structure, and sending the data to the UART receiving module of the CPU port;
s13, the CPU port UART module 103 analyzes specific data content according to the standard UART interface timing sequence requirement and transmits the data content to the channel selection and control module 104;
s14, the channel selection and control module 104 removes the frame identification, determines the data to be sent to the corresponding service port UART module from the channel number identification byte, and restores the 0x5E and 0x55 bytes at the same time, and judges whether there is error in the transmission process according to the check;
s15, the channel selection and control module 104 determines that the data is output to the corresponding service port UART module, and then sends the data to the corresponding service port UART module, which sends the data according to the configured parameters.
In this embodiment, when the service port UART module receives data, the 8 service port UART modules 105 and 112 all receive data at the same time because the service port UART modules work independently. The method comprises the following specific steps:
s21, 8 service port UART modules 105 and 112 will receive data at the same time according to the respective configured parameters, and buffer the data by using the block memory cell inside the CPLD;
s22, when there is data in the buffer region, the 8 service port UART modules 105 and 112 respectively send request signals to the channel selection and control module 104, which indicate that there is data to send;
s23, the channel selection and control module 104 adopts the mode that the state machine carries out round-robin detection on the request signal, when the state machine is idle and a certain path of service port UART module sends a request, a confirmation signal is given out to inform the module that data can be sent;
s24, when sending, the channel selection and control module 104 adds the frame head mark, the channel mark, the check and the frame tail mark information, and the sent data is sent to the CPU module 101 according to the baud rate of the CPU port UART module 103;
s25, after the data is sent, the corresponding service port UART module cancels the sending request signal, and the channel selection and control module 104 re-cycles the other ports.
The invention has reasonable design, simple structure, few peripheral components and low cost, adopts CPLD to expand and manage the UART interface, solves the problem of reliability of one-to-many serial port communication, meets the requirement of serial port expansion, and ensures that the full duplex transceiving of each expanded serial port is not influenced mutually, namely each serial port is completely independent, the baud rate can be independently set and the speed cannot be reduced, and the number of the required serial ports can be freely customized by selecting reasonable CPLD according to the resource utilization condition.
Claims (10)
1. A system for realizing multi-path UART interface extension through a CPLD is characterized in that: the CPLD module comprises a CPU port UART module, a channel selection and control module and 8 service port UART modules as service UART interfaces, wherein the CPU port UART module is in communication connection with the UART interfaces of the CPU module, the CPU port UART module is connected with the channel selection and control module, the 8 service port UART modules are all connected with the CPU module for performing parameter configuration on the service port UART modules, and the 8 service port UART modules are all connected with the channel selection and control module for selecting the service port UART modules according to requirements to realize corresponding UART interface data communication.
2. The system according to claim 1, wherein the multi-UART interface extension is implemented by a CPLD, and comprises: the CPLD module adopts a GW1N-LV4LQ144 chip, and 10 on-chip block memories of 18Kbit for on-chip storage of data are arranged in the CPLD module.
3. The system according to claim 1, wherein the multi-UART interface extension is implemented by a CPLD, and comprises: the CPU module is connected with the UART module through the IIC interface.
4. The system according to claim 1, wherein the multi-UART interface extension is implemented by a CPLD, and comprises: the parameter setting of the UART module of the service port comprises baud rate of data transmission, data bit width, parity check bit type and stop bit length.
5. The system according to claim 4, wherein the multi-way UART interface extension is realized by CPLD, and the system comprises: and the CPU module and the CPU port UART module carry out data communication by adopting an agreed transmission baud rate, a data bit width, an odd-even check bit type and a stop bit length, wherein the agreed transmission baud rate is greater than the sum of the transmission baud rates of the 8-path service port UART.
6. The system according to claim 1, wherein the multi-UART interface extension is implemented by a CPLD, and comprises: the CPU port UART module comprises a CPU port UART receiving module and a CPU port UART transmitting module.
7. The system according to any one of claims 1 to 6, wherein the system is configured to implement extension of multi-way UART interface through CPLD, and comprises: when the service port UART module transmits data, the specific steps are as follows:
s11, the CPU module configures parameters of the corresponding service port UART module according to requirements;
s12, framing by the CPU module according to the frame structure, and sending data to the UART receiving module of the CPU port;
s13, the CPU port UART module analyzes specific data content according to the standard UART interface time sequence requirement and transmits the data content to the channel selection and control module;
s14, the channel selection and control module removes the frame identification, determines the data to be sent to the corresponding service port UART module from the channel number identification byte, and simultaneously checks whether the transmission process has errors;
and S15, after determining that the data is output to the corresponding service port UART module, the channel selection and control module sends the data to the corresponding service port UART module, and the service port UART module sends the data out according to the configured parameters.
8. The system according to claim 7, wherein the multi-UART interface extension is implemented by a CPLD, and comprises: when the service port UART module receives data, the specific steps are as follows:
s21, 8 service port UART modules receive data and buffer memory at the same time according to respective configured parameters;
s22, when data exist in the buffer interval, the 8 service port UART modules respectively send request signals to the channel selection and control module, which indicate that the data need to be sent;
s23, the channel selection and control module adopts a mode that the state machine carries out round-robin detection on the request signal, when the state machine is idle and a certain path of service port UART module sends a request, a confirmation signal is given out to inform the module that the data can be sent;
s24, when sending, the channel selection and control module adds frame head identification, channel identification, check and frame tail identification information, and the sent data is sent to the CPU module according to the baud rate of the UART module of the CPU port;
and S25, after the data is sent, the corresponding service port UART module cancels the sending request signal, and the channel selection and control module re-rounds other ports.
9. The system according to claim 8, wherein the multi-UART interface extension is implemented by a CPLD, and comprises: the frame format of the data transmission of the CPU module and the CPLD module comprises: the 1 st byte is the frame start, and data 0x5E is adopted; the second byte is a channel number and corresponds to a service port 1-8; the middle of the frame is transmitted data content with variable length; the last byte is the sum check of the frame valid data; the last 1 byte is a frame end identifier, and data 0x5E is adopted; if the transmitted data appears 0x5E, the data is decomposed into two data of 0x55 and 0xEE, and if the transmitted data appears 0x55, the data is decomposed into two numbers of 0x55 and 0xE 5.
10. The system according to claim 9, wherein the multi-UART interface extension is implemented by a CPLD, and comprises: when receiving the data of the CPU module and the CPLD module, firstly positioning the data of a frame start identifier 0x5E, and if receiving 1 piece of 0x5E data, positioning the data by taking the data as the start according to the frame structure; if a plurality of 0x5E data are received consecutively, the last 10 x5E is used as the frame start identifier; if the receiver receives 0x55 data, it reverts to the original 0x5E or 0x55 data according to whether the following data is 0xEE or 0xE 5.
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| CN115442116A (en) * | 2022-08-31 | 2022-12-06 | 上海容之科技集团有限公司 | Communication method, communication device and storage medium based on serial port communication |
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| CN114490474B (en) | 2024-06-18 |
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Denomination of invention: A system for extending multiple UART interfaces through CPLD Granted publication date: 20240618 Pledgee: China Postal Savings Bank Co.,Ltd. Wuhan Branch Pledgor: WELLTRANS O&E Co.,Ltd. Registration number: Y2024980045318 |