CN114441598A - 3D stacked and packaged integrated circuit chip and failure positioning method and device thereof - Google Patents
3D stacked and packaged integrated circuit chip and failure positioning method and device thereof Download PDFInfo
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Abstract
The embodiment of the invention discloses a 3D stacked and packaged integrated circuit chip and a failure positioning method and a device thereof, wherein the failure positioning method comprises the following steps: determining a plurality of contrast detection layers located at different depths in the standard sample device; after the contrast detection layer is ground each time, phase values corresponding to different detection frequencies of the exposed contrast detection layer in a failure state are detected through a thermal imager; determining a failure positioning curve of each comparison detection layer according to the corresponding relation between the detection frequency and the phase value of each comparison detection layer in a failure state; performing failure positioning on the to-be-detected 3D stacked package integrated circuit chip according to the failure positioning curve of each comparison detection layer; the standard sample device is a 3D stacked package integrated circuit chip to be tested, wherein the 3D stacked package integrated circuit chip to be tested is of the same type and does not fail. The technical scheme provided by the embodiment of the invention realizes the failure positioning of the 3D stacked and packaged integrated circuit chip.
Description
Technical Field
The embodiment of the invention relates to the technical field of semiconductor device detection, in particular to a 3D stacked and packaged integrated circuit chip and a failure positioning method and device thereof.
Background
As semiconductor wafer fabrication moves toward advanced processes, moore's law faces significant challenges. The conventional technologies such as flip chip packaging and stack packaging do not meet the requirements of high performance chips such as a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), a Field Programmable Gate Array (FPGA), and the like, so that the requirement of the 2.5D/3D advanced packaging technology is gradually increased, and the technology becomes one of core technologies for solving the application of high-end products and continuing moore's law.
However, the development of 3D packaging technology also brings new challenges to failure analysis. For example, the location of failures to 3D stacked packaged integrated circuit chips becomes very difficult. The device comprises a plurality of layers, failure information can be effectively measured through an indium gallium arsenic micro-optical microscope, an enhanced thermal imager and other equipment, but the position of the film layer from which the information comes cannot be determined. Therefore, how to perform failure location on the 3D stacked and packaged integrated circuit chip becomes a technical problem to be solved urgently.
Disclosure of Invention
The embodiment of the invention provides a 3D stacked and packaged integrated circuit chip and a failure positioning method and device thereof, which are used for realizing failure positioning of the 3D stacked and packaged integrated circuit chip.
In a first aspect, an embodiment of the present invention provides a failure positioning method for a 3D stacked package integrated circuit chip, including:
determining a plurality of contrast detection layers positioned at different depths in the standard sample device;
after the contrast detection layer is ground each time, phase values corresponding to different detection frequencies of the exposed contrast detection layer in a failure state are detected through a thermal imager;
determining a failure positioning curve of each comparison detection layer according to the corresponding relation between the detection frequency and the phase value of each comparison detection layer in a failure state; the failure positioning curve is a curve comparing the phase value of the detection layer with the change of the detection frequency;
performing failure positioning on the to-be-detected 3D stacked package integrated circuit chip according to the failure positioning curve of each comparison detection layer; the standard sample device is a 3D stacked package integrated circuit chip to be tested, wherein the 3D stacked package integrated circuit chip to be tested is of the same type and does not fail.
Optionally, the determining a plurality of contrast detection layers located at different depths in the standard sample device includes:
determining a plurality of contrast detection layers located at different depths according to the thickness of the standard sample device;
or, determining a plurality of contrast detection layers at different depths according to the functional film layer of the standard sample device.
Optionally, the detecting the phase values corresponding to different detection frequencies of the exposed contrast detection layer in the failure state includes:
and after the surface of the exposed contrast detection layer is subjected to short-circuit failure treatment, detecting the phase value of the exposed contrast detection layer at different detection frequencies from the side, far away from the grinding side, of the standard sample device by a thermal imager.
Optionally, determining a plurality of contrast detection layers at different depths according to the thickness of the standard sample device includes:
dividing the standard sample device into a plurality of layers of alternative contrast layers with equal thickness according to a preset thickness;
and selecting the alternative contrast layer as the contrast detection layer at intervals.
Optionally, the determining a plurality of contrast detection layers located at different depths according to the functional film layer of the standard sample device includes:
determining the functional film layer of the standard sample device as an alternative contrast layer;
and selecting the alternative contrast layer as the contrast detection layer at intervals.
Optionally, the functional film layer of the standard sample device includes: the PCB comprises a welding ball layer, a PCB substrate, a first connecting contact layer, a switching unit, a second connecting contact layer and a top chip which are sequentially stacked; the step of selecting the alternative contrast film layer as the contrast detection layer at intervals comprises:
and selecting a welding ball layer positioned on one side of the PCB substrate far away from the switching unit, a first connecting contact layer between the PCB substrate and the switching unit, and a second connecting contact layer between the switching unit and the top chip as a contrast detection layer.
Optionally, before performing failure location on the to-be-tested 3D stacked package integrated circuit chip according to the failure location curve of each comparison detection layer, the method further includes:
detecting phase values of the to-be-detected 3D stacked package integrated circuit chip under different detection frequencies through a thermal imager; the detection frequency range of the to-be-detected 3D stacked package integrated circuit chip is located in the detection frequency range of the standard sample device;
determining a failure position curve to be detected according to the corresponding relation between the detection frequency and the phase value of the 3D stacked and packaged integrated circuit chip to be detected; the curve of the failure position to be detected is a curve of the phase value of the 3D stacked package integrated circuit chip to be detected changing along with the detection frequency.
Optionally, the performing failure location on the to-be-tested 3D stacked package integrated circuit chip according to the failure location curve of each comparison detection layer includes:
and determining the position of the failure film layer of the 3D stacked and packaged integrated circuit chip to be tested according to the relative distance between the failure positioning curve of each comparison detection layer and the failure position curve to be tested.
In a second aspect, an embodiment of the present invention provides a failure location device for a 3D package on package integrated circuit chip, configured to execute the failure location method for the 3D package on package integrated circuit chip according to any one of the first aspect, including:
the contrast detection layer determining unit is used for determining a plurality of contrast detection layers positioned at different depths in the standard sample device;
the phase value detection unit is used for detecting phase values corresponding to different detection frequencies of the exposed contrast detection layers in a failure state through a thermal imager after each layer of the contrast detection layers is sequentially ground;
the failure positioning curve determining unit is used for determining a failure positioning curve of each comparison detection layer according to the corresponding relation between the detection frequency and the phase value of each comparison detection layer in a failure state; the failure positioning curve is a curve comparing the phase value of the detection layer with the change of the detection frequency;
the failure positioning unit is used for performing failure positioning on the to-be-detected 3D stacked package integrated circuit chip according to the failure positioning curve of each comparison detection layer; the standard sample device is a 3D stacked package integrated circuit chip to be tested, wherein the 3D stacked package integrated circuit chip to be tested is of the same type and does not fail.
In a third aspect, an embodiment of the present invention provides a 3D stack package integrated circuit chip, including multiple stacked film layers, where failure location is performed by using any one of the failure location methods for a 3D stack package integrated circuit chip according to the first aspect.
The embodiment of the invention provides a failure positioning method of a 3D stacked and packaged integrated circuit chip, which comprises the steps of defining a plurality of contrast detection layers positioned at different depths in a standard sample device, grinding the standard sample device, and grinding the set contrast detection layers in sequence; after the contrast detection layer is ground each time, carrying out failure treatment on the contrast detection layer, so that the contrast detection layer can be used for simulating a film layer which is failed in a 3D stacked and packaged integrated circuit chip, and detecting phase values corresponding to different detection frequencies of the contrast detection layer in a failure state through a thermal imager after the failure treatment, thereby determining a failure positioning curve according to the corresponding relation between the detection frequencies and the phase values; each layer of contrast detection layer corresponds to one failure positioning curve; when the 3D stacked packaged integrated circuit chip to be detected is subjected to failure correspondence, the 3D stacked packaged integrated circuit chip to be detected does not need to be ground, and the layer where the failure position is located can be deduced through matching the database, so that the purpose of failure analysis and accurate positioning is achieved.
Drawings
Fig. 1 is a flowchart of a failure location method for a 3D stacked package integrated circuit chip according to an embodiment of the present invention;
FIG. 2 is a flow chart of another method for locating failures of a 3D stacked package integrated circuit chip according to an embodiment of the present invention;
FIG. 3 is a flow chart of another method for locating failures of a 3D stacked package integrated circuit chip according to an embodiment of the present invention;
FIG. 4 is a cross-sectional view of a 3D stacked package integrated circuit chip according to an embodiment of the present invention;
fig. 5 is a graph of a phase value versus a detection frequency for different depth contrast detection layers according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.
The embodiment of the invention provides a failure positioning method of a 3D stacked and packaged integrated circuit chip, fig. 1 is a flow chart of the failure positioning method of the 3D stacked and packaged integrated circuit chip provided by the embodiment of the invention, and referring to fig. 1, the failure positioning method of the 3D stacked and packaged integrated circuit chip comprises the following steps:
and S110, determining a plurality of contrast detection layers positioned at different depths in the standard sample device.
Specifically, the standard sample device is a 3D stacked package integrated circuit chip to be tested, which is of the same type and has no failure. The same type can be understood as that the component film layers of the standard sample device and the corresponding positions of each component film layer are the same as the component film layers of the 3D stacked package integrated circuit chip to be tested and the corresponding positions of each component film layer. Different layers are located at different positions in the device, i.e. corresponding to different depths. The failure of the 3D stacked and packaged integrated circuit chip can be understood as the abnormal condition that a film layer at a certain position in the 3D stacked and packaged integrated circuit chip is short-circuited and the like, so that the normal working condition of the 3D stacked and packaged integrated circuit chip is influenced.
The contrast detection layer can be the functional film layer of constituteing the standard sample device, and for example the standard sample device includes from the welding ball layer, PCB base plate, first connection contact point layer, switching unit, second connection contact point layer and the multilayer top chip constitution of stacking gradually the setting from bottom to top, and the contrast detection layer can be wherein whole or partial rete. Or, after the standard sample device is divided into a plurality of film layers according to the preset thickness, all or part of the film layers can be selected as the contrast detection layer. The smaller the preset thickness is, the more the number of the selected contrast detection layers is, and the more accurate the failure positioning of the to-be-detected 3D stacked package integrated circuit chip is.
And S120, after the contrast detection layer is ground each time, detecting phase values corresponding to different detection frequencies of the exposed contrast detection layer in a failure state through a thermal imager.
In particular, advanced packaging applications, complex interconnection schemes, and the rapid growth of higher performance power devices present unprecedented challenges to fault location and analysis. Defective or underperforming semiconductor devices often exhibit an abnormal distribution of local power loss, resulting in a local temperature rise. For example, after a 3D stacked package integrated circuit chip is short-circuited and fails, a high temperature generated at a short-circuited position becomes a hot spot, and based on the heat transfer property of a material, the high temperature generated at the short-circuited position is transferred to a low temperature position along with time, and then transferred to the outer surface of a device.
A Thermal imager (Infrared Thermal Camera) is a device that converts an image of the temperature distribution of a target to be measured into a visible image by detecting Infrared radiation of the target to be measured, and performing signal processing, photoelectric conversion, and the like using an Infrared Thermal imaging technique. The infrared phase-locked thermal image detection technology is a novel digital nondestructive detection technology, combines an infrared thermal imaging technology with a digital phase-locked technology, adopts an external excitation source with intensity changing according to a sine rule to excite a test piece or a material, changes the temperature caused on the surface of a component according to the sine rule, and changes the surface temperature of the component in a loading frequency oscillation mode, wherein the amplitude and the phase are related to the material characteristics, and when a defect exists in the structure of a sample piece, the amplitude and the phase difference are generated due to the temperature change caused on the surface corresponding to the defect position and the defect-free position of the sample piece. The difference in amplitude and phase is monitored by the enhanced thermal imager so that failure information can be effectively measured, but it is not possible to determine where the film layers from which the information came.
Wherein, the theoretical relationship between the heat transfer phase difference of the Lock-in thermal imaging and the detection frequency is determined based on the following steps:
in the formula (I), the compound is shown in the specification,
in order to detect the frequency of the signal,
in order to be the depth of the film,
is the detected phase value. According to the formula, the phase and frequency relationship of the hot spot at a certain depth has a positive correlation, and the corresponding phase values of the hot spots at different depths are different under the same detection frequency.
Based on this, the depth of the hot spot can be inferred from the phase value and frequency relationship. By defining the contrast detection layer, the contrast detection layer is used as a film layer of the 3D stacked package integrated circuit chip at different critical depths. Taking an unsteamed 3D stacked package integrated circuit chip as a standard sample device, grinding the standard sample device from the bottom of the standard sample device to obtain a first defined contrast detection layer, and then carrying out failure treatment on the contrast detection layer to enable the contrast detection layer to be in a failure state. After the standard sample device is electrified, the contrast detection film layer can generate heat radiation. And detecting phase values corresponding to different detection frequencies of the exposed contrast detection layer in a failure state by a thermal imager. The standard sample device is continued to be ground to a second defined contrast detection layer, and then the contrast detection layer is subjected to a failure treatment so that the contrast detection layer is in a failure state. After the standard sample device is electrified, the contrast detection film layer can generate heat radiation. And detecting phase values corresponding to different detection frequencies of the exposed contrast detection layer in a failure state by a thermal imager. And the rest is repeated until the contrast detection layer defined by the last layer is ground, and the failure treatment and the phase angle detection are carried out on the contrast detection layer.
S130, determining a failure positioning curve of each comparison detection layer according to the corresponding relation between the detection frequency and the phase value of each comparison detection layer in a failure state.
Specifically, when the corresponding relationship between the detection frequency and the phase value of the different contrast detection layers is obtained, the adopted detection frequencies may be the same or different. Preferably, the detection frequencies used when the different layers compare the correspondence between the detection frequencies of the detection layers and the phase values are the same. The phase values are collected, for example, at frequencies of 1Hz, 2Hz, 4Hz and 6Hz, all used. The phase value can be detected by using the same detection frequencies when the to-be-detected 3D stacked package integrated circuit chip is subjected to failure positioning in the subsequent process, so that the positioning result is more accurate.
In addition, when the corresponding relation between the detection frequency and the phase value of different layers of contrast detection layers is obtained, the phase value can be detected for multiple times under the same detection frequency. For example, three phase values are collected at 1Hz, 2Hz, 4Hz and 6 Hz. Then, the average value of the three phase values is used as the phase value under the corresponding detection frequency, so that the detection error can be reduced, and the accuracy of the positioning result is improved. And establishing a rectangular coordinate system by taking the detection frequency as an abscissa and the phase value as an ordinate. And (3) representing a pair of detection frequency and phase value in a rectangular coordinate system as a coordinate point, and connecting the coordinate points to determine a failure positioning curve. Namely, the failure location curve is a curve of the phase value of the contrast detection layer along with the change of the detection frequency. Or after multiple measurements, multiple phase values corresponding to the detection frequency are all represented as coordinate points in a rectangular coordinate system, and then a test result of data convergence is selected as a failure positioning curve, so that the detection error can be reduced, and the accuracy of the positioning result is improved.
And S140, performing failure positioning on the to-be-detected 3D stacked packaged integrated circuit chip according to the failure positioning curve of each comparison detection layer.
Illustratively, table 1 collects phase values for different contrast detections using frequencies 1Hz, 2Hz, 4Hz, and 6 Hz. Referring to table 1, three contrast detection layers at different depths in a standard sample device were identified. Wherein the depth of the first contrast sensing layer in the standard sample device is greater than the depth of the second contrast sensing layer in the standard sample device, wherein the depth of the second contrast sensing layer in the standard sample device is greater than the depth of the third contrast sensing layer in the standard sample device. The phase values collected by the first contrast detection layer at detection frequencies of 1Hz, 2Hz, 4Hz and 6Hz are 124.72, 166.25, 224.89 and 258.22 respectively; the phase values collected by the second contrast detection layer at detection frequencies of 1Hz, 2Hz, 4Hz and 6Hz are 55.71, 78.88, 109.47 and 127.06 respectively; the third contrast detection layer collected phase values of 37.74, 50.26, 71.67, 86.56 at detection frequencies of 1Hz, 2Hz, 4Hz, and 6Hz, respectively. From these data, a failure localization curve of the phase versus detection frequency of the different contrast detection layers can be determined.
When the 3D stacked packaged integrated circuit chip to be detected is subjected to failure correspondence, the 3D stacked packaged integrated circuit chip to be detected which is out of order does not need to be ground, and detection is directly carried out. For example, under the detection frequency of 4Hz, if the detected phase value is 120, it can be determined that the position where the to-be-detected 3D stacked package integrated circuit chip fails is located between the first contrast detection layer and the second contrast detection layer, so that the layer and depth of the failed position can be inferred, and the purpose of accurately positioning failure analysis is achieved. In addition, a failure positioning curve of each comparison detection layer is determined according to the corresponding relation between the detection frequency and the phase value of each comparison detection layer in a failure state, and the curve can determine the phase values which correspond to 3 HZ, 5HZ and the like and are not acquired experimentally. Therefore, for example, the 3D stacked package integrated circuit chip to be tested is detected at a detection frequency of 5Hz, and the obtained phase value can also be compared with a non-experimentally acquired phase value corresponding to 5Hz on the failure positioning curve, so that the layer and depth of the failure position can be inferred, and the purpose of accurately positioning the failure analysis is achieved. Preferably, the detection evaluation rate of the to-be-detected 3D stacked package integrated circuit chip is one or more of the detection evaluation rates of the standard sample device, so that the accuracy of the to-be-detected 3D stacked package integrated circuit chip failure positioning can be improved.
According to the failure positioning method of the 3D stacked and packaged integrated circuit chip, provided by the embodiment of the invention, the set contrast detection layers are sequentially ground by defining a plurality of contrast detection layers positioned at different depths in the standard sample device and grinding the standard sample device; after the contrast detection layer is ground each time, carrying out failure treatment on the contrast detection layer, so that the contrast detection layer can be used for simulating a film layer which is failed in a 3D stacked and packaged integrated circuit chip, and detecting phase values corresponding to different detection frequencies of the contrast detection layer in a failure state through a thermal imager after the failure treatment, thereby determining a failure positioning curve according to the corresponding relation between the detection frequencies and the phase values; each layer of contrast detection layer corresponds to one failure positioning curve; when the 3D stacked packaged integrated circuit chip to be detected is subjected to failure correspondence, the 3D stacked packaged integrated circuit chip to be detected does not need to be ground, and the layer where the failure position is located can be deduced through matching the database, so that the purpose of failure analysis and accurate positioning is achieved.
Fig. 2 is a flowchart of another failure location method for a 3D package on package integrated circuit chip according to an embodiment of the present invention, and referring to fig. 2, the failure location method for a 3D package on package integrated circuit chip includes:
and S210, determining a plurality of contrast detection layers positioned at different depths according to the thickness of the standard sample device.
Specifically, determining a plurality of contrast detection layers at different depths based on the thickness of the standard sample device may include: dividing the standard sample device into a plurality of layers of alternative contrast layers with equal thickness according to the preset thickness; and selecting alternative contrast layers as contrast detection layers at intervals. Illustratively, the standard sample device is divided into six candidate contrast layers from bottom to top, namely a first candidate contrast layer, a second candidate contrast layer, a third candidate contrast layer, a fourth candidate contrast layer, a fifth candidate contrast layer and a sixth candidate contrast layer. And selecting the first, third and fifth alternative contrast layers as contrast detection layers. That is, the first alternative layer is the first contrast detection layer, the third alternative layer is the second contrast detection layer, and the fifth alternative layer is the third contrast detection layer.
When the 3D stacked package integrated circuit chip to be tested is subjected to failure correspondence, for example, under the same detection frequency, the detected phase value is the same as that of the first comparison detection layer, and it is indicated that the position where the 3D stacked package integrated circuit chip to be tested fails is located in the first alternative layer; if the detected phase value is located between the first contrast detection layer and the second contrast detection layer, it indicates that the position of the to-be-detected 3D stacked package integrated circuit chip, where failure occurs, is located in the second alternative layer; if the detected phase value is the same as the phase value detected by the second comparison, the position where the to-be-detected 3D stacked package integrated circuit chip fails is located in the third alternative layer; if the measured phase value is located between the second contrast detection layer and the third contrast detection phase value, the position where the to-be-detected 3D stacked package integrated circuit chip fails is located in the fourth alternative layer; by analogy, the failure location of the whole to-be-detected 3D stacked packaged integrated circuit chip can be carried out by selecting the alternative comparison layer as the comparison detection layer at intervals.
And S220, sequentially grinding each layer of the contrast detection layer, and detecting phase values of the exposed contrast detection layer at different detection frequencies from one side of the standard sample device far away from the grinding side through a thermal imager after short circuit failure treatment is carried out on the surface of the exposed contrast detection layer.
Specifically, the positions of the comparison detection layers with different grinding values are subjected to failure treatment on the surfaces of the comparison detection layers to form failure simulation hot spots. For example, silver paste can be used to make the shorting dots, leaving the contrast detection layer in a failed state. The phase values of the exposed contrast detection layer at different detection frequencies are then detected by a thermal imager from the side of the standard sample device remote from the abraded side.
And S230, determining a failure positioning curve of each comparison detection layer according to the corresponding relation between the detection frequency and the phase value of each comparison detection layer in a failure state.
S240, detecting phase values of the to-be-detected 3D stacked and packaged integrated circuit chip under different detection frequencies through a thermal imager; the detection frequency range of the to-be-detected 3D stacked package integrated circuit chip is located in the detection frequency range of the standard sample device.
And S250, determining a failure position curve to be detected according to the corresponding relation between the detection frequency and the phase value of the 3D stacked and packaged integrated circuit chip to be detected.
Specifically, the curve of the failure position to be detected is a curve of a phase value of the 3D stacked package integrated circuit chip to be detected changing with the detection frequency. The phase values are collected, for example, also using frequencies 1Hz, 2Hz, 4Hz and 6Hz, in order to determine the curve of the position of the failure to be determined. The method for determining the curve of the failure location to be detected may refer to step S130, which is not described herein again. By using the phase values at different detection frequencies to determine the failure position curve to be detected, the phase value at each frequency can be compared with the failure positioning curve, so that the accuracy of failure positioning can be further improved.
S260, determining the position of the failure film layer of the to-be-tested 3D stacked and packaged integrated circuit chip according to the relative distance between the failure positioning curve of each comparison detection layer and the to-be-tested failure position curve.
Specifically, if the failure position curve to be tested almost coincides with one of the failure positioning curves, it can be considered that the position where the 3D stacked package integrated circuit chip to be tested fails is located at the position of the film layer corresponding to the failure positioning curve. If the failure position curve to be tested is located between the two failure positioning curves, it can be determined that the position of the 3D stacked package integrated circuit chip to be tested, where failure occurs, is located between the film layers corresponding to the two failure positioning curves.
And when the failure position curve to be tested is positioned between the two failure positioning curves, if the distance between the failure position curve to be tested and one failure positioning curve is larger than the distance between the failure position curve to be tested and the other failure positioning curve, the position where the failure occurs on the 3D stacked package integrated circuit chip to be tested is determined to be closer to the film layer corresponding to the failure positioning curve with the closer distance.
Fig. 3 is a flowchart of another failure location method for a 3D package on package integrated circuit chip according to an embodiment of the present invention, and referring to fig. 3, the failure location method for a 3D package on package integrated circuit chip includes:
and S310, determining a plurality of contrast detection layers positioned at different depths according to the functional film layers of the standard sample device.
Specifically, determining a plurality of contrast detection layers at different depths based on the functional film layers of the standard sample device may include: determining a functional film layer of the standard sample device as an alternative contrast layer; and selecting the alternative contrast layer as a contrast detection layer at intervals.
Fig. 4 is a cross-sectional view of a 3D stacked package integrated circuit chip according to an embodiment of the present invention, and referring to fig. 4, the functional film layers of the standard sample device include: the PCB comprises a solder ball layer 100, a PCB substrate 200, a first connecting contact layer 300, a switching unit 400, a second connecting contact layer 500 and a top chip 600 which are sequentially stacked. Among other things, solder ball layer 100 may include a plurality of solder balls a (one shown for example), first connection point layer 300 may include a plurality of first connection points B (one shown for example), and second connection point layer 500 may include a plurality of second connection points C (two shown for example). The step of selecting alternative contrast film layers at intervals as the contrast detection layers comprises the following steps: the solder ball layer 100 on the side of the PCB substrate 200 away from the interposer unit 400, the first connection contact layer 300 between the PCB substrate 200 and the interposer unit 400, and the second connection contact layer 500 between the interposer unit 400 and the top chip 600 are selected as the contrast detection layer 10.
Wherein the solder ball layer 100 serves as the first contrast detection layer 11, the first connection contact layer 300 serves as the second contrast detection layer 12, and the second connection contact layer 500 serves as the third contrast detection layer 13. The depth of the first contrast sensing layer 11 in the standard sample device is greater than the depth of the second contrast sensing layer 12 in the standard sample device, and the depth of the second contrast sensing layer 12 in the standard sample device is greater than the depth of the third contrast sensing layer 13 in the standard sample device.
And S320, sequentially grinding each layer of the contrast detection layer, and detecting phase values of the exposed contrast detection layer at different detection frequencies from one side of the standard sample device far away from the grinding side through a thermal imager after the surface of the exposed contrast detection layer is subjected to short circuit failure treatment.
Specifically, the positions of the contrast detection layers 10 are ground to different positions, and failure treatment is performed on the surfaces of the contrast detection layers 10 to form failure simulation hot spots. For example, silver paste may be used to make the shorting dots to render the contrast detection layer 10 in a failure state. The phase values of the exposed contrast detection layer at different detection frequencies are then detected by a thermal imager from the side of the standard sample device remote from the abraded side (the side of the third contrast detection layer 13 remote from the second contrast detection layer 12 in fig. 4).
Choose welding ball layer 100, first connection contact layer 300 and change second connection contact layer 500 and be the mode of contrast detection layer 10, when satisfying the interval and choosing the alternative contrast layer as contrast detection layer 10, because welding ball layer 100 includes a plurality of welding balls A, first connection contact layer 300 and second connection contact layer 500 all include a plurality of metal contact points, can use two welding balls A in silver-colored glue lug connection welding ball layer 100 to form the short-circuit point, use two first connection contact B in silver-colored glue lug connection first connection contact layer 300 to form the short-circuit point, use two second connection contact C in silver-colored glue lug connection second connection contact layer to form the short-circuit point, thereby the mode of going on failure handling to contrast detection layer 10 has been simplified.
S330, determining a failure positioning curve of each comparison detection layer according to the corresponding relation between the detection frequency and the phase value of each comparison detection layer in a failure state.
S340, detecting phase values of the to-be-detected 3D stacked package integrated circuit chip under different detection frequencies through a thermal imager; the detection frequency range of the to-be-detected 3D stacked package integrated circuit chip is located in the detection frequency range of the standard sample device.
And S350, determining a failure position curve to be detected according to the corresponding relation between the detection frequency and the phase value of the 3D stacked and packaged integrated circuit chip to be detected.
And S360, determining the position of the failure film layer of the to-be-tested 3D stacked and packaged integrated circuit chip according to the relative distance between the failure positioning curve of each comparison detection layer and the failure position curve to be tested.
Specifically, fig. 5 is a graph of a relationship between phase values and detection frequencies of different depth contrast detection layers according to an embodiment of the present invention, and referring to fig. 5 and fig. 4, a curve a is a failure positioning curve corresponding to the solder ball layer 100; curve b is a failure positioning curve corresponding to the first connection point layer 300; curve c is the corresponding failure location curve for the second connecting contact layer 500. If the failure position curve to be detected obtained after detecting the 3D stacked and packaged integrated circuit chip to be detected almost coincides with one of the failure positioning curves, it can be considered that the failure position of the 3D stacked and packaged integrated circuit chip to be detected is located at the position of the film layer corresponding to the failure positioning curve. If the failure position curve to be tested is located between the two failure positioning curves, it can be determined that the position of the 3D stacked package integrated circuit chip to be tested, where failure occurs, is located between the film layers corresponding to the two failure positioning curves. For example, if the curve of the failure location to be tested is located between the curve a and the curve b, it can be determined that the location of the failure of the 3D stacked package integrated circuit chip to be tested is located on the PCB substrate 200.
In summary, according to the technical scheme provided by the embodiment of the invention, on the basis of the heat transfer property of the material, the hot spot depth can be deduced according to the phase/frequency relation curve graph. Different critical locations of the package (e.g., solder ball layer 100, PCB substrate 200, first connection contact layer 300, interposer unit 400, second connection contact layer 500, and top chip 600, wherein the top chip 600 may also include multiple layers of chips) can be defined, the good samples can be sampled, polished to different locations, and then Phase/frequency curves can be obtained at the depth location by measuring the Phase (Phase) values at different frequencies using a failure simulation hot spot (e.g., a short-circuit spot made of silver paste). Then, in the actual failure analysis process, the failure position can be determined by firstly taking the good piece to establish a database, testing the failure sample at different frequencies, selecting the test result of data convergence, and then obtaining the established phase/frequency relation curve chart of different positions, so as to achieve the accurate positioning of the failure layer and the position. It should be noted that, for different products, different phase/frequency relation graphs need to be established respectively for use in the actual failure analysis.
The embodiment of the invention also provides a failure positioning device of the 3D stacked and packaged integrated circuit chip, which is used for executing the failure positioning method of the 3D stacked and packaged integrated circuit chip in any embodiment, and comprises the following steps:
the contrast detection layer determining unit is used for determining a plurality of contrast detection layers positioned at different depths in the standard sample device;
the phase value detection unit is used for detecting phase values corresponding to different detection frequencies of the exposed contrast detection layers in a failure state after each layer of the contrast detection layers is sequentially ground;
the failure positioning curve determining unit is used for determining a failure positioning curve of each comparison detection layer according to the corresponding relation between the detection frequency and the phase value of each comparison detection layer in a failure state;
the failure positioning unit is used for performing failure positioning on the to-be-detected 3D stacked package integrated circuit chip according to the failure positioning curve of each comparison detection layer; the standard sample device is a 3D stacked package integrated circuit chip to be tested, wherein the 3D stacked package integrated circuit chip to be tested is of the same type and does not fail.
Referring to fig. 4, an embodiment of the present invention further provides a 3D stacked package integrated circuit chip, which includes multiple stacked film layers, and the failure location is performed by using the failure location method for a 3D stacked package integrated circuit chip according to any of the embodiments described above. Have the same technical effect and are not described in detail herein.
It is to be noted that the foregoing description is only exemplary of the invention and that the principles of the technology may be employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.
Claims (10)
1. A failure positioning method for a 3D stacked package integrated circuit chip is characterized by comprising the following steps:
determining a plurality of contrast detection layers located at different depths in the standard sample device;
after the contrast detection layer is ground each time, phase values corresponding to different detection frequencies of the exposed contrast detection layer in a failure state are detected through a thermal imager;
determining a failure positioning curve of each comparison detection layer according to the corresponding relation between the detection frequency and the phase value of each comparison detection layer in a failure state; the failure positioning curve is a curve comparing the phase value of the detection layer with the change of the detection frequency;
performing failure positioning on the to-be-detected 3D stacked package integrated circuit chip according to the failure positioning curve of each comparison detection layer; the standard sample device is a 3D stacked package integrated circuit chip to be tested, wherein the 3D stacked package integrated circuit chip to be tested is of the same type and does not fail.
2. The method of claim 1, wherein determining a plurality of contrast detection layers at different depths in a standard sample device comprises:
determining a plurality of contrast detection layers located at different depths according to the thickness of the standard sample device;
or, a plurality of contrast detection layers positioned at different depths are determined according to the functional film layer of the standard sample device.
3. The method of claim 1, wherein the detecting phase values corresponding to different detection frequencies of the exposed contrast detection layer in a failure state comprises:
and after the surface of the exposed contrast detection layer is subjected to short-circuit failure treatment, detecting the phase value of the exposed contrast detection layer at different detection frequencies from the side, far away from the grinding side, of the standard sample device by a thermal imager.
4. The method of claim 2, wherein determining a plurality of contrast detection layers at different depths according to the thickness of the standard sample device comprises:
dividing the standard sample device into a plurality of layers of alternative contrast layers with equal thickness according to a preset thickness;
and selecting the alternative contrast layer as the contrast detection layer at intervals.
5. The method of claim 2, wherein determining a plurality of contrast detection layers at different depths from the functional film layers of the standard sample device comprises:
determining the functional film layer of the standard sample device as an alternative contrast layer;
and selecting the alternative contrast layer as the contrast detection layer at intervals.
6. The method of claim 5, wherein the functional film layers of the standard sample device comprise: the PCB comprises a welding ball layer, a PCB substrate, a first connecting contact layer, a switching unit, a second connecting contact layer and a top chip which are sequentially stacked; the step of selecting the alternative contrast film layer as the contrast detection layer at intervals comprises:
and selecting a welding ball layer positioned on one side of the PCB substrate far away from the switching unit, a first connecting contact layer between the PCB substrate and the switching unit, and a second connecting contact layer between the switching unit and the top chip as a contrast detection layer.
7. The method of claim 1, wherein before performing failure location on the 3D stacked package integrated circuit chip to be tested according to the failure location curve of each comparison detection layer, the method further comprises:
detecting phase values of the to-be-detected 3D stacked package integrated circuit chip under different detection frequencies through a thermal imager; the detection frequency range of the to-be-detected 3D stacked package integrated circuit chip is located in the detection frequency range of the standard sample device;
determining a failure position curve to be detected according to the corresponding relation between the detection frequency and the phase value of the 3D stacked and packaged integrated circuit chip to be detected; the curve of the failure position to be detected is a curve of the phase value of the 3D stacked package integrated circuit chip to be detected changing along with the detection frequency.
8. The method of claim 7, wherein the performing the failure location on the 3D stacked package integrated circuit chip to be tested according to the failure location curve of each comparison detection layer comprises:
and determining the position of the failure film layer of the 3D stacked and packaged integrated circuit chip to be tested according to the relative distance between the failure positioning curve of each comparison detection layer and the failure position curve to be tested.
9. A failure location device of a 3D package on package integrated circuit chip, for performing the failure location method of the 3D package on package integrated circuit chip as claimed in any one of claims 1 to 8, comprising:
the contrast detection layer determining unit is used for determining a plurality of contrast detection layers positioned at different depths in the standard sample device;
the phase value detection unit is used for detecting phase values corresponding to different detection frequencies of the exposed contrast detection layers in a failure state through a thermal imager after each layer of the contrast detection layers is sequentially ground;
the failure positioning curve determining unit is used for determining a failure positioning curve of each comparison detection layer according to the corresponding relation between the detection frequency and the phase value of each comparison detection layer in a failure state; the failure positioning curve is a curve comparing the phase value of the detection layer with the change of the detection frequency;
the failure positioning unit is used for performing failure positioning on the to-be-detected 3D stacked package integrated circuit chip according to the failure positioning curve of each comparison detection layer; the standard sample device is a 3D stacked package integrated circuit chip to be tested, wherein the 3D stacked package integrated circuit chip to be tested is of the same type and does not fail.
10. A 3D package on package integrated circuit chip, comprising a plurality of stacked film layers, wherein the failure location is performed by the failure location method of the 3D package on package integrated circuit chip according to any one of claims 1 to 8.
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