CN114446258B

CN114446258B - Display panel and display device

Info

Publication number: CN114446258B
Application number: CN202210195745.2A
Authority: CN
Inventors: 饶兵
Original assignee: TCL China Star Optoelectronics Technology Co Ltd
Current assignee: TCL China Star Optoelectronics Technology Co Ltd
Priority date: 2022-03-01
Filing date: 2022-03-01
Publication date: 2023-03-31
Anticipated expiration: 2042-03-01
Also published as: CN114446258A

Abstract

The application discloses display panel and display device, this display panel includes at least one source driver, at least one grid driver is with time schedule controller, through the source feedback signal that corresponds, grid feedback signal, time schedule controller can detect every source driver in real time, whether every grid driver is in normal operating condition, and then can distinguish whether the pixel in the display panel can carry out normal display, can determine target display area with this moment of controller, then obtain target frame image through compressing initial frame image, at this moment, target frame image can present on target display area completely and can not appear the unable technical problem who shows of partial picture fragment.

Description

Display panel and display device

Technical Field

The application relates to the technical field of display, in particular to a display panel and a display device.

Background

In the display panel, due to lack of a proper feedback path between the Timing Controller (TCON) and the Source Driver (Source Driver) and the Gate Driver (Gate Driver), the timing controller cannot acquire the state information of the Source Driver and the Gate Driver, and thus cannot determine whether the Source Driver and the Gate Driver are still in a normal state.

Therefore, when an abnormal state occurs, the corresponding pixel cannot be normally displayed, and because the timing controller cannot discriminate whether the corresponding pixel can be normally displayed, the abnormal pixel which cannot be normally displayed loses a picture segment, thereby causing incomplete picture display.

Disclosure of Invention

The application provides a display panel and a display device, which are used for relieving the technical problem of incomplete picture display in an abnormal state.

In a first aspect, the present application provides a display panel, which includes at least one source driver, at least one gate driver, and a timing controller, wherein each source driver outputs a source feedback signal, and the source feedback signal is used to characterize whether the source driver is normal; each grid driver outputs a grid feedback signal, and the grid feedback signal is used for representing whether the grid driver is normal or not; the time schedule controller is electrically connected with the source driver and the grid driver and is used for obtaining a target display area of the display panel according to at least one source electrode feedback signal and at least one grid electrode feedback signal, determining the ratio of the target display area to the initial display area of the display panel as the compression ratio of the initial frame image data, processing the initial frame image data according to the compression ratio to obtain and output the target frame image data to the source driver, and the initial display area is the display area of the display panel under the condition that at least one source electrode driver and at least one grid electrode driver are normal.

In some embodiments, the timing controller includes a state signal receiver, an image processing circuit, and a data transmitter, wherein the state signal receiver is electrically connected to the at least one source driver and the at least one gate driver, and is configured to output corresponding state feedback information according to the received source feedback signals and gate feedback signals; the image processing circuit is electrically connected with the output end of the state signal receiver and used for determining a compression rate according to the received state feedback information and processing the initial frame image data according to the compression rate to obtain target frame image data; the input end of the data emitter is electrically connected with the image processing circuit, and the output end of the data emitter is electrically connected with at least one source electrode driver and used for outputting data signals to the corresponding source electrode driver according to the target frame image data.

In some embodiments, each source driver includes a data clock recovery circuit and a source failure determination circuit, and an input terminal of the data clock recovery circuit is electrically connected to the timing controller and configured to output a corresponding lock signal according to an accessed data signal; the source fault judging circuit is electrically connected with the data clock recovery circuit and the time schedule controller and is used for outputting corresponding source feedback signals according to the accessed locking signals.

In some embodiments, the source fault determining circuit includes a first transistor and a first resistor, a gate of the first transistor is electrically connected to the data clock recovery circuit to receive the access lock signal, one of a source/drain of the first transistor is grounded, and the other of the source/drain of the first transistor is electrically connected to the timing controller to output a source feedback signal to the timing controller; one end of the first resistor is electrically connected with the other of the source electrode and the drain electrode of the first transistor, and the other end of the first resistor is connected with a power positive signal.

In some embodiments, each gate driver includes a shift register, a gate signal output circuit, and a gate failure determination circuit, wherein an input terminal of the shift register is electrically connected to the timing controller for outputting a corresponding output enable signal; the input end of the grid signal output circuit is electrically connected with the shift register, and each output end of the grid signal output circuit is used for correspondingly outputting at least one scanning signal; the grid fault judging circuit is electrically connected with the shift register and the grid signal output circuit and used for outputting corresponding grid feedback signals according to the received output enabling signals and the at least one scanning signal.

In some embodiments, the gate fault determining circuit includes a nor circuit and an xor circuit, or the nor circuit is electrically connected to each output terminal of the gate signal output circuit, and is configured to perform a nor operation on at least one scan signal to generate a corresponding GP signal; the exclusive-or circuit is electrically connected with the shift register or the nor circuit through the time sequence controller and is used for generating a corresponding grid feedback signal according to an exclusive-or operation result of the output enable signal and the GP signal.

In some embodiments, the nor circuit includes a second resistor and a plurality of second transistors, and one end of the second resistor is connected to the positive power signal; one of the source/drain electrodes of the second transistors is electrically connected with the other end of the second resistor, the other of the source/drain electrodes of the second transistors is grounded, and the grid electrode of each second transistor is connected with a scanning signal.

In some embodiments, when the output enable signal is at a low potential, at least one scan signal is at a low potential; when the output enable signal is at a high potential, the grid signal output circuit normally outputs at least one scanning signal.

In some embodiments, the gate driver is normal when the output enable signal is opposite in phase to the GP signal.

In a second aspect, the present application provides a display device, which includes the display panel in at least one of the above embodiments, wherein the timing controller has a first input terminal for receiving a video signal and a second input terminal for receiving a control signal.

The application provides a display panel and display device, through the source electrode feedback signal that corresponds, grid feedback signal, time schedule controller can detect every source electrode driver in real time, whether every grid electrode driver is in normal operating condition, and then can distinguish whether the pixel in the display panel can normally show, with this moment of controller can determine target display area, then obtain target frame image through compressing initial frame image after, at this moment, target frame image can present on target display area completely and can not appear the unable technical problem that shows of partial picture fragment.

Drawings

The technical solution and other advantages of the present application will become apparent from the detailed description of the embodiments of the present application with reference to the accompanying drawings.

Fig. 1 is a schematic structural diagram of a display panel according to an embodiment of the present disclosure.

Fig. 2 is a schematic view of a second structure of a display panel according to an embodiment of the present disclosure.

Fig. 3 is a schematic structural diagram of a third display panel according to an embodiment of the present disclosure.

Fig. 4 is a partial timing diagram of a display panel according to an embodiment of the present disclosure.

Fig. 5 is a schematic view of a working flow of a display panel according to an embodiment of the present application.

Fig. 6 is a schematic view of an application scenario of a display panel according to an embodiment of the present application.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

In view of the above-mentioned technical problem that the display of the image is incomplete when the source drivers 200 and the gate drivers 300 are in the abnormal state, the present embodiment provides a display panel, please refer to fig. 1 to 6, as shown in fig. 1 to 4, the display panel includes at least one source driver 200, at least one gate driver 300 and a timing controller 100, each source driver 200 outputs a source feedback signal FBS, and the source feedback signal FBS is used for indicating whether the source driver 200 is normal or not; each gate driver 300 outputs a gate feedback signal FBG, and the gate feedback signal FBG is used for indicating whether the gate driver 300 is normal; the timing controller 100 is electrically connected to the source driver 200 and the gate driver 300, and configured to obtain a target display area of the display panel according to at least one source feedback signal FBS and at least one gate feedback signal FBG, determine that a ratio of the target display area to an initial display area of the display panel is a compression ratio of initial frame image data, process the initial frame image data according to the compression ratio to obtain and output the target frame image data to the source driver 200, and the initial display area is a display area of the display panel when the at least one source driver 200 and the at least one gate driver 300 are normal.

It can be understood that, in the display panel provided in this embodiment, through the corresponding source feedback signal FBS and the corresponding gate feedback signal FBG, the timing controller 100 can detect whether each source driver 200 and each gate driver 300 are in a normal operating state in real time, and further can discriminate whether pixels in the display panel can perform normal display, so that the timing controller 100 can determine a target display area at this time, and then obtain a target frame image by compressing the initial frame image, at this time, the target frame image can be completely presented on the target display area without the technical problem that a part of the frame segment cannot be displayed.

The initial frame image data may generate a corresponding initial frame image having the initial display area. The target frame image data may generate a corresponding target frame image having a display area equal to the target display area.

In this embodiment, since the state monitoring of whether all the source drivers 200 and all the gate drivers 300 of the display panel are normal or not is performed, the source drivers 200 and/or the gate drivers 300 in the normal state or the abnormal state can be determined in real time according to the corresponding source feedback signals FBS and gate feedback signals FBG, and thus, the display area can be determined according to the continuous and maximum number of the source drivers 200 and/or the gate drivers 300 in the normal state. For example, as shown in fig. 2, all the source drivers 200 and all the gate drivers 300 of the display panel are in a normal state, in which case the target display area is an initial display area, such as the display area AA1 shown in fig. 2. For another example, as shown in fig. 3, the first gate driver 300 and the fourth gate driver 300 from top to bottom are in an abnormal state, and the first source driver 200 and the sixth source driver 200 from left to right are in an abnormal state, at this time, the consecutive and maximum number of the source drivers 200 and/or the gate drivers 300 in the normal state are the second gate driver 300, the third gate driver 300, and the second source driver 200 to the fifth source driver 200 from left to right, and correspondingly, the orthogonal area corresponding to the consecutive and maximum number of the source drivers 200 and/or the gate drivers 300 in the normal state is a target display area, for example, the display area AA2 shown in fig. 3.

If only the source driver 200 or the gate driver 300 is abnormal, only the continuous display area needs to be determined, and the orthogonal display area does not need to be determined.

It is understood that, after the source driver 200 receives the target frame image data, the target frame image data may be displayed on the target display area as described above. Since the initial display area is the display area of the display panel under the condition that the at least one source driver 200 and the at least one gate driver 300 are normal, the target display area is always smaller than or equal to the initial display area, and thus, the compression ratio in this embodiment may be greater than or equal to zero and smaller than or equal to 1.

When the compression rate is zero, it indicates that at least one source driver 200 and/or at least one gate driver 300 in the display panel are abnormal, and at this time, the display panel has no area available for normal display.

It should be noted that the normal or normal state indicates that all output channels of one source driver 200 can normally output corresponding data signals or all output channels of one gate driver 300 can normally output corresponding scan signals when turned on. The above-mentioned abnormal or abnormal state indicates that at least one output channel of one source driver 200 cannot normally output a corresponding data signal or at least one output channel of one gate driver 300 cannot normally output a corresponding scan signal.

When the source feedback signal FBS is at a high potential, it represents that the corresponding source driver 200 is normal, and when the source feedback signal FBS is at a low potential, it represents that the corresponding source driver 200 is abnormal. When the gate feedback signal FBG is at a high potential, it characterizes that the corresponding gate driver 300 is normal, and when the gate feedback signal FBG is at a low potential, it characterizes that the corresponding gate driver 300 is abnormal.

In one embodiment, the timing controller 100 includes a status signal receiver 110, an image processing circuit 120 and a data transmitter 130, wherein the status signal receiver 110 is electrically connected to at least one source driver 200 and at least one gate driver 300, and is configured to output corresponding status feedback information according to each received source feedback signal FBS and each received gate feedback signal FBG; the image processing circuit 120 is electrically connected to the output terminal of the status signal receiver 110, and is configured to determine a compression rate according to the received status feedback information, and process the initial frame image data according to the compression rate to obtain target frame image data; the input end of the data transmitter 130 is electrically connected to the image processing circuit 120, and the output end of the data transmitter 130 is electrically connected to at least one source driver 200, for outputting a data signal to the corresponding source driver 200 according to the target frame image data.

In one embodiment, the timing controller 100 further includes a control signal circuit 140 and a timing transmitter 150, wherein the control signal circuit 140 is electrically connected to the image processing circuit 120 and the output terminal of the status signal receiver 110; the input terminal of the timing transmitter 150 is electrically connected to the control signal circuit 140, and the output terminal of the timing transmitter 150 is electrically connected to at least one gate driver 300, so as to provide the timing signal to the corresponding gate driver 300.

In one embodiment, each source driver 200 includes a data clock recovery circuit 210 and a source failure determination circuit 220, wherein an input terminal of the data clock recovery circuit 210 is electrically connected to the timing controller 100, and is configured to output a corresponding lock signal according to an accessed data signal; the source fault determining circuit 220 is electrically connected to the data clock recovery circuit 210 and the timing controller 100, and is configured to output a corresponding source feedback signal FBS according to the accessed lock signal.

It should be noted that the Data Clock Recovery (CDR) circuit is used to recover a Clock signal embedded in a Data signal transmitted from the timing controller 100.

In one embodiment, each of the source drivers 200 may further include a data output circuit 230, an input terminal of the data output circuit 230 is electrically connected to another output terminal of the data clock recovery circuit 210, and each output terminal of the data output circuit 230 is used for outputting the corresponding data signal D1 to the data signal Dm.

In one embodiment, the source failure determining circuit 220 includes a first transistor QS1 and a first resistor R1, a gate of the first transistor QS1 is electrically connected to the data clock recovery circuit 210 to receive a LOCK (LOCK) signal, one of a source/drain of the first transistor QS1 is grounded, and the other of the source/drain of the first transistor QS1 is electrically connected to the timing controller 100 to output a source feedback signal FBS to the timing controller 100; one end of the first resistor R1 is electrically connected to the other of the source/drain of the first transistor QS1, and the other end of the first resistor R1 is connected to the positive power supply signal VDD.

It should be noted that the latch signal of the embodiment can pull up the source feedback signal FBS to a high level through the source failure determination circuit 220 when the source driver 200 is normal, or pull down the source feedback signal FBS to a low level through the source failure determination circuit 220 when the source driver 200 is abnormal.

In one embodiment, each gate driver 300 includes a shift register 310, a gate signal output circuit 320, and a gate failure determination circuit 330, wherein an input terminal of the shift register 310 is electrically connected to the timing controller 100 for outputting a corresponding output enable signal (OE); the input end of the gate signal output circuit 320 is electrically connected to the shift register 310, and each output end of the gate signal output circuit 320 is used for correspondingly outputting at least one scanning signal; the gate failure determining circuit 330 is electrically connected to the shift register 310 and the gate signal output circuit 320, and is configured to output a corresponding gate feedback signal FBG according to the received output enable signal and the at least one scan signal.

It should be noted that, when the output enable signal is at the low potential, at least one scan signal is at the low potential; when the output enable signal is at a high level, the gate signal output circuit 320 normally outputs at least one scan signal.

In one embodiment, the gate fault determining circuit 330 includes a nor circuit 331 and an xor circuit 332, where the nor circuit 331 is electrically connected to each output terminal of the gate signal output circuit 320, and is configured to perform a nor operation on at least one scan signal to generate a corresponding GP signal; the xor circuit 332 is electrically connected to the shift register 310 or the nor circuit 331 and the timing controller 100, and is configured to generate the corresponding gate feedback signal FBG according to an xor operation result of the output enable signal and the GP signal.

It can be understood that, in this embodiment, the nor circuit 331 can monitor whether all the output channels of the same gate driver 300 are normal or not, that is, whether each output channel is shorted to the ground/zero potential or the positive power signal VDD, or whether the scan line connected to the corresponding output channel is shorted to the zero potential or the positive power signal VDD.

The exclusive-or circuit 332 may be a component having an exclusive-or function, such as an exclusive-or logic gate.

In one embodiment, the nor circuit 331 includes a second resistor R2 and a plurality of second transistors, for example, n transistors, such as a transistor Q1, a transistor Q2.. And a transistor Qn, wherein one end of the second resistor R2 is connected to the power positive signal VDD; one of the source/drain electrodes of the second transistors is electrically connected with the other end of the second resistor R2, the other of the source/drain electrodes of the second transistors is grounded, and the grid electrode of each second transistor is connected with a scanning signal.

It is understood that, in the present embodiment, the number of the second transistors corresponds to the number of output channels corresponding to one gate driver 300. When all the scan signals output from one gate driver 300 are low, the GP signal output from the nor circuit 331 is high; when at least one of all the scan signals output from one gate driver 300 is high, the GP signal output from the nor circuit 331 is low.

In one embodiment, the gate driver 300 is normal when the output enable signal is opposite in phase to the GP signal.

In summary, as shown in fig. 4, under the control of the output enable signal (OE), one of the gate drivers 300 outputs the scan signals G1 to Gn, the phases of the scan signals G1 to Gn lag behind one another, and the GP signal (GP) is at a high potential when the scan signals G1 to Gn are at a low potential; when at least one of the scan signals G1 to Gn is at a high level, the GP signal is at a low level. Here, the time period t1 is a time interval between adjacent pulses of two adjacent scan signals, for example, a time interval between a falling edge of a first pulse of the scan signal G1 and a rising edge of a first pulse of the scan signal G2. The time period t2 is the time at which the pulses of the scanning signals output by the other gate drivers 300 in at least one gate driver 300 are located, and it can be understood that the phases of the scanning signals output by the other gate drivers 300 sequentially lag behind the phase of the scanning signal Gn.

It should be noted that, when the phases of the output enable signal and the GP signal are the same, it indicates that a short circuit phenomenon occurs between at least one output channel of one of the gate drivers 300 and the zero potential or the high potential, and accordingly, the one of the gate drivers 300 is abnormal or in an abnormal state.

As shown in fig. 5, the operation process of the display panel may be that when the timing controller 100 detects that all the gate drivers 300 and all the source drivers 200 are in a normal state, the timing controller 100 operates normally, and the image display is normal.

If the timing controller 100 detects that all the gate drivers 300 are in the normal state and all the source drivers 200 are not in the normal state, the continuous, maximum number of the source drivers 200 in the normal state are determined, and the timing controller 100 determines the maximum (effective) display area according to the gate drivers 300 and the source drivers 200 that are still in the normal state and compresses the image with an appropriate compression rate.

If the timing controller 100 detects that all the source drivers 200 are in the normal state and all the gate drivers 300 are not in the normal state, the continuous, maximum number of gate drivers 300 in the normal state are determined, and the timing controller 100 determines the maximum (effective) display area according to the gate drivers 300 and the source drivers 200 that are still in the normal state and compresses the image with an appropriate compression rate.

If the timing controller 100 detects that all the source drivers 200 and all the gate drivers 300 are not in the normal state, the sequential, maximum number of the source drivers 200 and the gate drivers 300 that are in the normal state are determined, and the timing controller 100 determines the maximum (effective) display area according to the gate drivers 300 and the source drivers 200 that are still in the normal state, and compresses the image with an appropriate compression rate.

In one embodiment, this implementation provides an application scenario of the display panel, and based on the above embodiment, the timing controller 100 may discriminate the display priority of each frame image, and when it is detected that at least one of the at least one gate driver 300 and the at least one source driver 200 is in an abnormal state, preferentially output an important frame image with the highest display priority, for example, as shown in fig. 6, the important frame image carries "quakeproof and disaster reduction, hand safety |)! "important frame image of information, and then the upper graph in fig. 6 is processed into the lower graph in fig. 6 at an appropriate compression rate, and at this time, the important frame image can be preferentially and completely displayed in the target display area.

In one embodiment, the present embodiment provides a display device, which includes the display panel in at least one embodiment, the timing controller 100 has a first input terminal for receiving video (RGB) signals, and a second input terminal for receiving control (Ctrl) signals.

It can be understood that, in the display apparatus provided in this embodiment, through the corresponding source feedback signal FBS and the corresponding gate feedback signal FBG, the timing controller 100 can detect whether each source driver 200 and each gate driver 300 are in a normal operating state in real time, and further can discriminate whether the pixels in the display panel can perform normal display, so that the timing controller 100 can determine a target display area at this time, and then obtain a target frame image by compressing the initial frame image, at this time, the target frame image can be completely presented on the target display area without the technical problem that a part of the frame segment cannot be displayed.

It should be noted that the display panel in the above embodiment may be a liquid crystal display panel.

In the foregoing embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to the related descriptions of other embodiments.

The display panel and the display device provided by the embodiment of the present application are described in detail above, and a specific example is applied in the description to explain the principle and the implementation of the present application, and the description of the embodiment is only used to help understanding the technical solution and the core idea of the present application; those of ordinary skill in the art will understand that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications or substitutions do not depart from the spirit and scope of the present disclosure as defined by the appended claims.

Claims

1. A display panel, comprising:

each source driver outputs a source feedback signal, and the source feedback signal is used for representing whether the source driver is normal or not;

each grid driver outputs a grid feedback signal, and the grid feedback signal is used for representing whether the grid driver is normal or not; and

the time schedule controller is electrically connected with the source driver and the gate driver and is used for obtaining a target display area of the display panel according to at least one source feedback signal and at least one gate feedback signal, determining the ratio of the target display area to the initial display area of the display panel as the compression ratio of initial frame image data, processing the initial frame image data according to the compression ratio to obtain and output target frame image data to the source driver, wherein the initial display area is the display area of the display panel under the condition that the at least one source driver and the at least one gate driver are normal;

wherein each of the source drivers includes:

the input end of the data clock recovery circuit is electrically connected with the time schedule controller and is used for outputting a corresponding lock signal according to an accessed data signal; and

the source fault judging circuit is electrically connected with the data clock recovery circuit and the time schedule controller and is used for outputting the corresponding source feedback signal according to the accessed locking signal;

wherein, the source fault judging circuit includes:

a first transistor, a gate of which is electrically connected to the data clock recovery circuit to access the latch signal, one of a source/drain of which is grounded, and the other of the source/drain of which is electrically connected to the timing controller to output the source feedback signal to the timing controller; and

one end of the first resistor is electrically connected with the other one of the source electrode and the drain electrode of the first transistor, and the other end of the first resistor is connected with a power positive signal.

2. The display panel according to claim 1, wherein the timing controller comprises:

the state signal receiver is electrically connected with the at least one source driver and the at least one grid driver and is used for outputting corresponding state feedback information according to the received each source feedback signal and each grid feedback signal;

the image processing circuit is electrically connected with the output end of the state signal receiver and used for determining the compression ratio according to the received state feedback information and processing the initial frame image data according to the compression ratio to obtain the target frame image data; and

and the input end of the data emitter is electrically connected with the image processing circuit, and the output end of the data emitter is electrically connected with the at least one source electrode driver and used for outputting a data signal to the corresponding source electrode driver according to the target frame image data.

3. The display panel according to claim 1, wherein each of the gate drivers comprises:

the input end of the shift register is electrically connected with the time sequence controller and is used for outputting a corresponding output enable signal;

the input end of the grid signal output circuit is electrically connected with the shift register, and each output end of the grid signal output circuit is used for correspondingly outputting at least one scanning signal;

and the grid fault judging circuit is electrically connected with the shift register and the grid signal output circuit and is used for outputting the corresponding grid feedback signal according to the received output enabling signal and the at least one scanning signal.

4. The display panel according to claim 3, wherein the gate failure determination circuit comprises:

the NOR circuit is electrically connected with each output end of the grid signal output circuit and is used for carrying out NOR operation on the at least one scanning signal to generate a corresponding GP signal;

and the exclusive-or circuit is electrically connected with the shift register, the NOR circuit and the time schedule controller and is used for generating the corresponding grid feedback signal according to the exclusive-or operation result of the output enable signal and the GP signal.

5. The display panel according to claim 4, wherein the NOR circuit comprises:

one end of the second resistor is connected with a power positive signal;

one of source/drain electrodes of the second transistors is electrically connected with the other end of the second resistor, the other of the source/drain electrodes of the second transistors is grounded, and a grid electrode of each second transistor is connected with one scanning signal.

6. The display panel according to claim 3, wherein when the output enable signal is at a low potential, the at least one scan signal is at a low potential; when the output enable signal is at a high potential, the gate signal output circuit normally outputs the at least one scan signal.

7. The display panel of claim 4, wherein the gate driver is normal when the output enable signal is opposite in phase to the GP signal.

8. A display device comprising a display panel as claimed in any one of claims 1 to 7, the timing controller having a first input for receiving a video signal, a second input for receiving a control signal.