CN114422597A - FPGA-based data frame timing forwarding method and device, FPGA and data exchange equipment - Google Patents
FPGA-based data frame timing forwarding method and device, FPGA and data exchange equipment Download PDFInfo
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Abstract
The application provides a data frame timing forwarding method and device based on an FPGA, the FPGA and data exchange equipment, which are used for constructing a more efficient processing framework for storing and forwarding data frames when the data frames are forwarded according to timestamps, so that a large amount of hardware resources and data processing resources can be saved. For the data exchange equipment, the FPGA is configured, the FPGA is responsible for carrying a timestamp to indicate the data frame forwarding work of a desired sending time point, on one hand, the data frame which does not reach the sending time point is transferred to a memory outside the FPGA, the storage space and the management cost of a large number of data frames by the FPGA body are saved, on the other hand, the FPGA body can perform the data frame forwarding by virtue of saved large data processing resources, so that a more efficient processing framework is constructed for the data frame storage and forwarding, and a large number of hardware resources and data processing resources can be saved.
Description
Technical Field
The application relates to the field of communication, in particular to a data frame timing forwarding method and device based on an FPGA, the FPGA and data exchange equipment.
Background
In communication, a header of service data contains a timestamp, which indicates a data forwarding time, which may also be referred to as a timing time, and when the data switching device receives the type of service data, the data switching device needs to parse the header and forward the service data according to the timing time specified by the timestamp.
When the data exchange equipment only processes one or more frames of the service data of the type, only a timing device in the processor chip is needed, when the timing time is up, whether a time stamp in the data frame is close to or equal to the current time is inquired and judged, and if the time stamp is equal to the current time, the data frame is forwarded.
When the amount of the service data of this type is large, for example, when there are thousands, tens of thousands, hundreds of thousands of data to be processed, each timing time needs to compare the timestamp of the data frame, which extremely consumes the timer resource and the computing resource of the processor, and causes a bottleneck to the performance of the processor processing the service data of this type, and a large amount of idle memory space fragments will be left after the data frame is taken away, resulting in a storage address space storage policy of the newly input data frame requiring a complex method to solve the cache management problem of the data frame.
Disclosure of Invention
The application provides a method and a device for forwarding a data frame at regular time based on a Field-Programmable Gate Array (FPGA), the FPGA and a data exchange device, which are used for constructing a more efficient processing architecture for storing and forwarding the data frame when the data frame is forwarded according to a timestamp, so that a large amount of hardware resources and data processing resources can be saved.
In a first aspect, the present application provides a method for forwarding a data frame at a fixed time based on an FPGA, which is applied to the FPGA, wherein the FPGA includes six modules, namely an input time-second buffer module, an input data frame buffer module, a data queue management module, a data frame processing and storing module, a storage queue traversing module, and an output data frame buffer module, and the method includes:
the input data frame buffer module buffers data frames outside the FPGA;
the data frame processing and storing module extracts the data frame from the input data frame caching module, extracts a carried time stamp used for indicating an expected sending time point from a frame header of the data frame, and forwards the data frame to the output data frame caching module for outputting if the corresponding time point of the time stamp is earlier than or equal to the current time point provided by the input time second caching module; if the corresponding time point of the timestamp is later than the current time point provided by the input time second cache module, storing the data frame in a memory outside the FPGA, and extracting a corresponding line number from the data queue management module as a storage identifier of the data frame on the memory outside the FPGA, wherein the input time second cache module is used for caching a digital clock of a clock source outside the FPGA, the output data frame cache module is used for forwarding the input data frame to an output port, the data queue management module is used for storing the line number of an unallocated data frame, and the line number of the unallocated data frame corresponds to different storage positions of the memory outside the FPGA;
the storage queue traversing module traverses different data frames stored in a memory outside the FPGA along with the triggering of the periodic trigger signal provided by the input time second cache module, forwards a target data frame of which the expected sending time point is equal to the current time point provided by the input time second cache module to the output data frame cache module, and triggers the data queue management module to update according to the line number of the target data frame so as to return the line number of the target data frame.
With reference to the first aspect of the present application, in a first possible implementation manner of the first aspect of the present application, the data queue management module stores the line number of the unallocated data frame by using a first-in first-out queue.
With reference to the first aspect of the present application, in a second possible implementation manner of the first aspect of the present application, during the process that the data frame is stored in the memory outside the FPGA by the data frame processing and storing module, the line number is further added to the frame header of the data frame.
With reference to the first aspect of the present application, in a third possible implementation manner of the first aspect of the present application, in a process that the data frame processing and storing module stores the data frame in a memory outside the FPGA, a corresponding count value is generated based on a time difference between a corresponding time point of the timestamp and a current time point provided by the input time second cache module, and the count value is added to a frame header of the data frame;
and the storage queue traversing module is specifically used for traversing the frame headers of different data frames stored in a memory outside the FPGA along with the triggering of the periodic trigger signal provided by the input time-second cache module, subtracting one from the count value carried in the frame headers of the different data frames during each traversal, and forwarding the target data frame with the corresponding count value of zero to the output data frame cache module.
With reference to the first aspect of the present application, in a fourth possible implementation manner of the first aspect of the present application, the periodic trigger Signal provided by the input time-second buffer module is specifically an interrupt Signal generated according to an update time per secondInterrupt。
With reference to the first aspect of the present application, in a fifth possible implementation manner of the first aspect of the present application, the Memory outside the FPGA is specifically a Random Access Memory (RAM).
In a second aspect, the present application provides a device for forwarding data frames at regular time based on an FPGA, the device including:
the buffer unit is used for buffering data frames outside the FPGA through the input data frame buffer module;
the processing unit is used for extracting the data frame from the input data frame cache module through the data frame processing and storing module, extracting a carried time stamp used for indicating an expected sending time point from a frame header of the data frame, and forwarding the data frame to the output data frame cache module for outputting if the corresponding time point of the time stamp is earlier than or equal to the current time point provided by the input time second cache module; if the corresponding time point of the timestamp is later than the current time point provided by the input time second cache module, storing the data frame in a memory outside the FPGA, and extracting a corresponding line number from the data queue management module as a storage identifier of the data frame on the memory outside the FPGA, wherein the input time second cache module is used for caching a digital clock of a clock source outside the FPGA, the output data frame cache module is used for forwarding the input data frame to an output port, the data queue management module is used for storing the line number of an unallocated data frame, and the line number of the unallocated data frame corresponds to different storage positions of the memory outside the FPGA;
and the traversal unit is used for traversing different data frames stored in a memory outside the FPGA by the storage queue traversal module along with the triggering of the periodic trigger signal provided by the input time second cache module, forwarding a target data frame of which the expected sending time point is equal to the current time point provided by the input time second cache module to the output data frame cache module, and triggering the data queue management module to update according to the line number of the target data frame so as to return the line number of the target data frame.
With reference to the second aspect of the present application, in a first possible implementation manner of the second aspect of the present application, the data queue management module stores the line number of the unallocated data frame by using a first-in first-out queue.
With reference to the second aspect of the present application, in a second possible implementation manner of the second aspect of the present application, the processing unit further adds a line number to a frame header of the data frame in a process of storing the data frame in a memory outside the FPGA through the data frame processing and storing module.
In combination with the second aspect of the present application, in a third possible implementation manner of the second aspect of the present application, in a process that the processing unit stores the data frame in a memory outside the FPGA through the data frame processing and storing module, the processing unit further generates a corresponding count value based on a time difference between a corresponding time point of the timestamp and a current time point provided by the input time second cache module, and adds the count value to a frame header of the data frame;
and the traversal unit is specifically used for traversing the frame headers of different data frames stored in a memory outside the FPGA by triggering the storage queue traversal module along with the periodic trigger signal provided by the input time second cache module, subtracting one from the count value carried in the frame headers of the different data frames during each traversal, and forwarding the target data frame with the corresponding count value of zero to the output data frame cache module.
With reference to the second aspect of the present application, in a fourth possible implementation manner of the second aspect of the present application, the periodic trigger Signal provided by the input time-second buffer module is specifically an interrupt Signal generated according to an update time per secondInterrupt。
With reference to the second aspect of the present application, in a fifth possible implementation manner of the second aspect of the present application, the memory outside the FPGA is specifically a RAM.
In a third aspect, the present application provides an FPGA, which includes a processor and a memory, where the memory stores a computer program, and the processor executes the method provided by the first aspect of the present application or any one of the possible implementation manners of the first aspect of the present application when calling the computer program in the memory.
In a fourth aspect, the present application provides a data exchange device, where the data exchange device includes the FPGA provided in the third aspect, and the data exchange device performs forwarding of data frames through the FPGA.
In a fifth aspect, the present application provides a computer-readable storage medium storing a plurality of instructions adapted to be loaded by a processor to perform the method provided in the first aspect of the present application or any one of the possible implementations of the first aspect of the present application.
From the above, the present application has the following advantageous effects:
for the data exchange equipment, the FPGA is configured, the FPGA is responsible for carrying a timestamp to indicate the data frame forwarding work of a desired sending time point, on one hand, the data frame which does not reach the sending time point is transferred to a memory outside the FPGA, the storage space and the management cost of a large number of data frames by the FPGA body are saved, on the other hand, the FPGA body can perform the data frame forwarding by virtue of saved large data processing resources, so that a more efficient processing framework is constructed for the data frame storage and forwarding, and a large number of hardware resources and data processing resources can be saved.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
FIG. 1 is a schematic structural diagram of an FPGA of the present application;
FIG. 2 is a schematic flow chart of the method for forwarding data frames based on FPGA according to the present application
FIG. 3 is a schematic diagram of a working scenario of the FPGA of the present application;
FIG. 4 is a schematic diagram of a scenario in which a memory external to the FPGA stores a frame of data according to the present application;
fig. 5 is a schematic structural diagram of the FPGA-based data frame timing forwarding apparatus according to the present application;
fig. 6 is a schematic structural diagram of a data exchange device according to the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
The terms "first," "second," and the like in the description and in the claims of the present application and in the above-described drawings are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It will be appreciated that the data so used may be interchanged under appropriate circumstances such that the embodiments described herein may be practiced otherwise than as specifically illustrated or described herein. Moreover, the terms "comprises," "comprising," and any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or modules is not necessarily limited to those steps or modules explicitly listed, but may include other steps or modules not expressly listed or inherent to such process, method, article, or apparatus. The naming or numbering of the steps appearing in the present application does not mean that the steps in the method flow have to be executed in the chronological/logical order indicated by the naming or numbering, and the named or numbered process steps may be executed in a modified order depending on the technical purpose to be achieved, as long as the same or similar technical effects are achieved.
The division of the modules presented in this application is a logical division, and in practical applications, there may be another division, for example, multiple modules may be combined or integrated into another system, or some features may be omitted, or not executed, and in addition, the shown or discussed coupling or direct coupling or communication connection between each other may be through some interfaces, and the indirect coupling or communication connection between the modules may be in an electrical or other similar form, which is not limited in this application. The modules or sub-modules described as separate components may or may not be physically separated, may or may not be physical modules, or may be distributed in a plurality of circuit modules, and some or all of the modules may be selected according to actual needs to achieve the purpose of the present disclosure.
Before introducing the FPGA-based data frame timing forwarding method provided by the present application, first, the background related to the present application is introduced.
The FPGA-based data frame timing forwarding method and device, the FPGA and the computer-readable storage medium can be applied to data exchange equipment and used for constructing a more efficient processing architecture for storing and forwarding the data frame when the data frame is forwarded according to the timestamp, so that a large amount of hardware resources and data processing resources can be saved.
According to the FPGA-based data frame timing forwarding method, an execution main body can be an FPGA-based data frame timing forwarding device or an FPGA integrated with the FPGA-based data frame timing forwarding device, and the FPGA can be assembled on different types of data exchange Equipment such as a server, a physical host or User Equipment (UE).
The FPGA-based data frame timing forwarding device may be implemented by hardware or software, and the UE may specifically be a terminal device such as a smart phone, a tablet computer, a notebook computer, a desktop computer, or a Personal Digital Assistant (PDA).
The data exchange device may be set in a device cluster manner, and may be a dedicated device for performing data forwarding operations, and such a device is generally directly deployed in a communication network system in a specific application scenario; or, the data exchange device may also be a device that loads a corresponding data program to perform data forwarding work, and may be specifically adjusted according to actual needs.
The method for forwarding the data frame based on the FPGA at regular time provided by the present application is described below.
Firstly, referring to fig. 1, a schematic structural diagram of the FPGA of the present application is shown, and as can be seen from fig. 1, the FPGA of the present application includes six modules, namely, an input time second buffer module, an input data frame buffer module, a data queue management module, a data frame processing and storing module, a storage queue traversing module, and an output data frame buffer module.
On the basis of the structure shown in fig. 1, with continued reference to fig. 2, the method for forwarding a data frame based on an FPGA at a fixed time may specifically include the following steps S201 to S203:
step S201, inputting a data frame buffer module to buffer a data frame outside the FPGA;
it is understood from the working point of view that the FPGA starts from the external, i.e. predetermined data link, when it performs the forwarding of the data frame.
For the input data frame buffer module, it can specifically convert the parallel signal of the externally input data frame into the serial signal processed inside the FPGA, and also convert the clock carried by the externally input data frame into the global synchronous clock inside the FPGA, where the clock is the timestamp carried in the header of the data frame to indicate the expected sending time point.
Illustratively, generally, for a data frame for which this application is directed, the following is included:
the format is | frame header | + | data field |;
the format of the | frame header | is | timestamp | + | other fields |;
the | data field | represents the information that really wants to be conveyed in the design.
Step S202, the data frame processing and storing module extracts the data frame from the input data frame caching module, extracts the carried time stamp used for indicating the expected sending time point from the frame header of the data frame, and forwards the data frame to the output data frame caching module for outputting if the corresponding time point of the time stamp is earlier than or equal to the current time point provided by the input time second caching module; if the corresponding time point of the timestamp is later than the current time point provided by the input time second cache module, storing the data frame in a memory outside the FPGA, and extracting a corresponding line number from the data queue management module as a storage identifier of the data frame on the memory outside the FPGA, wherein the input time second cache module is used for caching a digital clock of a clock source outside the FPGA, the output data frame cache module is used for forwarding the input data frame to an output port, the data queue management module is used for storing the line number of an unallocated data frame, and the line number of the unallocated data frame corresponds to different storage positions of the memory outside the FPGA;
it can be understood that, when the input data frame buffer module buffers a new data frame into the FPGA, the data frame processing and storing module may be triggered to determine whether the data frame is forwarded in real time or is transferred to a memory outside the FPGA.
Wherein the determination process is performed based on a comparison between a corresponding time point of the time stamp and a current time point provided by the input time-second buffer module.
For the input time second buffer module, it can receive the digital clock of the clock source outside the FPGA and provide the current time for the interior of the FPGA, which is also indicated by the timestamp. Specifically, the input time second buffer module may convert an external input time second parallel signal into a serial signal processed inside the FPGA, or may convert an external time second clock into a global synchronization clock inside the FPGA.
In addition, for the time management related to the FPGA, an external clock-crystal oscillator can be also involved, and the external clock-crystal oscillator is used for driving a clock in the FPGA chip.
When the data frame which does not need to be forwarded in real time is transferred to a memory outside the FPGA, a line number can be provided by the data queue management module to identify the data frame, for the line number, the line number stored in the data queue management module is understood as the line number which is not allocated to the corresponding data frame, if a line number X is currently allocated, the line number can be taken out from the line number stored in the data queue management module, at the moment, the line number stored in the data queue management module is in a state without the line number X, if no line number exists in the data queue management module, the line number which can be provided in the data queue management module is already allocated, the data frame which can be transferred to the memory outside the FPGA reaches a preset upper limit, and in the state, the data frame which is stored in the memory outside the FPGA needs to be waited to reach a preset sending time point for forwarding, Returning the row number to the rear of the data queue management module can continuously provide the row number which can be distributed.
Obviously, under the mechanism, the setting of the line number not only can identify the data frames to be transferred, but also fixes the upper limit of the number of the data frames to be transferred in advance due to the fixed limit of the number of the data frames, and certainly, in practical application, the number of the line number can be set to be much larger than the normal number which can be reached in unit time during actual data forwarding work, so that the transferring work of the data frames cannot be influenced, and meanwhile, if the line number is completely distributed, an event that the work of the FPGA or a memory outside the FPGA is abnormal can be possibly caused, and an alarm effect of abnormal monitoring is achieved.
For the external memory of the FPGA, the memory can be any type and can meet the requirement of storing data frames outside the FPGA, and as a practical implementation mode, the RAM can be specifically adopted as the external memory for storing the data frames outside the FPGA, can be read and written at any time (except for refreshing), is high in speed, and is suitable for the read-write operation of the data frames based on time expansion related to the application.
At this time, the above-mentioned contents can be understood by referring to an operation scene schematic diagram of the FPGA shown in fig. 3 in combination with the crystal oscillator and the RAM (the FPGA may also be referred to as a data forwarding module).
In addition, the output port referred to in this application may be understood as a port configured by the data switching device for forwarding a data frame, and may include a port at a physical layer or a port at a data layer, which is adjusted according to actual needs.
The output data frame buffer module can buffer the input data frame, namely buffer the data frame forwarded by other modules, and forward the data frame to the output port, so as to promote the FPGA to complete the forwarding work of the data frame.
Step S203, the storage queue traversing module traverses different data frames stored in a memory outside the FPGA according to the triggering of the periodic trigger signal provided by the input time-second buffer module, forwards the target data frame of which the expected transmission time point is equal to the current time point provided by the input time-second buffer module to the output data frame buffer module, and triggers the data queue management module to update according to the line number of the target data frame, so as to return the line number of the target data frame.
When the data frame is transferred to a storage outside the FPGA for forwarding, the data frame can be delivered to a storage queue traversing module of the FPGA, whether each data frame stored in the storage outside the FPGA reaches a preset sending time point or not is monitored in a traversing mode, if the data frame reaches the preset sending time point (the expected sending time point is equal to the current time point provided by the input time second cache module), the target data frame can be extracted from the storage outside the FPGA and forwarded to the output data frame cache module, and the output data frame cache module forwards the target data frame to the output port.
As can be seen from the above, for the data exchange device, an FPGA is configured for the data exchange device, and the FPGA is responsible for carrying a timestamp to indicate a data frame forwarding operation at a desired sending time point, so that on one hand, a data frame which does not reach the sending time point is transferred to a memory outside the FPGA, thereby saving storage space and management cost of the FPGA body for a large number of data frames, and on the other hand, the FPGA body can perform data frame forwarding by using a large amount of saved data processing resources, thereby constructing a more efficient processing architecture for the data frame storage and forwarding, and saving a large amount of hardware resources and data processing resources.
In addition, in practical application, the FPGA can also be configured with a further optimization scheme.
As another practical implementation, the data queue management module may specifically store the line number of the unallocated data frame by using a first-in-first-out queue.
In a specific application, the depth of a First-in First-out (FIFO) queue may be the number of frames of a data frame that can be stored in a memory outside the FPGA, and the depth is set to number _ of _ lines, which is used to manage a data frame queue stored in the memory outside the FPGA.
Initially, sequentially filling data in the FIFO queue into 1, … …, N (N equals to number _ of _ lines), which means that no data frame is unloaded from a memory outside the FPGA;
when the FPGA runs for a period of time, if the memory outside the FPGA does not have any data frame taken out and the FIFO queue is empty, the system can judge that each line of the memory outside the FPGA is full, and the system can store the data frame into the memory outside the FPGA again after waiting for the data frame to be taken out.
It will be appreciated that managing the line numbers used to identify corresponding data frames via the FIFO queue has the advantage of being low cost and efficient in management.
As another practical implementation manner, in the process that the data frame processing and storing module stores the data frame in the memory outside the FPGA, the line number, which is extracted by the data queue management module and allocated for the data frame, may be directly added to the frame header of the data frame.
At this time, for the data frame, the format of the data frame is | frame header | + | data field |, and the format of | frame header | is | row number | + | timestamp |, so the row number allocated to the data frame is indicated simply and clearly, which is convenient for the traversal of the storage queue traversal module.
As another practical implementation manner, for the traversal processing related to the storage queue traversal module, in the process that the data frame processing and storing module stores the data frame in the memory outside the FPGA, specifically, a corresponding count value may be generated based on a time difference between a corresponding time point of the timestamp and a current time point provided by the input time second cache module, and the count value is added to the frame header of the data frame;
at this time, for the data frame, the format of the data frame is | frame header | + | data field |, and the format of | frame header | is | line sign | + | counting value | + | timestamp |.
If the count value is counted in seconds, it is obvious that the value may be directly a time difference calculated in seconds, for example, a time difference of 5 seconds corresponds to a count value of 5.
Correspondingly, the storage queue traversing module may be specifically configured to traverse the frame headers of different data frames stored in a memory outside the FPGA along with the triggering of the periodic trigger signal provided by the input time-second cache module, subtract one from the count value carried in the frame headers of the different data frames for each traversal, and forward the target data frame whose corresponding count value is zero to the output data frame cache module.
Compared with the prior art that whether the data frame is forwarded or not is determined by comparing the current time point (the current time point provided by the corresponding input time second cache module) with the preset sending time point, in the traversal mechanism of the present application, frequent comparison for extracting the two time points (generally in a timestamp form) is bypassed, but the uniform trigger signal is adopted for triggering traversal, and timing is performed respectively, so that data processing required for frequently executing extraction and comparison of the two time points is greatly saved, timer resources and calculation resources are greatly reduced, execution efficiency of the present application on data frame forwarding work is further enhanced, and execution cost is significantly reduced.
In another practical implementation, the periodic trigger Signal provided by the input time-second buffer module may be specifically an interrupt Signal generated according to an update time per secondInterruptIn this case, the storage queue traversal module may uniformly traverse the data frames stored in the memory outside the FPGA in units of seconds, and in this case, if the above-mentioned exemplary timing mechanism is executed, the time difference in units of seconds may be directly used as a count value to perform timing, so that the traversal processing executed by the storage queue traversal module is better, concise and clear.
For the memory outside the FPGA, it is mentioned above that the line number related to the present application may identify the data frame stored in the memory outside the FPGA, and may also determine a specific storage location in the memory outside the FPGA, and in practical application, the storage location may also be a specific line in a data frame storage format of the line in the memory outside the FPGA, specifically, the present application may also be understood by referring to a scene diagram of the memory outside the FPGA shown in fig. 4 for storing the data frame.
Taking the RAM as an example, since the space where the external RAM address 0 is located is used for other purposes of the system, and the capacity of the external RAM is usually large and much larger than the buffer area of the required data frame, the middle area of the external RAM is taken as the buffer area of the data frame. According to the size of the RAM and the length of a data frame, the external RAM is designed to be divided into rows, the rows are provided with number _ of _ lines, the byte number of each row is larger than that of the data frame, the byte number of each row is equal and is the power of N of 2, and therefore the addressing operation is conveniently carried out on the row head of each row;
when the FPGA operates initially, the external RAM is divided according to lines, a storage mark | is arranged at the head of each line, the storage mark | is 1 to indicate that a data frame is stored in a storage position (line) at the head, the storage mark | is 0 to indicate that the data frame is not stored in the storage position (line) or is taken away, and the storage mark | is 0 initially;
thus, taking the above exemplary implementation as an example, the interrupt Signal per secondInterruptWhen the data arrives, the storage queue traversal module starts a traversal process, the read-write process required for traversing each line of the cache area of the external RAM works under the clock drive of the external crystal oscillator of the FPGA, traversal is sequentially carried out from the first line to the number _ of _ lines line, and each line is processed as follows:
reading a storage mark in the row of data frame, traversing the next row if the storage mark | represents 0, reading the value of the row second counter if the storage mark | represents 1, and subtracting 1 from the value of the second counter;
if the value of the second counter is changed into 0, the data frame is immediately taken out from the line, when the data frame is taken out, the | storage mark | of the line is set to be 0, the data frame is forwarded to an output data frame buffer module, and meanwhile, the line number of the taken out data frame is stored in an FIFO queue of a storage queue management module;
if the value of the second counter does not become 0, the value of the second counter is stored as a new second counter in the corresponding address after the operation is completed.
The above is the introduction of the method for forwarding the data frame at the fixed time based on the FPGA provided by the present application, and in order to better implement the method for forwarding the data frame at the fixed time based on the FPGA provided by the present application, the present application also provides a device for forwarding the data frame at the fixed time based on the FPGA from the perspective of a functional module.
Referring to fig. 5, fig. 5 is a schematic structural diagram of the FPGA-based data frame timing forwarding apparatus according to the present invention, in the present application, the FPGA-based data frame timing forwarding apparatus 500 may specifically include the following structure:
a buffer unit 501, configured to buffer a data frame outside the FPGA through an input data frame buffer module;
a processing unit 502, configured to extract a data frame from the input data frame cache module through the data frame processing and storage module, extract a timestamp carried in a frame header of the data frame and used for indicating an expected sending time point, and forward the data frame to the output data frame cache module for output if a corresponding time point of the timestamp is earlier than or equal to a current time point provided by the input time second cache module; if the corresponding time point of the timestamp is later than the current time point provided by the input time second cache module, storing the data frame in a memory outside the FPGA, and extracting a corresponding line number from the data queue management module as a storage identifier of the data frame on the memory outside the FPGA, wherein the input time second cache module is used for caching a digital clock of a clock source outside the FPGA, the output data frame cache module is used for forwarding the input data frame to an output port, the data queue management module is used for storing the line number of an unallocated data frame, and the line number of the unallocated data frame corresponds to different storage positions of the memory outside the FPGA;
the traversal unit 502 is configured to traverse different data frames stored in a memory outside the FPGA by triggering the storage queue traversal module with a periodic trigger signal provided by the input time-second buffer module, forward a target data frame whose expected transmission time point is equal to a current time point provided by the input time-second buffer module to the output data frame buffer module, and trigger the data queue management module to update according to a line number of the target data frame, so as to return the line number of the target data frame.
In yet another exemplary implementation, the data queue management module uses a first-in-first-out queue to store the row number of the unallocated data frame.
In yet another exemplary implementation manner, the processing unit 502 further adds a line number to a header of the data frame during the process of storing the data frame in a memory outside the FPGA through the data frame processing and storing module.
In yet another exemplary implementation manner, in the process of storing the data frame in the memory outside the FPGA through the data frame processing and storing module, the processing unit 502 further generates a corresponding count value based on a time difference between a corresponding time point of the timestamp and a current time point provided by the input time second cache module, and adds the count value to a frame header of the data frame;
the traversal unit 503 is specifically configured to traverse the frame headers of different data frames stored in the memory outside the FPGA by triggering the storage queue traversal module with the periodic trigger signal provided by the input time-second cache module, reduce the count value carried in the frame headers of the different data frames by one for each traversal, and forward the target data frame with the corresponding count value of zero to the output data frame cache module.
In another exemplary implementation, the periodic trigger Signal provided by the input time-second buffer module is specifically an interrupt Signal generated according to an update time per secondInterrupt。
In yet another exemplary implementation, the memory external to the FPGA is embodied as RAM.
The application also provides an FPGA, wherein the FPGA can structurally comprise six modules, namely an input time second cache module, an input data frame cache module, a data queue management module, a data frame processing and storing module, a storage queue traversing module and an output data frame cache module, and the FPGA can comprise a processor and a memory, when the processor is used for executing a computer program stored in the memory and triggering the FPGA to execute corresponding data frame forwarding work, the steps of the FPGA-based data frame timing forwarding method in the corresponding embodiment of FIG. 2 are realized; or, when the processor is configured to trigger the FPGA to execute a corresponding data frame forwarding operation when executing the computer program stored in the memory, the processor implements functions of each unit in the embodiment corresponding to fig. 5, and the memory is configured to store the computer program required by the processor to execute the data frame timing forwarding method in the embodiment corresponding to fig. 2.
The application also provides a data exchange device from the perspective of a hardware structure, wherein the data exchange device comprises the FPGA provided by the application, and the FPGA is used for forwarding data frames. Referring to fig. 6, fig. 6 shows a schematic structural diagram of the data exchange device, specifically, the data exchange device may further include a processor 601, a memory 602, and an input/output device 603 in addition to the FPGA.
Illustratively, a computer program may be partitioned into one or more modules/units, which are stored in the memory 602 and executed by the processor 601 to accomplish the present application. One or more modules/units may be a series of computer program instruction segments capable of performing certain functions, the instruction segments being used to describe the execution of a computer program in a computer device.
The data exchange devices may include, but are not limited to, a processor 601, a memory 602, and input output devices 603. It will be appreciated by a person skilled in the art that the illustration is merely an example of a data switching device and does not constitute a limitation of the data switching device and may comprise more or less components than those illustrated, or some components may be combined, or different components, e.g. the data switching device may further comprise a network access device, a bus, etc. via which the processor 601, the memory 602, the input output device 603, etc. are connected.
The Processor 601 may be a Central Processing Unit (CPU), other general purpose Processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), an FPGA or other programmable logic device, a discrete gate or transistor logic device, a discrete hardware component, or the like. The general purpose processor may be a microprocessor or the processor may be any conventional processor or the like, the processor being the control center of the data switching apparatus, the various parts of the overall apparatus being connected by various interfaces and lines.
The memory 602 may be used for storing computer programs and/or modules, and the processor 601 may implement various functions of the computer apparatus by executing or executing the computer programs and/or modules stored in the memory 602 and calling data stored in the memory 602. The memory 602 may mainly include a program storage area and a data storage area, wherein the program storage area may store an operating system, an application program required for at least one function, and the like; the storage data area may store data created according to use of the data exchange device, and the like. In addition, the memory may include high speed random access memory, and may also include non-volatile memory, such as a hard disk, a memory, a plug-in hard disk, a Smart Media Card (SMC), a Secure Digital (SD) Card, a Flash memory Card (Flash Card), at least one magnetic disk storage device, a Flash memory device, or other volatile solid state storage device.
The processor 601 is configured to execute the computer program stored in the memory 602 to trigger the FPGA to execute the corresponding data frame forwarding operation, and specifically may implement the following functions:
the input data frame buffer module buffers data frames outside the FPGA;
the data frame processing and storing module extracts the data frame from the input data frame caching module, extracts a carried time stamp used for indicating an expected sending time point from a frame header of the data frame, and forwards the data frame to the output data frame caching module for outputting if the corresponding time point of the time stamp is earlier than or equal to the current time point provided by the input time second caching module; if the corresponding time point of the timestamp is later than the current time point provided by the input time second cache module, storing the data frame in a memory outside the FPGA, and extracting a corresponding line number from the data queue management module as a storage identifier of the data frame on the memory outside the FPGA, wherein the input time second cache module is used for caching a digital clock of a clock source outside the FPGA, the output data frame cache module is used for forwarding the input data frame to an output port, the data queue management module is used for storing the line number of an unallocated data frame, and the line number of the unallocated data frame corresponds to different storage positions of the memory outside the FPGA;
the storage queue traversing module traverses different data frames stored in a memory outside the FPGA along with the triggering of the periodic trigger signal provided by the input time second cache module, forwards a target data frame of which the expected sending time point is equal to the current time point provided by the input time second cache module to the output data frame cache module, and triggers the data queue management module to update according to the line number of the target data frame so as to return the line number of the target data frame.
It can be clearly understood by those skilled in the art that, for convenience and brevity of description, the specific working processes of the FPGA-based data frame timing forwarding apparatus, the FPGA, the data switching device and the corresponding units thereof described above may refer to the description of the FPGA-based data frame timing forwarding method in the corresponding embodiment of fig. 2, and are not described herein again in detail.
It will be understood by those skilled in the art that all or part of the steps of the methods of the above embodiments may be performed by instructions or by associated hardware controlled by the instructions, which may be stored in a computer readable storage medium and loaded and executed by a processor.
For this reason, the present application provides a computer-readable storage medium, where a plurality of instructions are stored, where the instructions can be loaded by a processor to execute the steps of the FPGA-based data frame timing forwarding method in the embodiment corresponding to fig. 2 in the present application, and specific operations may refer to the description of the FPGA-based data frame timing forwarding method in the embodiment corresponding to fig. 2, and are not described herein again.
Wherein the computer-readable storage medium may include: read Only Memory (ROM), Random Access Memory (RAM), magnetic or optical disks, and the like.
Since the instructions stored in the computer-readable storage medium can execute the steps of the FPGA-based data frame timing forwarding method in the embodiment corresponding to fig. 2, the beneficial effects that can be achieved by the FPGA-based data frame timing forwarding method in the embodiment corresponding to fig. 2 can be achieved, which are described in detail in the foregoing description and are not described herein again.
The method and the device for forwarding the data frame at regular time based on the FPGA, the device for forwarding the data frame at regular time based on the FPGA, and the computer-readable storage medium provided by the present application are introduced in detail, and specific examples are applied in the description to explain the principle and the implementation of the present application, and the description of the above embodiments is only used to help understanding the method and the core idea of the present application; meanwhile, for those skilled in the art, according to the idea of the present application, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present application.
Claims (10)
1. A data frame timing forwarding method based on FPGA is characterized in that the method is applied to FPGA, the FPGA comprises six modules of an input time second cache module, an input data frame cache module, a data queue management module, a data frame processing and storing module, a storage queue traversing module and an output data frame cache module, and the method comprises the following steps:
the input data frame buffer module buffers data frames outside the FPGA;
the data frame processing and storing module extracts the data frame from the input data frame caching module, extracts a time stamp carried in a frame header of the data frame and used for indicating an expected sending time point, and forwards the data frame to the output data frame caching module for outputting if the corresponding time point of the time stamp is earlier than or equal to the current time point provided by the input time second caching module; if the corresponding time point of the timestamp is later than the current time point provided by the input time second cache module, storing the data frame in a memory outside the FPGA, and extracting a corresponding line number from the data queue management module as a storage identifier of the data frame on the memory outside the FPGA, wherein the input time second cache module is used for caching a digital clock of a clock source outside the FPGA, the output data frame cache module is used for forwarding the input data frame to an output port, the data queue management module is used for storing the line number of an unallocated data frame, and the line number of the unallocated data frame corresponds to different storage positions of the memory outside the FPGA;
the storage queue traversing module traverses different data frames stored in a memory outside the FPGA along with the triggering of the periodic trigger signal provided by the input time second cache module, forwards a target data frame of which the expected sending time point is equal to the current time point provided by the input time second cache module to the output data frame cache module, and triggers the data queue management module to update according to the line number of the target data frame so as to return the line number of the target data frame.
2. The method of claim 1, wherein the data queue management module stores the line number of the unallocated data frame using a first-in-first-out queue.
3. The method according to claim 1, wherein the data frame processing and storing module further adds the line number to a header of the data frame during storing the data frame in a memory external to the FPGA.
4. The method according to claim 1, wherein the data frame processing and storing module generates a corresponding count value based on a time difference between a corresponding time point of the timestamp and a current time point provided by the input time second cache module during the process of storing the data frame in a memory outside the FPGA, and adds the count value to a header of the data frame;
the storage queue traversing module is specifically configured to traverse frame headers of different data frames stored in a memory outside the FPGA along with the triggering of the periodic trigger signal provided by the input time-second cache module, reduce a count value carried in the frame headers of the different data frames by one for each traversal, and forward a target data frame with a corresponding count value of zero to the output data frame cache module.
5. Method according to claim 1, wherein the periodic trigger Signal provided by the input time-second buffer module is an interrupt Signal generated according to an update time per secondInterrupt。
6. Method according to claim 1, characterized in that the memory external to the FPGA is in particular a random access memory RAM.
7. An FPGA-based data frame timing forwarding device, characterized in that the device comprises:
the buffer unit is used for buffering the data frame outside the FPGA through an input data frame buffer module;
the processing unit is used for extracting the data frame from the input data frame cache module through the data frame processing and storing module, extracting a carried time stamp used for indicating an expected sending time point from a frame header of the data frame, and forwarding the data frame to the output data frame cache module for outputting if the corresponding time point of the time stamp is earlier than or equal to the current time point provided by the input time second cache module; if the corresponding time point of the timestamp is later than the current time point provided by the input time second cache module, storing the data frame in a memory outside the FPGA, and extracting a corresponding line number from the data queue management module as a storage identifier of the data frame on the memory outside the FPGA, wherein the input time second cache module is used for caching a digital clock of a clock source outside the FPGA, the output data frame cache module is used for forwarding the input data frame to an output port, the data queue management module is used for storing the line number of an unallocated data frame, and the line number of the unallocated data frame corresponds to different storage positions of the memory outside the FPGA;
and the traversal unit is used for traversing different data frames stored in a memory outside the FPGA through the storage queue traversal module along with the triggering of the periodic trigger signal provided by the input time second cache module, forwarding a target data frame of which the expected sending time point is equal to the current time point provided by the input time second cache module to the output data frame cache module, and triggering the data queue management module to update according to the line number of the target data frame so as to return the line number of the target data frame.
8. A field programmable gate array FPGA, characterized in that it comprises a processor and a memory, in which a computer program is stored, which when called by the processor executes the method according to any one of claims 1 to 6.
9. A data switching device, characterized in that the data switching device comprises the FPGA of claim 8, and the data switching device performs the forwarding work of data frames through the FPGA.
10. A computer-readable storage medium storing a plurality of instructions adapted to be loaded by a processor to perform the method of any of claims 1 to 6.
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