CN114421990A - Quadrature demodulator chip - Google Patents

Abstract

The invention proposes a quadrature demodulator chip whose basic function is to realize the conversion of signal frequency. The input signal is a radio frequency signal, and the output signal is a baseband signal. By adding a local oscillator signal, the down-conversion processing of the signal is realized. The quadrature signal generator uses the SCL frequency divider to divide the input differential local oscillator signal, and generates four local oscillator signals with the same frequency and 90° phase difference with each other. The signal is amplified and buffered and sent to the mixer; The frequency converter converts the input RF signal into a current signal, mixes it with the local oscillator signal, adds it in the resistive load and feeds it into the output buffer of the latter stage; the output buffer outputs the mixed IQ quadrature signal, And realize fixed impedance through on-chip resistance to achieve broadband impedance matching; the above three parts all provide DC bias through the bias module. The input RF signal is in differential form; the local oscillator signal is in differential form or single-ended form; the output baseband signal is an IQ quadrature signal, and the frequency is the difference between the frequency of the local oscillator and the RF signal.

Description

A quadrature demodulator chip

technical field

The invention belongs to the technical field of wireless communication transceiver systems, and in particular, relates to a quadrature demodulator chip.

Background technique

In modern communication systems, the extension of the frequency band and the increase of the transmission distance make the transmission process more and more favored in the radio frequency domain; and with the shrinking of the process size and the further improvement of the computing power, the signal processing must also be carried out in the digital domain. Although the performance of analog-to-digital converters and digital-to-analog converters is constantly improving, whether it is the attenuation of the channel or the requirement of transmit power, an RF front-end is required to achieve signal capture and transmission. As an indispensable part of wireless communication, the RF front-end can amplify and down-convert weak signals in its receiving part, and then provide the intermediate frequency signal to the analog-to-digital converter; its transmitting part receives the output signal of the digital-to-analog converter, Complete the up-conversion and amplification of the signal. In the whole process, the frequency conversion is realized by the quadrature modulator or quadrature demodulator, and the quadrature modulator realizes the up-frequency of the intermediate frequency signal and suppresses the image signal to improve the purity of the transmitted spectrum as much as possible; The intermodulator is located after the low-noise amplifier, and can provide a certain gain while reducing the frequency of the RF signal.

Although the RF front-end is gradually being replaced by RF communication multi-function chips as a whole, the RF front-end system built on discrete devices still occupies the mainstream, and its demand for quadrature modulators and quadrature demodulators is still huge, but the current The frequency coverage of quadrature demodulators on the market is low, which cannot meet the frequency hopping application of common frequencies from low frequency to high frequency band.

SUMMARY OF THE INVENTION

The technical solution of the present invention is: to deal with the problems of low frequency band coverage and poor linearity of the quadrature demodulator encountered in the development of the radio frequency front-end system of discrete components, and propose a wide coverage, high linearity and low power consumption quadrature solution. adjuster.

The technical scheme of the present invention includes: a quadrature demodulator chip, the chip includes a quadrature signal generator, a bias module, a mixer and an output driver;

The quadrature signal generator receives the local oscillator signal in differential form, generates the quadrature differential local oscillator signal, amplifies and limits the quadrature differential local oscillator signal, and sends it to the mixer, the quadrature differential local oscillator The signal includes I branch local oscillator positive signal LO_I'+, I branch local oscillator negative signal LO_I'-, Q branch local oscillator positive signal LO_Q'+, Q branch local oscillator negative signal LO_Q'-;

Bias module, which provides a temperature-invariant bias voltage signal for the quadrature signal generator, mixer and output driver respectively;

The mixer receives an externally input differential radio frequency signal, the differential radio frequency signal includes a radio frequency positive signal RF+, a radio frequency negative signal RF-, and mixes the differential radio frequency signal with the quadrature differential local oscillator signal transmitted by the quadrature signal generator frequency operation to obtain the baseband quadrature differential current signal, convert the baseband quadrature differential current signal into a voltage signal through the resistive load, obtain the baseband quadrature differential voltage signal, and then low-pass filter the baseband quadrature differential voltage signal and output it to the output a driver (400), wherein the baseband quadrature differential voltage signal includes an I branch positive signal I+, an I branch negative signal I-, a Q branch positive signal Q+, and a Q branch negative signal Q-;

The output driver isolates the baseband quadrature differential voltage signal output by the mixer from the mixer, enhances the driving capability of the baseband quadrature differential voltage signal and realizes impedance matching and then outputs the output signal to obtain the baseband quadrature differential voltage output signal. The frequency of the cross-differential voltage output signal is the difference between the frequency of the local oscillator signal and the differential radio frequency signal, and the baseband quadrature differential voltage output signal includes the I branch positive output signal I'+, the I branch negative output signal I'-, The Q branch output signal Q'+, and the Q branch negative output signal Q'-.

Preferably, the quadrature signal generator includes a first input buffer, a second input buffer, an SCL divider by two, a first output buffer, a second output buffer, a third output buffer, and a fourth output buffer ;The local oscillator input positive signal LO_in+ is connected to the first input buffer, the local oscillator input negative signal LO_in- is connected to the second input buffer, the first input buffer outputs the local oscillator positive signal LO+, and the second input buffer outputs the local oscillator negative signal lo-;

The output terminals of the first input buffer and the second input buffer are connected to the input terminal of the SCL frequency divider. The SCL frequency divider divides the local oscillator positive signal LO+ and the local oscillator negative signal LO- and outputs it. The SCL frequency divider The output terminals of the first output buffer, the second output buffer, the third output buffer, the input terminal of the fourth output buffer are respectively connected, the first output buffer, the second output buffer, the third output buffer, The fourth output buffer amplifies and limits the signal after frequency division by the SCL frequency divider, which are respectively the positive local oscillator signal LO_I'+ of the I branch, the negative local oscillator signal LO_I'- of the I branch, and the Q branch local signal. The positive vibration signal LO_Q'+, the negative local oscillator signal LO_Q'- of the Q branch, the signals of the I branch and the Q branch are at the same frequency and have a phase difference of 90° with each other.

Preferably, the first input buffer and the second input buffer have the same input buffer structure;

The input end of the input buffer is connected to the base of the transistor Q111 and one end of the impedance matching element Rx, the other end of Rx is connected to the power supply, the collector of Q111 is connected to one end of the load resistor R111 and the base of the transistor Q112, and the other end of the resistor R111 is connected to Power supply, the emitter of Q111 is connected to the collector of transistor Q113, the emitter of Q113 is grounded, the collector of Q112 is connected to one end of the current limiting resistor R112, the other end of the resistor R112 is connected to the power supply, the emitter of Q112 is the output of the input buffer, It is connected to the input end of the SCL frequency divider of the latter stage and the collector of the transistor Q114, the emitter of Q114 is grounded, and the bases of Q113 and Q114 are both connected to the BIAS voltage supplied by the bias module.

Preferably, the SCL frequency divider includes a master-level circuit and a slave-level circuit;

The main circuit includes transistors Q121, Q122, Q123, Q124, Q125, Q126, Q127, resistors R121, R122;

The slave circuit includes transistors Q221, Q222, Q223, Q224, Q225, Q226, Q227, resistors R221, R222;

In the main stage circuit, the positive signal LO+ of the local oscillator is connected to the base of the transistor Q125, the negative signal LO- of the local oscillator is connected to the base of the transistor Q126, the emitters of Q125 and Q126 are connected together and the collector of the transistor Q127 is connected , the emitter of Q127 is grounded, and the base is connected to the BIAS voltage provided by the bias module; the collector of Q125 is connected to the emitters of the differential pair transistors Q121 and Q122, and the bases of Q121 and Q122 are respectively connected to the output Q branch of the secondary circuit. Frequency local oscillator positive signal LO_Q+, Q branch frequency divided local oscillator negative signal LO_Q-, correspondingly, its collector is the output of main stage circuit I branch frequency divided local oscillator negative signal LO_I-, I branch frequency divided local oscillator The positive signal LO_I+, on the one hand, is used as the two output signals of the SCL frequency divider, on the other hand, it is connected to the bases of Q221 and Q222 of the slave circuit, and at the same time, the collectors of the main circuit Q121 and Q122 are connected to the resistors R121 and R122, respectively. One end, the other end of the two resistors is connected to the power supply, in addition, the collector of Q121 is connected to the collector of transistor Q123 and the base of Q124, the collector of Q122 is connected to the collector of transistor Q124 and the base of Q123, Q123, Q124 form a cross Coupling structure, the emitters of the two are connected together and connected to the collector of Q126;

In the slave stage circuit, the positive signal LO+ of the local oscillator is connected to the base of the transistor Q225, the negative signal LO- of the local oscillator is connected to the base of the transistor Q226, and the emitters of Q225 and Q226 are connected together and the collector of the transistor Q227 is connected , the emitter of Q227 is grounded, and the base is connected to the BIAS voltage provided by the bias module; the collector of Q225 is connected to the emitters of the differential pair transistors Q221 and Q222, and the bases of Q221 and Q222 are respectively connected to the output I branch of the main stage circuit. The frequency local oscillator positive signal LO_I+, the I branch frequency divides the local oscillator negative signal LO_I-, correspondingly, its collector is the output of the slave stage circuit Q branch frequency divides the local oscillator negative signal LO_Q-, the Q branch frequency divides this The positive signal LO_Q+, on the one hand, is used as the two output signals of the SCL frequency divider (121), on the other hand, it is connected to the bases of Q121 and Q122 of the main stage circuit, and at the same time, the collectors of the slave stage circuits Q221 and Q222 are respectively connected to resistors One end of R221, R222, the other end of the two resistors is connected to the power supply, in addition, the collector of Q221 is connected to the collector of transistor Q223 and the base of Q224, the collector of Q222 is connected to the collector of transistor Q224 and the base of Q223, Q223 , Q224 form a cross-coupling structure, the emitters of the two are connected together and connected to the collector of Q226.

Preferably, the first output buffer, the second output buffer, the third output buffer, and the fourth output buffer are all output buffer structures;

The output buffer includes transistors Q131, Q132, Q133, Q134, Q135, Q136, Q137, Q138, and resistors R131, R132, R133, R134;

The input end of the output buffer is connected to the base of the transistor Q131, the collector of Q131 is connected to one end of the resistor R131, the other end of R131 is connected to the power supply, the emitter of Q131 is connected to the collector of the transistor Q135 and the base of the amplifier Q132, Q132 The emitter of the transistor Q136 is connected to the collector, the collector of Q132 is connected to one end of the load resistor R132 and the base of Q133, the other end of R132 is connected to the power supply, the collector of Q133 is connected to one end of the resistor R133, and the other end of R133 is connected to the power supply. The emitter of Q133 is connected to the base of Q134 and the collector of Q137, the collector of Q134 is connected to one end of the resistor R134, the other end of R134 is connected to the power supply, the emitter of Q134 is the output end of the output buffer, on the one hand it is connected to the next stage mixing The input of the frequency converter is connected to the collector of Q138 on the one hand, the emitters of Q135, Q136, Q137, and Q138 are all grounded, and the bases are all connected to the BIAS voltage supplied by the bias module.

Preferably, the mixer includes an I-branch double-balanced mixer structure and a Q-branch double-balanced mixer structure; wherein:

The structure of the I-branch double-balanced mixer includes resistor R301, resistor R302, transistors Q301, Q302, Q303, Q304, Q305, Q306, and capacitor C301;

The structure of the Q branch double-balanced mixer includes resistor R307, resistor R308, transistors Q307, Q308, Q309, Q310, Q311, Q312, and capacitor C302;

The positive terminal RF+ of the differential radio frequency signal is connected to one end of the resistors R301 and R302, the other ends of the resistors R301 and R302 are respectively connected to the emitters of the transistors Q301 and Q302, the bases of Q301 and Q302 are connected to the voltage signal provided by the bias module, and the collectors are respectively Connect to the emitters of transistors Q303, Q304 and Q305, Q306, the base of transistor Q303 is connected to I branch local oscillator positive signal LO_I'+, the base of transistor Q304 is connected to I branch local oscillator negative signal LO_I'-, transistor Q305 The base of the Q branch is connected to the positive signal LO_Q'+ of the local oscillator of the Q branch, the base of the switch Q306 is connected to the negative signal LO_Q'- of the local oscillator of the Q branch, and the collector of the transistor Q303 is the output terminal. On the one hand, it is connected to one end of the load resistor R303, and at the same time, it is connected to one end of the filter capacitor C301 and fed into the lower-level circuit. The collector of the transistor Q304 is the output end, which is connected to the collector of Q309 on the one hand, and the load resistor on the other hand. One end of R304 is connected, and the other end of the filter capacitor C301 is connected to the lower-level circuit, and the other end of the resistors R303 and R304 is connected to the power supply; the collector of the transistor Q305 is the output end, which is connected to the collector of Q312 on the one hand, and the It is connected to one end of the load resistor R308, and at the same time, it is connected to one end of the filter capacitor C302 and fed into the lower-level circuit. The collector of the transistor Q306 is the output end, which is connected to the collector of Q311 on the one hand, and one end of the load resistor R307 on the other hand. , at the same time connect the other end of the filter capacitor C302 and feed it into the lower-level circuit, and the other ends of the resistors R307 and R308 are connected to the power supply;

The negative terminal RF- of the differential radio frequency signal is connected to one end of the resistors R305 and R306, the other ends of the resistors R305 and R306 are respectively connected to the emitters of the transistors Q307 and Q308, the bases of Q307 and Q308 are connected to the voltage signal provided by the bias module, and the collectors Connect to the emitters of transistors Q309, Q310 and Q311, Q312 respectively, the base of transistor Q309 is connected to the positive signal LO_I'+ of the local oscillator of the I branch, the base of the transistor Q310 is connected to the negative signal LO_I'- of the local oscillator of the I branch, and the transistor The base of Q311 is connected to the Q branch local oscillator positive signal LO_Q'+, the base of the switch Q312 is connected to the Q branch local oscillator negative signal LO_Q'-, the collector of the transistor Q312 is the output end, on the one hand it is connected with the collector of Q305 The electrodes are connected. On the one hand, it is connected to one end of the load resistor R308, and at the same time, it is connected to one end of the filter capacitor C302 and fed into the lower-level circuit. The collector of the transistor Q311 is the output end, which is connected to the collector of Q306 on the one hand and the load on the other hand. One end of the resistor R307 is connected, and the other end of the filter capacitor C302 is connected at the same time, and fed into the lower-level circuit, the other ends of the resistors R307 and R308 are connected to the power supply; the collector of the transistor Q309 is the output end, which is connected to the collector of Q304 on the one hand, and one On the one hand, it is connected to one end of the load resistor R304, and at the same time, it is connected to one end of the filter capacitor C301 and fed into the lower-level circuit. The collector of the transistor Q310 is the output end, which is connected to the collector of Q303 on the one hand, and one end of the load resistor R303 on the other hand. Connected, at the same time connect the other end of the filter capacitor C301, and feed it into the lower-level circuit, and the other ends of the resistors R303 and R304 are connected to the power supply.

Preferably, the positive terminal RF+ of the differential radio frequency signal is fed through the inductor L301 outside the chip to provide a DC path; the negative terminal RF- of the differential radio frequency signal is fed through the inductor L302 outside the chip to provide a DC path.

Preferably, the output driver includes four drive buffers, the input end of each drive buffer respectively receives one of the four groups of signals output by the mixer, and the output end of the drive buffer and the external port are connected by a resistance of 50 ohms. Broadband matching;

The drive buffer includes transistors Q401, Q402, resistors R401, R402, R403, R404;

The base of the transistor Q401 is the input end of the drive buffer; the collector of Q401 is connected to one end of the resistor R401, the other end of R401 is connected to the power supply, the emitter of the transistor Q401 is connected to the collector of the transistor Q402, and at the same time is connected to one end of the resistor R402, The other end of the resistor R402 is the output end of the emitter follower structure;

The base of the transistor 402 receives the voltage supplied by the bias module, and the emitter of the transistor 402 is grounded.

The advantages of the present invention compared with the prior art are:

(1), the present invention adopts the SCL two-frequency divider to realize the main function of the quadrature signal generator, and performs frequency division processing on the local oscillator signal, and the frequency band coverage is large;

(2) The structure of one-stage amplifier and two-stage emitter follower in the output buffer of the present invention not only ensures the consistency of the amplitude of the quadrature local oscillator signal, but also enhances the driving ability of the quadrature local oscillator signal.

(3), the present invention adopts bias to adjust the current working range of the mixer, and the linearity index is high;

(4) The port of the present invention adopts fixed impedance matching, which has strong versatility and low power consumption.

Description of drawings

Fig. 1 is the circuit structure schematic diagram of the present invention;

FIG. 2 is a schematic structural diagram of the quadrature signal generator 100 of the present invention;

3 is a schematic structural diagram of an input buffer in the quadrature signal generator 100 of the present invention;

4 is a schematic structural diagram of the SCL frequency divider in the quadrature signal generator 100 of the present invention;

5 is a schematic structural diagram of an output buffer in the quadrature signal generator 100 of the present invention;

FIG. 6 is a schematic structural diagram of the mixer 300 of the present invention;

FIG. 7 is a schematic structural diagram of the output driver 400 of the present invention.

Detailed ways

The present invention will be further described with reference to the accompanying drawings and design examples.

A quadrature demodulator chip designed in the present invention has an operating frequency of 30MHz to 2500MHz, an input third-order intercept point IIP3 greater than 30dB, and a power consumption of less than 160mA. Both the local oscillator and the radio frequency are differential inputs, and can provide certain conversion gain. This example can be implemented in CMOS or Bipolar. To simplify the description, the content related to transistors in this section is described in Bipolar terminology. If it is implemented by CMOS, all transistors can be replaced with MOS tubes. The quadrature demodulator of this embodiment basically realizes the conversion of signal frequency, its input is a radio frequency signal, and the output signal is a baseband signal, and the signal is down-converted by adding a local oscillator signal. The input RF signal is in the differential form; the local oscillator signal is in the differential form or single-ended form, and in the single-ended form, one end needs to be AC grounded; the output baseband signal is an IQ quadrature signal, and the frequency can be the difference between the local oscillator and the RF signal frequency.

As shown in FIG. 1 , a quadrature demodulator chip provided by the present invention includes a quadrature signal generator 100 , a bias module 200 , a mixer 300 and an output driver 400 ;

The quadrature signal generator 100 receives a differential local oscillator signal, generates a quadrature differential local oscillator signal, amplifies and limits the quadrature differential local oscillator signal, and sends it to the mixer 300, where the quadrature differential local oscillator signal is amplified and amplitude-limited. The local oscillator signals include the I branch local oscillator positive signal LO_I'+, the I branch local oscillator negative signal LO_I'-, the Q branch local oscillator positive signal LO_Q'+, and the Q branch local oscillator negative signal LO_Q'-. The signal amplitude is the same.

The bias module 200 utilizes the Bipolar characteristic to generate a temperature-invariant bias voltage signal to provide the temperature-invariant bias voltage signal to the quadrature signal generator 100, the mixer 300, and the output driver 400, respectively;

The mixer 300 receives the differential radio frequency signal input from the outside, the differential radio frequency signal includes the radio frequency positive signal RF+, the radio frequency negative signal RF-, and the differential radio frequency signal and the quadrature differential local oscillator signal transmitted by the quadrature signal generator 100 Perform the quadrature mixing operation to obtain the baseband quadrature differential current signal, convert the baseband quadrature differential current signal into a voltage signal through the resistive load, obtain the baseband quadrature differential voltage signal, and then perform low-pass filtering on the baseband quadrature differential voltage signal Then output to the output driver 400, the baseband quadrature differential voltage signal includes the I branch positive signal I+, the I branch negative signal I-, the Q branch positive signal Q+, and the Q branch negative signal Q-;

The output driver 400 isolates the baseband quadrature differential voltage signal output by the mixer 300 from the mixer 300, enhances the driving capability of the baseband quadrature differential voltage signal and realizes impedance matching, and then outputs the baseband quadrature differential voltage output signal. The frequency of the baseband quadrature differential voltage output signal is the difference between the frequency of the local oscillator signal and the differential radio frequency signal, and the baseband quadrature differential voltage output signal includes the I branch positive output signal I'+ and the I branch negative output signal I '-, Q branch output signal Q'+, Q branch negative output signal Q'-.

As another preferred solution, the bias module 200 can also provide PTAT current for any module among the three modules of the quadrature signal generator 100 , the mixer 300 and the output driver 400 by utilizing the characteristic of increased leakage at high temperature of LPNP, In order to make up for the tendency of the speed of each device to decrease at high temperature.

As shown in FIG. 2 , the quadrature signal generator 100 includes a first input buffer 111 , a second input buffer 112 , an SCL two divider 121 , a first output buffer 131 , a second output buffer 132 , a third The output buffer 133 and the fourth output buffer 134; the local oscillator input positive signal LO_in+ is connected to the first input buffer 111, the local oscillator input negative signal LO_in- is connected to the second input buffer 112, and the first input buffer 111 outputs the local oscillator The positive signal LO+, the second input buffer 112 outputs the local oscillator negative signal LO-;

The output ends of the first input buffer 111 and the second input buffer 112 are connected to the input end of the SCL frequency divider 121, and the SCL frequency divider 121 divides the local oscillator positive signal LO+ and the local oscillator negative signal LO- and outputs it after frequency division. The output terminals of the SCL frequency divider 121 are respectively connected to the input terminals of the first output buffer 131 , the second output buffer 132 , the third output buffer 133 and the fourth output buffer 134 . The output buffer 132, the third output buffer 133, and the fourth output buffer 134 amplify and limit the signal after frequency division by the SCL frequency divider 121, which are the I branch local oscillator positive signals LO_I'+, I respectively The branch LO negative signal LO_I'-, the Q branch LO positive signal LO_Q'+, the Q branch LO negative signal LO_Q'-, the I branch and the Q branch signal have a phase difference of 90° with each other at the same frequency.

As shown in FIG. 3 , the first input buffer 111 and the second input buffer 112 have the same input buffer structure;

The input end of the input buffer is connected to the base of the transistor Q111 and one end of the impedance matching element Rx, the other end of Rx is connected to the power supply, the collector of Q111 is connected to one end of the load resistor R111 and the base of the transistor Q112, and the other end of the resistor R111 is connected to Power supply, the emitter of Q111 is connected to the collector of transistor Q113, the emitter of Q113 is grounded, the collector of Q112 is connected to one end of the current limiting resistor R112, the other end of the resistor R112 is connected to the power supply, the emitter of Q112 is the output of the input buffer, It is connected to the input end of the SCL frequency divider of the latter stage and the collector of the transistor Q114, the emitter of Q114 is grounded, and the bases of Q113 and Q114 are both connected to the BIAS voltage supplied by the bias module.

As shown in FIG. 4 , the SCL two-frequency divider is used to realize the main function of the quadrature signal generator, and the SCL frequency divider 121 includes a master-level circuit and a slave-level circuit;

The main circuit includes transistors Q121, Q122, Q123, Q124, Q125, Q126, Q127, resistors R121, R122;

The slave circuit includes transistors Q221, Q222, Q223, Q224, Q225, Q226, Q227, resistors R221, R222;

In the main stage circuit, the positive signal LO+ of the local oscillator is connected to the base of the transistor Q125, the negative signal LO- of the local oscillator is connected to the base of the transistor Q126, the emitters of Q125 and Q126 are connected together and the collector of the transistor Q127 is connected , the emitter of Q127 is grounded, and the base is connected to the BIAS voltage provided by the bias module; the collector of Q125 is connected to the emitters of the differential pair transistors Q121 and Q122, and the bases of Q121 and Q122 are respectively connected to the output Q branch of the secondary circuit. Frequency local oscillator positive signal LO_Q+, Q branch frequency divided local oscillator negative signal LO_Q-, correspondingly, its collector is the output of main stage circuit I branch frequency divided local oscillator negative signal LO_I-, I branch frequency divided local oscillator The positive signal LO_I+ is used as the two output signals of the SCL frequency divider 121 on the one hand, and is connected to the bases of Q221 and Q222 of the slave circuit on the one hand, and at the same time, the collectors of the main circuit Q121 and Q122 are connected to the resistors R121 and R122 respectively. One end of the two resistors, the other end of the two resistors is connected to the power supply, in addition, the collector of Q121 is connected to the collector of transistor Q123 and the base of Q124, the collector of Q122 is connected to the collector of transistor Q124 and the base of Q123, Q123, Q124 constitute Cross-coupling structure, the emitters of the two are connected together and connected to the collector of Q126;

In the slave stage circuit, the positive signal LO+ of the local oscillator is connected to the base of the transistor Q225, the negative signal LO- of the local oscillator is connected to the base of the transistor Q226, and the emitters of Q225 and Q226 are connected together and the collector of the transistor Q227 is connected , the emitter of Q227 is grounded, and the base is connected to the BIAS voltage provided by the bias module; the collector of Q225 is connected to the emitters of the differential pair transistors Q221 and Q222, and the bases of Q221 and Q222 are respectively connected to the output I branch of the main stage circuit. The frequency local oscillator positive signal LO_I+, the I branch frequency divides the local oscillator negative signal LO_I-, correspondingly, its collector is the output of the slave stage circuit Q branch frequency divides the local oscillator negative signal LO_Q-, the Q branch frequency divides this The positive signal LO_Q+, on the one hand, is used as the two output signals of the SCL frequency divider 121, on the other hand, it is connected to the bases of Q121 and Q122 of the main stage circuit, and at the same time, the collectors of the slave stage circuits Q221 and Q222 are respectively connected to the resistors R221, One end of R222 and the other end of the two resistors are connected to the power supply. In addition, the collector of Q221 is connected to the collector of transistor Q223 and the base of Q224. The collector of Q222 is connected to the collector of transistor Q224 and the base of Q223. Q223, Q224 A cross-coupling structure is formed, and the emitters of the two are connected together and connected to the collector of Q226.

As shown in FIG. 5 , the first output buffer 131 , the second output buffer 132 , the third output buffer 133 , and the fourth output buffer 134 are all output buffer structures;

The output buffer is implemented with an emitter follower structure, including transistors Q131, Q132, Q133, Q134, Q135, Q136, Q137, Q138, and resistors R131, R132, R133, R134;

The input end of the output buffer is connected to the base of the transistor Q131, the collector of Q131 is connected to one end of the resistor R131, the other end of R131 is connected to the power supply, the emitter of Q131 is connected to the collector of the transistor Q135 and the base of the amplifier Q132, Q132 The emitter of the transistor Q136 is connected to the collector, the collector of Q132 is connected to one end of the load resistor R132 and the base of Q133, the other end of R132 is connected to the power supply, the collector of Q133 is connected to one end of the resistor R133, and the other end of R133 is connected to the power supply. The emitter of Q133 is connected to the base of Q134 and the collector of Q137, the collector of Q134 is connected to one end of the resistor R134, the other end of R134 is connected to the power supply, the emitter of Q134 is the output end of the output buffer, on the one hand it is connected to the next stage mixing The input of the frequency converter is connected to the collector of Q138 on the one hand, the emitters of Q135, Q136, Q137, and Q138 are all grounded, and the bases are all connected to the BIAS voltage supplied by the bias module.

The structure of one-stage amplifier and two-stage emitter follower in the above-mentioned output buffer not only ensures the consistency of the amplitude of the quadrature local oscillator signal, but also enhances the driving ability of the quadrature local oscillator signal.

In this embodiment, the input frequency range of the local oscillator is 60MHz～5000MHz, and the input frequency is divided by the SCL two-frequency divider after passing through the buffer placed in the quadrature signal generator 100 to obtain four channels with a phase difference of 90 degrees from each other. Local oscillator signal LO_I'+, LO_I'-, LO_Q'+, LO_Q'-;

As shown in FIG. 6 , the main body of the mixer 300 is two double-balanced mixers based on Gilbert cells, an I-branch double-balanced mixer structure and a Q-branch double-balanced mixer structure, which are respectively used for in-phase (I) and quadrature (Q) channels. in:

The structure of the I-branch double-balanced mixer includes resistor R301, resistor R302, transistors Q301, Q302, Q303, Q304, Q305, Q306, and capacitor C301;

The structure of the Q branch double-balanced mixer includes resistor R307, resistor R308, transistors Q307, Q308, Q309, Q310, Q311, Q312, and capacitor C302;

The positive terminal RF+ of the differential radio frequency signal is connected to one end of the resistors R301 and R302, the other ends of the resistors R301 and R302 are respectively connected to the emitters of the transistors Q301 and Q302, the bases of Q301 and Q302 are connected to the voltage signal provided by the bias module, and the collectors are respectively Connect to the emitters of transistors Q303, Q304 and Q305, Q306, the base of transistor Q303 is connected to I branch local oscillator positive signal LO_I'+, the base of transistor Q304 is connected to I branch local oscillator negative signal LO_I'-, transistor Q305 The base of the Q branch is connected to the positive signal LO_Q'+ of the local oscillator of the Q branch, the base of the switch Q306 is connected to the negative signal LO_Q'- of the local oscillator of the Q branch, and the collector of the transistor Q303 is the output terminal. On the one hand, it is connected to one end of the load resistor R303, and at the same time, it is connected to one end of the filter capacitor C301 and fed into the lower-level circuit. The collector of the transistor Q304 is the output end, which is connected to the collector of Q309 on the one hand, and the load resistor on the other hand. One end of R304 is connected, and the other end of the filter capacitor C301 is connected to the lower-level circuit, and the other end of the resistors R303 and R304 is connected to the power supply; the collector of the transistor Q305 is the output end, which is connected to the collector of Q312 on the one hand, and the It is connected to one end of the load resistor R308, and at the same time, it is connected to one end of the filter capacitor C302 and fed into the lower-level circuit. The collector of the transistor Q306 is the output end, which is connected to the collector of Q311 on the one hand, and one end of the load resistor R307 on the other hand. , at the same time connect the other end of the filter capacitor C302 and feed it into the lower-level circuit, and the other ends of the resistors R307 and R308 are connected to the power supply;

The negative terminal RF- of the differential radio frequency signal is connected to one end of the resistors R305 and R306, the other ends of the resistors R305 and R306 are respectively connected to the emitters of the transistors Q307 and Q308, the bases of Q307 and Q308 are connected to the voltage signal provided by the bias module, and the collectors Connect to the emitters of transistors Q309, Q3010 and Q311, Q312 respectively, the base of transistor Q309 is connected to the positive signal LO_I'+ of the local oscillator of the I branch, the base of the transistor Q310 is connected to the negative signal LO_I'- of the local oscillator of the I branch, and the transistor The base of Q311 is connected to the Q branch local oscillator positive signal LO_Q'+, the base of the switch Q312 is connected to the Q branch local oscillator negative signal LO_Q'-, the collector of the transistor Q312 is the output end, on the one hand it is connected with the collector of Q305 The electrodes are connected. On the one hand, it is connected to one end of the load resistor R308, and at the same time, it is connected to one end of the filter capacitor C302 and fed into the lower-level circuit. The collector of the transistor Q311 is the output end, which is connected to the collector of Q306 on the one hand and the load on the other hand. One end of the resistor R307 is connected, and the other end of the filter capacitor C302 is connected at the same time, and fed into the lower-level circuit, the other ends of the resistors R307 and R308 are connected to the power supply; the collector of the transistor Q309 is the output end, which is connected to the collector of Q304 on the one hand, and one On the one hand, it is connected to one end of the load resistor R304, and at the same time, it is connected to one end of the filter capacitor C301 and fed into the lower-level circuit. The collector of the transistor Q310 is the output end, which is connected to the collector of Q303 on the one hand, and one end of the load resistor R303 on the other hand. Connected, at the same time connect the other end of the filter capacitor C301, and feed it into the lower-level circuit, and the other ends of the resistors R303 and R304 are connected to the power supply.

The positive terminal RF+ of the differential RF signal is fed through the inductor L301 outside the chip to provide a DC path; the negative terminal RF- of the differential RF signal is fed through the inductor L302 outside the chip to provide a DC path.

Externally, the mixer 300 realizes the ground path through the series inductors L301 and L302. The RF input interface realizes impedance matching through the resistors R301 and R302. The RF signal is converted into a current signal through the resistors and the transconductors Q301 and Q302. Q305 and Q306 are mixed with the local oscillator signal, and the output current is added on the load resistors R303 and R304 and fed into the lower-level circuit. Filter capacitors are added to the I and Q channel outputs for bandwidth limiting.

As shown in FIG. 7 , the output driver (400) includes four drive buffers, the input end of each drive buffer receives one of the four sets of signals output by the mixer, and the output end of the drive buffer and the external port pass through The resistor realizes 50 ohm broadband matching; the output signal of this module is the same baseband voltage signal as the input signal, and the module enhances the driving ability of the signal and realizes the isolation from the front-end mixer.

The drive buffer includes transistors Q401, Q402, resistors R401, R402, R403, R404;

The base of the transistor Q401 is the input end of the drive buffer; the collector of Q401 is connected to one end of the resistor R401, the other end of R401 is connected to the power supply, the emitter of the transistor Q401 is connected to the collector of the transistor Q402, and at the same time is connected to one end of the resistor R402, The other end of the resistor R402 is the output end of the emitter follower structure;

The base of the transistor 402 receives the voltage supplied by the bias module, and the emitter of the transistor 402 is grounded.

Through the development of the above-mentioned quadrature demodulator chip, the present invention also summarizes the design method of the above-mentioned quadrature demodulator, directly aiming at the design target, from the core indicators including but not limited to the working frequency band, linearity, etc., to select and design Appropriate circuit modules, and complete the interconnection between circuit modules; on the other hand, it starts from the port definition of the design target, combines the circuit modules, and carries out layout planning according to the signal flow to complete the quadrature demodulator chip. forming.

The design method of the above quadrature demodulator specifically includes the following steps:

(1) Determine the design object, obtain the design target, analyze the working frequency band, and determine the required modules. For the quadrature demodulator, the quadrature signal generator 100 is an indispensable part; in addition, the bias module 200, Mixer 300 and output driver 400 .

(2), analyze the working frequency band, and determine the type of the quadrature signal generator 100 . The working frequency of this design example covers the low frequency, and the working frequency range is close to 2.5GHz. Considering the performance requirements and the difficulty of obtaining the input local oscillator signal, this example selects the SCL two-frequency divider to realize the main function of the quadrature signal generator; considering Considering the factor of power consumption, this example chooses the structure of one-stage amplifier and two-stage emitter follower to enhance the driving capability of the quadrature local oscillator signal. The input port of the quadrature signal generator should achieve 50 ohm broadband matching through resistance or other methods, and its main structure includes but is not limited to RC-CR type, SCL two-frequency divider type, and passive polyphase network type. In the case of wide operating frequency band or high operating frequency, in order to simplify the design, the quadrature signal generator usually chooses a high-order RC-CR structure, and then cascades several stages of amplifiers to limit and amplify the signal; the operating frequency band is low In some cases, in order to simplify the design, the quadrature signal generator can choose the SCL two-frequency divider structure; in the case of pursuing performance, the quadrature signal generator can be designed specifically.

(3) Determine the working states of the bias module 200 and the mixer 300 . The bias module 200 uses a bandgap reference source to generate bias voltage, and provides a reference voltage signal that does not change with temperature for the three parts of the quadrature signal generator 100 , the mixer 300 and the output buffer 400 . The bias module may be a bandgap reference source, and at this time, the bias module is independent of other modules, and the cascade connection between the modules is usually DC coupling.

(4) The mixer 300 selects a double-balanced structure. For the quadrature demodulator, the transconductor can be used as the input stage of the radio frequency signal, and the load is usually resistance or inductance or a combination of resistance and inductance. The radio frequency signal RF+ is converted into a current through a resistor R301 and R302 placed in the mixer 300, and then connected to the emitters of the trans-conductors Q301 and Q302 in the mixer 300, and the DC working current I1 of the trans-conductors Q301 and Q302 passes through the bias. The setting module 200 determines that, in order to improve the linearity, the DC operating current I1 can be correspondingly increased. Similarly, the radio frequency signal RF- is converted into a current through a resistor R305, R306 placed in the mixer 300, and then connected to the emitters of the trans-conduit Q307 and Q308 in the mixer 300, and the DC work across the trans-conduit Q307 and Q308 The current I1 is determined by the biasing module 200. In order to improve the linearity, the DC operating current I1 can be correspondingly increased. The load of the mixer 300 is the resistors R303, R304 and R307, R308 to realize the current-to-voltage conversion.

(5), determine the status of the output driver 400 . An analog-to-digital converter is usually connected after the quadrature demodulator. In order to enhance the driving capability of the output driver 400, an emitter-follower structure is selected. The mode is about the power supply voltage VDD minus the voltage drop of V1 (I1*R1) and the pn junction of Q401. Combined with the common mode requirements of the post-chip stage, the design information such as the DC operating current I1 of the trans-conduit Q301 and the load resistance R1 of the mixer 300 can be obtained. value. The load resistance R1 is R303 and R304, and I1 is the DC working current of Q301 and Q302. The output buffer is usually a follower structure for the quadrature demodulator, and the output can be matched by 50 ohms through resistors or other methods, and can not be matched when the output frequency is lower than 200MHz.

(6), complete the matching design of the three main signal ports of radio frequency, baseband and local oscillator, and determine the interconnection between stages. The RF input frequency range is 30MHz to 2500MHz, and its input will be converted into current through resistors R301 and R302, and then 50 ohm matching is achieved through resistors R301 and R302. The input frequency range of the local oscillator is 60MHz to 5000MHz, and the input is divided by the SCL two-frequency divider after the buffer placed in the quadrature signal generator 100 to obtain four local oscillator signals LO_I' with a phase difference of 90 degrees from each other. +, LO_I'-, LO_Q'+, LO_Q'-, the input terminal is the base of the transistor Q111, then the transistor Q111 can be biased through the resistor Rx, and 50 ohm matching can be achieved. A 50-ohm broadband matching is achieved between the output driver 400 and the external port through a resistor R402.

(7) DC coupling is adopted for the interstage connection, the voltage output of the bias module 200 is connected to the quadrature signal generator 100 , the mixer 300 and the output driver 400 , and the local oscillator signal LO_I′ of the quadrature signal generator 100 is connected +, LO_I'-, LO_Q'+, LO_Q'- are connected to the bases of the switches Q303, Q304, Q305, Q306, Q309, Q310, Q311, and Q312 in the mixer 300, and the mixer 300 is loaded with R303, R304 The voltage outputs on , R307 , R308 are connected to the output driver 400 .

(8) According to the port definition, determine the position arrangement of the three main signal ports of the radio frequency, baseband and local oscillator; arrange the local oscillator ports LO_in+, LO_in-, and the RF input ports RF+ and RF- around the chip in the opposite side. , the baseband ports I'+, I'-, Q'+, and Q'- can be arranged on one side of the chip on both sides of the chip temporarily idle. After the position of the port is determined, the layout of the circuit module is planned according to the signal flow direction, and the layout design is completed.

The index information is obtained according to the layout data, and compared with the design goal, the design is completed if it is satisfied, and the module is briefly modified if it is not satisfied.

The index information obtained in this example meets the requirements of the design objectives, the layout is solidified, and the design is completed.

The content not described in detail in the specification of the present invention belongs to the well-known technology of those skilled in the art. The above are only the preferred embodiments of the present invention. For those skilled in the art, without departing from the technical principle of the present invention, several improvements and derivatives can be made. These improvements and derivatives should be regarded as It is the protection scope of the present invention.

Claims (8)

1. A quadrature demodulator chip, comprising a quadrature signal generator (100), a bias module (200), a mixer (300) and an output driver (400);

the orthogonal signal generator (100) receives the local oscillation signals in the differential form, generates orthogonal differential local oscillation signals, amplifies and limits the orthogonal differential local oscillation signals, and sends the amplified and limited orthogonal differential local oscillation signals to the frequency mixer (300), wherein the orthogonal differential local oscillation signals comprise I branch local oscillation positive signals LO _ I '+, I branch local oscillation negative signals LO _ I' -, Q branch local oscillation positive signals LO _ Q '+, and Q branch local oscillation negative signals LO _ Q' -;

the bias module (200) is used for respectively providing bias voltage signals which do not change along with the temperature for the quadrature signal generator (100), the mixer (300) and the output driver (400);

the frequency mixer (300) receives differential radio frequency signals input from the outside, the differential radio frequency signals comprise radio frequency positive signals RF + and radio frequency negative signals RF-, the differential radio frequency signals and orthogonal differential local oscillation signals transmitted by the orthogonal signal generator (100) are subjected to frequency mixing operation to obtain baseband orthogonal differential current signals, the baseband orthogonal differential current signals are converted into voltage signals through a resistance load to obtain baseband orthogonal differential voltage signals, the baseband orthogonal differential voltage signals are subjected to low-pass filtering and then output to the output driver (400), and the baseband orthogonal differential voltage signals comprise I branch positive signals I +, I branch negative signals I-, Q branch positive signals Q +, Q branch negative signals Q-;

the output driver (400) isolates the baseband quadrature differential voltage signal output by the frequency mixer (300) from the frequency mixer (300), enhances the driving capability of the baseband quadrature differential voltage signal, realizes impedance matching and outputs the baseband quadrature differential voltage signal to obtain a baseband quadrature differential voltage output signal, wherein the frequency of the baseband quadrature differential voltage output signal is the difference between the frequencies of a local oscillator signal and a differential radio frequency signal, and the baseband quadrature differential voltage output signal comprises an I branch positive output signal I '+, an I branch negative output signal I' -, a Q branch positive output signal Q '+, and a Q branch negative output signal Q' -.

2. A quadrature demodulator chip as claimed in claim 1, characterized in that the quadrature signal generator (100) comprises a first input buffer (111), a second input buffer (112), an SCL divider (121), a first output buffer (131), a second output buffer (132), a third output buffer (133), a fourth output buffer (134);

the local oscillator input positive signal LO _ in + is connected with the first input buffer (111), the local oscillator input negative signal LO _ in-is connected with the second input buffer (112), the first input buffer (111) outputs the local oscillator positive signal LO +, and the second input buffer (112) outputs the local oscillator negative signal LO-;

the output ends of the first input buffer (111) and the second input buffer (112) are connected to the input end of an SCL frequency divider (121), the SCL frequency divider (121) divides the local oscillator positive signal LO + and the local oscillator negative signal LO-and outputs the divided local oscillator positive signal LO + and local oscillator negative signal LO-, the output end of the SCL frequency divider (121) is connected to the input ends of a first output buffer (131), a second output buffer (132), a third output buffer (133) and a fourth output buffer (134), the first output buffer (131), the second output buffer (132), the third output buffer (133) and the fourth output buffer (134) amplify and amplitude-limit the divided signals of the SCL frequency divider (121), which are respectively an I branch local oscillator positive signal LO _ I ' +, an I branch local oscillator negative signal LO _ I ' -, a Q branch local oscillator positive signal LO _ Q ' +, a Q branch local oscillator negative LO _ Q ' -, and local oscillator negative LO _ Q ' -, the I branch signal and the Q branch signal have the same frequency and are 90-degree phase difference with each other.

3. A quadrature demodulator chip as claimed in claim 2, characterised in that the first input buffer (111) and the second input buffer (112) are of the same input buffer structure;

the input end of the input buffer is connected with the base of a transistor Q111 and one end of an impedance matching element Rx, the other end of the Rx is connected with a power supply, the collector of the Q111 is connected with one end of a load resistor R111 and the base of a transistor Q112, the other end of the resistor R111 is connected with the power supply, the emitter of the Q111 is connected with the collector of the transistor Q113, the emitter of the Q113 is grounded, the collector of the Q112 is connected with one end of a current limiting resistor R112, the other end of the resistor R112 is connected with the power supply, the emitter of the Q112 is the output end of the input buffer and is connected with the input end of a later-stage SCL frequency divider and the collector of the transistor Q114, the emitter of the Q114 is grounded, and the bases of the Q113 and the Q114 are both connected with a BIAS voltage supplied by the BIAS module.

4. A quadrature demodulator chip as claimed in claim 2, characterised in that the SCL divider (121) comprises a master stage circuit and a slave stage circuit;

the main stage circuit comprises transistors Q121, Q122, Q123, Q124, Q125, Q126 and Q127 and resistors R121 and R122;

the slave stage circuit comprises transistors Q221, Q222, Q223, Q224, Q225, Q226 and Q227 and resistors R221 and R222;

in the main-stage circuit, a local oscillator positive signal LO + is connected to the base of a transistor Q125, a local oscillator negative signal LO-is connected to the base of a transistor Q126, the emitters of the transistors Q125 and Q126 are connected together and connected with the collector of a transistor Q127, the emitter of the transistor Q127 is grounded, and the base is connected with BIAS voltage provided by a BIAS module; the collector of Q125 is connected to the emitters of the differential pair transistors Q121, Q122, the bases of Q121 and Q122 are respectively connected to the divided local oscillator positive signal LO _ Q + of the Q branch, the divided local oscillator negative signal LO _ Q-, of the Q branch, corresponding, the collectors of the two-way frequency division local oscillator negative signal LO _ I and the I-way frequency division local oscillator positive signal LO _ I + are used as two output signals of the SCL frequency divider (121) and are connected to the bases of Q221 and Q222 of the slave stage circuit, meanwhile, the collectors of the main-stage circuits Q121 and Q122 are respectively connected with one ends of the resistors R121 and R122, the other ends of the two resistors are connected with a power supply, in addition, the collector of the transistor Q121 is connected with the collector of the transistor Q123 and the base of the transistor Q124, the collector of the transistor Q122 is connected with the collector of the transistor Q124 and the base of the transistor Q123, the transistors Q123 and Q124 form a cross coupling structure, and the emitters of the two are connected together and connected with the collector of the transistor Q126;

in the slave stage circuit, a local oscillator positive signal LO + is connected to the base electrode of a transistor Q225, a local oscillator negative signal LO-is connected to the base electrode of a transistor Q226, the emitter electrodes of the transistor Q225 and the transistor Q226 are connected together and connected with the collector electrode of a transistor Q227, the emitter electrode of the transistor Q227 is grounded, and the base electrode is connected with BIAS voltage provided by a BIAS module; the collector of Q225 is connected with the emitters of the differential pair transistors Q221, Q222, the bases of Q221 and Q222 are respectively connected with the output I branch frequency division local oscillation positive signal LO _ I + and the I branch frequency division local oscillation negative signal LO _ I-of the primary circuit, correspondingly, the collectors of the two signals are the output Q branch frequency division local oscillation negative signal LO _ Q-, Q branch frequency division local oscillation positive signal LO _ Q + of the slave stage circuit, on one hand, the two output signals are used as two output signals of the SCL frequency divider (121), on the other hand, the two output signals are connected to the bases of Q121 and Q122 of the master stage circuit, meanwhile, the collectors of the slave stage circuits Q221 and Q222 are respectively connected with one ends of the resistors R221 and R222, the other ends of the two resistors are connected with a power supply, the collector of the transistor Q221 is connected with the collector of the transistor Q223 and the base of the transistor Q224, the collector of the transistor Q222 is connected with the collector of the transistor Q224 and the base of the transistor Q223, the transistors Q223 and Q224 form a cross-coupling structure, and the emitters of the two are connected together and connected with the collector of the transistor Q226.

5. A quadrature demodulator chip as claimed in claim 2, characterised in that the first output buffer (131), the second output buffer (132), the third output buffer (133) and the fourth output buffer (134) are all of the same output buffer structure;

the output buffer comprises transistors Q131, Q132, Q133, Q134, Q135, Q136, Q137 and Q138, resistors R131, R132, R133 and R134;

the input end of the output buffer is connected to the base of the transistor Q131, the collector of the transistor Q131 is connected to one end of the resistor R131, the other end of the resistor R131 is connected to the power supply, the emitter of the transistor Q131 is connected to the collector of the transistor Q135 and the base of the amplifying tube Q132, the emitter of the transistor Q132 is connected to the collector of the transistor Q136, the collector of the transistor Q132 is connected to one end of the load resistor R132 and the base of the load resistor Q133, the other end of the resistor R132 is connected to the power supply, the collector of the transistor Q133 is connected to one end of the resistor R133, the emitter of the transistor Q133 is connected to the power supply, the collector of the transistor Q134 is connected to one end of the resistor R134, the other end of the transistor R134 is connected to the power supply, the emitter of the transistor Q134 is connected to the output end of the output buffer, the input end of the next-stage mixer is connected to the input end, the collectors of the transistor Q138 are all grounded, and the bases are connected to the BIAS voltage supplied by the BIAS module.

6. A quadrature demodulator chip as claimed in claim 1, characterised in that the mixer (300) comprises an I-branch double balanced mixer structure and a Q-branch double balanced mixer structure; wherein:

the I-branch double-balanced mixer structure comprises a resistor R301, a resistor R302, transistors Q301, Q302, Q303, Q304, Q305 and Q306 and a capacitor C301;

the Q-branch double-balanced mixer structure comprises a resistor R307, a resistor R308, transistors Q307, Q308, Q309, Q310, Q311, Q312 and a capacitor C302;

the positive terminal RF + of the differential radio frequency signal is connected with one end of the resistors R301 and R302, the other ends of the resistors R301 and R302 are respectively connected with the emitters of the transistors Q301 and Q302, the bases of the transistors Q301 and Q302 are connected with the voltage signal provided by the bias module, the collectors are respectively connected with the emitters of the transistors Q303, Q304, Q305 and Q306, the base of the transistor Q303 is connected with the I branch local oscillator positive signal LO _ I '+, the base of the transistor Q304 is connected with the I branch local oscillator negative signal LO _ I' -, the base of the transistor Q305 is connected with the Q branch local oscillator positive signal LO _ Q '+, the base of the switching tube Q306 is connected with the Q branch local oscillator negative signal LO _ Q' -, the collector of the transistor Q303 is the output terminal, one side of the collector of the transistor Q303 is connected with the collector of the Q310, one side of the load resistor R303 is connected with one end of the filter capacitor C301, and the collector of the transistor Q304 is fed into the next stage circuit, the collector of the output terminal of the transistor Q304, one end of the filter capacitor is connected with the collector of the Q309, the other end of the filter capacitor C301 is connected with one end of the load resistor R304, the other end of the filter capacitor C301 is fed into a lower-level circuit, and the other ends of the resistors R303 and R304 are connected with a power supply; the collector of the transistor Q305 is an output end, which is connected with the collector of the Q312, the load resistor R308, the filter capacitor C302 and the lower circuit, the collector of the transistor Q306 is an output end, which is connected with the collector of the Q311, the load resistor R307, the filter capacitor C302 and the lower circuit, the resistors R307 and R308 are connected with the power supply;

the negative terminal RF-of the differential radio frequency signal is connected with one end of a resistor R305 and a resistor R306, the other end of the resistor R305 and the other end of the resistor R306 are respectively connected with the emitter of a transistor Q307 and the emitter of a transistor Q308, the base of the transistor Q307 and the base of the transistor Q308 are connected with the voltage signal provided by a bias module, the collector is respectively connected with the emitter of a transistor Q309, a transistor Q310 and the emitter of a transistor Q312, the base of the transistor Q309 is connected with an I branch local oscillator positive signal LO _ I '+, the base of the transistor Q310 is connected with an I branch local oscillator negative signal LO _ I' -, the base of the transistor Q311 is connected with a Q branch local oscillator positive signal LO _ Q '+, the base of the switching tube Q312 is connected with a Q branch local oscillator negative signal LO _ Q' -, the collector of the transistor Q312 is an output terminal, one end of the transistor Q312 is connected with the collector of the load resistor R308, one end of the filter capacitor C302 and is fed into a lower circuit, the collector of the transistor Q311 is an output terminal, one end of the resistor is connected with a collector of the Q306, the other end of the resistor is connected with one end of a load resistor R307, the other end of the load resistor R307 is connected with the other end of the filter capacitor C302 and is fed into a lower circuit, and the other ends of the resistors R307 and R308 are connected with a power supply; the collector of the transistor Q309 is an output terminal, which is connected to the collector of the transistor Q304, to one end of the load resistor R304, to one end of the filter capacitor C301, and fed to the next stage circuit, the collector of the transistor Q310 is an output terminal, which is connected to the collector of the transistor Q303, to one end of the load resistor R303, to the other end of the filter capacitor C301, and fed to the next stage circuit, and the other ends of the resistors R303 and R304 are connected to a power supply.

7. A quadrature demodulator chip as claimed in claim 6, characterised in that the positive terminal RF + of the differential radio frequency signal is fed through the inductor L301 to ground outside the chip, providing a DC path; the negative terminal RF-of the differential RF signal is fed through the inductor L302 to ground outside the chip, providing a DC path.

8. A quadrature demodulator chip as claimed in claim 1, wherein the output driver (400) comprises four driving buffers, each driving buffer having an input for receiving one of the four sets of signals outputted by the mixer, and an output of the driving buffer being coupled to the external port via a resistor to implement 50 ohm wide band matching;

the driving buffer comprises transistors Q401 and Q402, resistors R401, R402, R403 and R404;

the base of the transistor Q401 is the input end of the driving buffer; the collector of the transistor Q401 is connected with one end of the resistor R401, the other end of the resistor R401 is connected with a power supply, the emitter of the transistor Q401 is connected with the collector of the transistor Q402 and is simultaneously connected with one end of the resistor R402, and the other end of the resistor R402 is the output end of the emitter follower structure;

the base of transistor 402 receives the voltage supplied by the bias module and the emitter of transistor 402 is grounded.

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