CN114416614B - Interrupt processing module for protecting field and recovering field - Google Patents
Interrupt processing module for protecting field and recovering field Download PDFInfo
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- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
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Abstract
The invention discloses an interrupt processing module for protecting and recovering a site, which comprises a DMA read-write instruction generating unit, a DMA unit and a processor core internal register access unit, wherein the DMA read-write instruction generating unit is connected with the DMA unit, the DMA unit is in bidirectional connection with the processor core internal register access unit and a memory, and the processor core internal register access unit is in bidirectional connection with a processor core internal register. The invention realizes the data movement between the internal register of the processor core and the internal memory by the mutual coordination of the internal register access unit of the processor core and the DMA unit, does not need to use a general register as a bridge for moving data, saves the time required by protecting the site and recovering the site, and reduces the code volumes of the protecting site and the recovering site.
Description
Technical Field
The invention relates to the technical field of interrupt processing of processors, in particular to an interrupt processing module for protecting a site and recovering the site.
Background
When an interrupt occurs, the processor will save the data in the internal registers of the processor core in the current state to the memory, and this behavior of the processor is referred to as "protection field" in the present application. The prior art processor protects the process in the field: 1. the processor takes out the data in the control register and the status register in the inner core and stores the data into the general register; 2. the processor then saves the data in the general register to the memory.
When the interrupt processing is finished, the processor restores the data to be restored in the memory to the corresponding register in the processor core, and the action of the processor is called as 'restoration site'. The prior art processor resumes the process of the scene: 1. the processor takes out the data to be recovered in the memory and stores the data to be recovered in the general register in the processor core; 2. and the processor restores the data to be restored in the general register to the corresponding control register and the corresponding state register in the processor core.
Accordingly, the prior art processor protects/restores the field using the general purpose registers as a bridge for transferring data between the control/status registers and the memory. If the data movement between the control/status register and the memory can be directly realized, the time required for transmitting data from the control/status register to the general register in the protection field and the time required for transmitting data from the general register to the control/status register in the recovery field are saved, the time required for protecting the field and the recovery field is greatly shortened, and the code volumes of the protection field and the recovery field are reduced.
Disclosure of Invention
In order to solve the above problems of the conventional interrupt processing technology of a processor, the present invention provides an interrupt processing module for protecting a site and recovering a site, which can reduce the code volume and shorten the time required for protecting the site and recovering the site.
The interrupt processing module for protecting the site and recovering the site comprises a DMA read-write instruction generating unit, a DMA unit and a processor core internal register access unit, wherein the DMA read-write instruction generating unit is connected with the DMA unit, the DMA unit is in bidirectional connection with the processor core internal register access unit and a memory, and the processor core internal register access unit is in bidirectional connection with a processor core internal register;
the DMA read-write instruction generating unit is used for sending a DMA read-write starting instruction to the DMA unit according to the DMA read-write assembly instruction;
The DMA unit is used for receiving a DMA read/write starting instruction and starting DMA read/write operation; the DMA write operation refers to that an access unit of an internal register of a processor core reads out data to be protected in the internal register of the processor core, returns the data to the DMA unit and writes the data into a memory by the DMA unit; the DMA read operation means that the DMA unit reads out the data to be recovered in the memory and writes the data into the corresponding internal register of the processor core by the internal register access unit of the processor core;
And the processor core internal register access unit is used for reading and recovering data in the processor core internal register in cooperation with the DMA unit, wherein the processor core internal register is uniformly coded and the address space is continuous.
Further, the DMA unit initiates a DMA write operation comprising sending a data fetch command to a processor core internal register access unit and sending a write data command to a memory; the DMA unit initiates a DMA read operation that includes sending a read data command to the memory and a data recovery command to the processor core internal register access circuitry.
Further, the specific workflow of the interrupt handling module for protecting and restoring the site includes the steps of:
Step 1, when an interrupt occurs, a processor jumps to an interrupt entry, executes a DMA write assembly instruction and starts to protect a site;
Step 2, the DMA write assembly instruction triggers a DMA read-write instruction generating unit to set a dmawrstart mark;
Step 3, the DMA unit monitors a dma_wr_start mark, starts DMA write operation, and sends a data access command to a register access unit in the processor core, wherein the data access command comprises a register read instruction and a register read address;
Step 4, after receiving the data access command, the register access unit in the processor core returns the data in the register of the corresponding address to the DMA unit according to the register read address in the data access command;
Step 5, the DMA unit writes the received data into the memory;
Step 6, judging whether the protection site is over, if so, entering step 7, otherwise, jumping to step 4;
step 7, the DMA read-write instruction generating unit clears the dma_wr_start mark, and the processor starts to process interrupt;
step 8, after the processor finishes processing the interrupt, executing a DMA read assembly instruction and starting to recover the site;
step 9, the DMA read assembly instruction triggers the DMA read-write instruction generating unit to set a dmard start mark;
Step 10, the DMA unit monitors a dmard start mark and starts DMA reading operation;
Step 11, the DMA unit reads the data to be recovered in the memory and sends a data recovery command to a register access unit in the processor core, wherein the data recovery command comprises a register write instruction, a register write address and register write data;
step 12, after receiving the data recovery command, the access unit of the internal register of the processor core recovers the data to be recovered to the register of the corresponding address according to the register write address in the data recovery command;
Step 13, judging whether the recovery site is finished, if so, entering step 14, otherwise, jumping to step 11;
In step 14, the dma read/write command generating unit clears the dma_rd_start flag, and the processor executes the interrupt return command to exit the interrupt.
Further, the processor core internal register access unit comprises a register reduction unit, wherein the register reduction unit is used for uniformly reducing data and data effective signals of all the processor core internal registers into x paths of data and data effective signals, wherein x is a positive integer less than the number of the processor core internal registers;
The processor core internal register access unit selects effective data and data effective signals from x paths of data and data effective signals reduced by the register reduction unit and returns the effective data and the data effective signals to the DMA unit, wherein the data effective signals are logical OR of the x paths of data effective signals reduced by the register reduction circuit, and the effective data is selected from the x paths of data reduced by the register reduction circuit by utilizing the x paths of data effective signals reduced by the register reduction circuit.
The invention realizes the data movement between the internal register of the processor core and the internal memory by the mutual coordination of the internal register access unit of the processor core and the DMA unit, does not need to use a general register as a bridge for moving data, saves the time required by protecting the site and recovering the site, and reduces the code volumes of the protecting site and the recovering site.
Drawings
FIG. 1 is a block diagram and signal flow diagram of an interrupt handling module for protecting and restoring a site;
FIG. 2 is a particular workflow diagram of an interrupt handling module for protecting and restoring a site;
FIG. 3 is a code volume comparison of two processor interrupt handling approaches of the prior art and the present invention.
Detailed Description
The invention will be described in further detail with reference to the drawings and the detailed description. The embodiments of the invention have been presented for purposes of illustration and description, and are not intended to be exhaustive or limited to the invention in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, and to enable others of ordinary skill in the art to understand the invention for various embodiments with various modifications as are suited to the particular use contemplated.
Example 1
An interrupt processing module for protecting the site and recovering the site is shown in figure 1, and comprises a DMA read-write instruction generating unit, a DMA unit and a processor core internal register access unit, wherein the DMA read-write instruction generating unit is connected with the DMA unit, the DMA unit is in bidirectional connection with the processor core internal register access unit and a memory, and the processor core internal register access unit is in bidirectional connection with a processor core internal register.
And the DMA read-write instruction generating unit is used for sending a DMA read-write starting instruction to the DMA unit according to the DMA read-write assembly instruction.
The specific workflow of the DMA read-write instruction generating unit is as follows:
1. When an interrupt occurs, the processor jumps to an interrupt entry, executes a DMA write assembly instruction, and starts to protect the site;
2. The DMA write assembly instruction triggers the DMA read-write instruction generating unit to set a dma_wr_start mark, so that the DMA unit starts DMA write operation and performs interrupt protection field operation;
3. After the interrupt protection field operation is finished, the DMA read-write instruction generating unit clears the dmawrstart mark, and the processor starts to process the interrupt;
4. After the processor processes the interrupt, the processor executes a DMA read assembly instruction and starts to recover the site;
5. The DMA read assembly instruction triggers the DMA read-write instruction generating unit to set a dma_rd_start mark, so that the DMA unit starts DMA read operation to perform interrupt recovery field operation;
6. After the on-site operation of the interrupt recovery is finished, the DMA read-write instruction generating unit clears the dmard start mark, and the processor executes the interrupt return instruction and exits the interrupt.
The DMA unit receives a DMA read/write initiation instruction for sending a DMA read/write operation to the processor core internal register access unit, wherein sending the DMA read operation includes sending a read data command to the memory and sending a data recovery command to the processor core internal register access unit, and sending the DMA write operation includes sending a get data command to the processor core internal register access unit and sending a write data command to the memory.
The specific workflow of the DMA unit is as follows:
1. Interrupt protection field stage
① The DMA unit monitors a dmawrstart mark, starts DMA write operation, and sends a data access command to a register access unit in the processor core, wherein the data access command comprises a register read instruction (reg_rd) and a register read address (reg_raddr);
② After receiving the data access command, the register access unit in the processor core returns the data (reg_rdata) and the data valid signal (reg_rdata_vld) thereof in the register of the corresponding address to the DMA unit according to the register read address (reg_raddr) in the data access command;
③ After receiving the reg_rdata and the reg_rdata_vld, the DMA unit converts the reg_rdata, reg_rdata_vld signals and the memory address into a write data command (including a write command wr_cmd, write data wdata and a data valid signal wdata _vld), writes the data into the memory, and completes the operation of interrupting the protection field.
2. Interrupt resume live phase
① The DMA unit monitors a dmard start mark, starts DMA read operation, sends out a read data command (rd_cmd) to the memory, reads out data to be recovered (rdata) and a data valid signal (rdata_vld), converts the read data and the read data into a data recovery command (comprising a register write command reg_wr, a register write address reg_ waddr and register write data reg_ wdata) and transmits the data recovery command to a register access unit in the processor core;
② And after receiving the data recovery command, the register access unit in the processor core recovers the data to be recovered to the register of the corresponding address, and completes the operation of interrupting the recovery site.
And the processor core internal register access unit is used for receiving the data access/data recovery command sent by the DMA unit, the data and data effective signals of each register returned by the processor core internal register access unit, and sending the data access/data recovery command to the read/write port of each register in the processor core, wherein the registers in the processor core are uniformly coded and the address space is continuous.
The specific workflow of the internal register access unit of the processor core is as follows:
1. Interrupt protection field stage
① After receiving the data access commands (reg_rd and reg_raddr), the register access unit in the processor core sends the data access commands (reg_rd and reg_raddr) to a read port of each register in the processor core;
② After the register of the corresponding address in the processor core receives the data fetching command (reg_rd, reg_raddr), data (reg_rdata_x, x=0, 1,2, …, n) of the registers in the processor core and data valid signals (reg_rdata_vld_x, x=0, 1,2, …, n; active high level) of the registers in the processor core are returned to the processor core internal register access unit;
③ The register reduction circuit reduces the data reg_rdata_0, reg_rdata_1, …, reg_rdata_n-1, reg_rdata_n, and the data valid signals reg_rdata_vld_0, reg_rdata_vld_1, … for the n processor core internal registers, reg_rdata_vld_n-1 reg_rdata_vld_n is reduced to 3-way data reg_rdata_00, reg_rdata_11 reg_rdata_vld_n is reduced to 3-way data reg_rdata_00 reg_rdata_11;
④ The processor core internal register access unit selects corresponding effective data through 3 paths of data effective signals reg_rdata_vld_00, reg_rdata_vld_11 and reg_rdata_vld_22 to generate effective data reg_rdata;
⑤ The processor core internal register access unit performs OR operation on 3 data valid signals reg_rdata_vld_00, reg_rdata_vld_11 and reg_rdata_vld_22 to generate a data valid signal reg_rdata_vld;
⑥ The processor core internal register access unit returns valid data reg_rdata and a data valid signal reg_rdata_vld to the DMA unit.
2. Interrupt resume live phase
After receiving the data recovery commands (reg_wr, reg_waddr, reg_ wdata), the processor core internal register access unit sends the data recovery commands (reg_wr, reg_waddr, reg_ wdata) to the write port of each register in the processor core, and writes the data to be recovered reg_ wdata into the register of the corresponding address.
In combination, the specific workflow of the interrupt handling module for protecting and restoring a site, as shown in fig. 2, includes the following steps:
Step 1, when an interrupt occurs, a processor jumps to an interrupt entry, executes a DMA write assembly instruction and starts to protect a site;
Step 2, the DMA write assembly instruction triggers a DMA read-write instruction generating unit to set a dmawrstart mark;
Step 3, the DMA unit monitors a dma_wr_start mark, starts DMA write operation, and sends a data access command to a register access unit in the processor core, wherein the data access command comprises a register read instruction and a register read address;
Step 4, after receiving the data access command, the register access unit in the processor core returns the data in the register of the corresponding address to the DMA unit according to the register read address in the data access command;
Step 5, the DMA unit writes the received data into the memory;
Step 6, judging whether the protection site is over, if so, entering step 7, otherwise, jumping to step 4;
step 7, the DMA read-write instruction generating unit clears the dma_wr_start mark, and the processor starts to process interrupt;
step 8, after the processor finishes processing the interrupt, executing a DMA read assembly instruction and starting to recover the site;
step 9, the DMA read assembly instruction triggers the DMA read-write instruction generating unit to set a dmard start mark;
Step 10, the DMA unit monitors a dmard start mark and starts DMA reading operation;
Step 11, the DMA unit reads the data to be recovered in the memory and sends a data recovery command to a register access unit in the processor core, wherein the data recovery command comprises a register write instruction, a register write address and register write data;
step 12, after receiving the data recovery command, the access unit of the internal register of the processor core recovers the data to be recovered to the register of the corresponding address according to the register write address in the data recovery command;
Step 13, judging whether the recovery site is finished, if so, entering step 14, otherwise, jumping to step 11;
In step 14, the dma read/write command generating unit clears the dma_rd_start flag, and the processor executes the interrupt return command to exit the interrupt.
The technical effects achieved by the present invention are demonstrated below in connection with specific examples, assuming that 1000 registers are to be protected inside the processor core, each register having a data bit width of 32 bits, and each cycle of transmission data bit width of 256 bits, i.e., 832 bits.
1. Interrupt processing mode of existing processor
The required time to move the data in the control and status registers to the general purpose registers is 1000/8=125 clock cycles; the required time for moving the data to be protected in the general register to the memory is 1000/8=125 clock cycles; the required time for moving the data to be restored in the memory to the general register is 1000/8=125 clock cycles; the required time to move the data to be restored in the general purpose registers to the control registers and the status registers is 1000/8=125 clock cycles. Thus, the time required to interrupt the protected site is 250 clock cycles and the time required to interrupt the recovered site is 250 clock cycles.
2. The interrupt processing mode of the processor provided by the invention
The DMA read-write instruction generating unit sends a DMA read-write starting instruction to the DMA unit, and the time required for starting DMADMA read-write operation is 4 clock cycles; the DMA write operation takes 1000/8=125 clock cycles to move the data in the internal registers of the processor core to memory; the DMA read operation takes 1000/8=125 clock cycles to move the data to be restored in the memory to the corresponding registers within the processor core. Thus, the time required to interrupt the protected site is 129 clock cycles and the time required to interrupt the recovered site is 129 clock cycles.
Compared with the prior art, the invention greatly saves the time required for protecting the site and recovering the site. Code pairs of the two processor interrupt handling modes are shown in fig. 3, from which it is also apparent that the code volumes of the protection site and the restoration site are reduced.
Each operation of the processor core internal register access unit is directed to the read/write ports of all the processor core internal registers to be protected. When the internal register access unit of the processor core writes data into a register, the register write data reg_ wdata can be written into only the register with the same address as the register write address reg_ waddr in the data recovery command; similarly, when the register access unit in the processor core reads data from the register, only the register with the same address as the register read address reg_raddr in the data fetch command returns valid data and valid (high-level) data valid signals, and then the data in the register to be read by the DMA unit can be screened out through the data valid signals fed back by each register.
According to this principle, the above screening is implemented by using a register reduction unit, where the register reduction unit is configured to reduce the data and the data valid signals of all the registers in the processor core into x paths of data and data valid signals, where x is a positive integer less than the number of registers in the processor core. In this embodiment, x=3 corresponds to 1-way control register data, 1-way status register data, and 1-way general register data, respectively. In this process, the data in the register corresponding to the address must be among the 3 paths of data.
The processor core internal register access unit selects effective data and data effective signals from 3 paths of data and data effective signals reduced by the register reduction unit and returns the effective data and the data effective signals to the DMA unit, wherein the data effective signals are logical OR of 3 paths of data effective signals reduced by the register reduction circuit, and the effective data is selected from 3 paths of data reduced by the register reduction circuit by utilizing the 3 paths of data effective signals (only 1 path is high level).
The above method for screening 1-path effective data from n-path data can be realized based on the prior art, and is not described herein.
It will be apparent that the described embodiments are only some, but not all, embodiments of the invention. All other embodiments, which can be made by those skilled in the art and which are included in the embodiments of the present invention without the inventive step, are intended to be within the scope of the present invention.
Claims (4)
1. The interrupt processing module for protecting the site and recovering the site is characterized by comprising a DMA read-write instruction generating unit, a DMA unit and a processor core internal register access unit, wherein the DMA read-write instruction generating unit is connected with the DMA unit, the DMA unit is in bidirectional connection with the processor core internal register access unit and a memory, and the processor core internal register access unit is in bidirectional connection with a processor core internal register;
the DMA read-write instruction generating unit is used for sending a DMA read-write starting instruction to the DMA unit according to the DMA read-write assembly instruction;
The DMA unit is used for receiving a DMA read/write starting instruction and starting DMA read/write operation; the DMA write operation refers to that an access unit of an internal register of a processor core reads out data to be protected in the internal register of the processor core, returns the data to the DMA unit and writes the data into a memory by the DMA unit; the DMA read operation means that the DMA unit reads out the data to be recovered in the memory and writes the data into the corresponding internal register of the processor core by the internal register access unit of the processor core;
And the processor core internal register access unit is used for reading and recovering data in the processor core internal register in cooperation with the DMA unit, wherein the processor core internal register is uniformly coded and the address space is continuous.
2. The interrupt handling module for use in protecting and resuming a field according to claim 1, wherein the DMA unit initiating a DMA write operation includes sending a data fetch command to a processor core internal register access unit and sending a write data command to memory; the DMA unit initiates a DMA read operation that includes sending a read data command to the memory and a data recovery command to the processor core internal register access circuitry.
3. The interrupt handling module for protecting and resuming a site according to claim 2, wherein the specific workflow includes the steps of:
Step 1, when an interrupt occurs, a processor jumps to an interrupt entry, executes a DMA write assembly instruction and starts to protect a site;
Step 2, the DMA write assembly instruction triggers a DMA read-write instruction generating unit to set a dmawrstart mark;
Step 3, the DMA unit monitors a dma_wr_start mark, starts DMA write operation, and sends a data access command to a register access unit in the processor core, wherein the data access command comprises a register read instruction and a register read address;
Step 4, after receiving the data access command, the register access unit in the processor core returns the data in the register of the corresponding address to the DMA unit according to the register read address in the data access command;
Step 5, the DMA unit writes the received data into the memory;
Step 6, judging whether the protection site is over, if so, entering step 7, otherwise, jumping to step 4;
step 7, the DMA read-write instruction generating unit clears the dma_wr_start mark, and the processor starts to process interrupt;
step 8, after the processor finishes processing the interrupt, executing a DMA read assembly instruction and starting to recover the site;
step 9, the DMA read assembly instruction triggers the DMA read-write instruction generating unit to set a dmard start mark;
Step 10, the DMA unit monitors a dmard start mark and starts DMA reading operation;
Step 11, the DMA unit reads the data to be recovered in the memory and sends a data recovery command to a register access unit in the processor core, wherein the data recovery command comprises a register write instruction, a register write address and register write data;
step 12, after receiving the data recovery command, the access unit of the internal register of the processor core recovers the data to be recovered to the register of the corresponding address according to the register write address in the data recovery command;
Step 13, judging whether the recovery site is finished, if so, entering step 14, otherwise, jumping to step 11;
In step 14, the dma read/write command generating unit clears the dma_rd_start flag, and the processor executes the interrupt return command to exit the interrupt.
4. An interrupt processing module for use in protecting and recovering a field according to any one of claims 1-3, wherein the processor core internal register access unit includes a register reduction unit for uniformly reducing data and data valid signals of all processor core internal registers to x-way data and data valid signals, where x is a positive integer less than the number of processor core internal registers;
The processor core internal register access unit selects effective data and data effective signals from x paths of data and data effective signals reduced by the register reduction unit and returns the effective data and the data effective signals to the DMA unit, wherein the data effective signals are logical OR of the x paths of data effective signals reduced by the register reduction circuit, and the effective data is selected from the x paths of data reduced by the register reduction circuit by utilizing the x paths of data effective signals reduced by the register reduction circuit.
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