CN114373676A - Manufacturing method of planar VDMOS device double-gate structure - Google Patents
Manufacturing method of planar VDMOS device double-gate structure Download PDFInfo
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- CN114373676A CN114373676A CN202210051895.6A CN202210051895A CN114373676A CN 114373676 A CN114373676 A CN 114373676A CN 202210051895 A CN202210051895 A CN 202210051895A CN 114373676 A CN114373676 A CN 114373676A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 16
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 45
- 229920005591 polysilicon Polymers 0.000 claims abstract description 44
- 238000000034 method Methods 0.000 claims abstract description 30
- 125000006850 spacer group Chemical group 0.000 claims abstract description 29
- 230000009977 dual effect Effects 0.000 claims abstract description 17
- 238000005530 etching Methods 0.000 claims abstract description 14
- 238000000151 deposition Methods 0.000 claims abstract description 5
- 150000004767 nitrides Chemical class 0.000 claims description 11
- 210000000746 body region Anatomy 0.000 claims description 9
- 238000001039 wet etching Methods 0.000 claims description 6
- 230000003647 oxidation Effects 0.000 claims description 2
- 238000007254 oxidation reaction Methods 0.000 claims description 2
- 238000001746 injection moulding Methods 0.000 abstract description 5
- 230000015556 catabolic process Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 238000012876 topography Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66484—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with multiple gate, at least one gate being an insulated gate
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
The invention discloses a manufacturing method of a plane type VDMOS device double-gate structure, wherein an ONO structure is formed on the surface of an epitaxial layer; arranging a first mask above the second oxide layer, wherein the arrangement position of the first mask is matched with the position of the double grid; the second oxide layer left under the first mask is a double-grid interval oxide layer; depositing polysilicon over the second oxide layer and the dual-gate spacer oxide layer; and etching back the polysilicon to expose the surface of the dual-gate interval oxide layer, and leaving polysilicon side walls on two sides of the dual-gate interval oxide layer, wherein the polysilicon side walls are of a dual-gate structure of the planar VDMOS device. The dual-gate spacer oxide layer fills the spacer region between the dual gates before the dual-gate structure is formed, so that the position of the dual-gate structure can be accurately controlled, the self-alignment of body injection molding can be realized, the process steps are saved, and the cost is saved.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a manufacturing method of a planar VDMOS device double-gate structure.
Background
In power applications, VDMOS devices may be used in power supplies, buck converters, and low voltage motor controllers to provide power application functionality.
On-resistance R of the deviceONMaximum breakdown voltage BVDSSAnd total capacitance are important characteristics of a VDMOS design. These characteristics are important operating parameters of VDMOS devices that determine the applications for which these devices are used. The on-resistance generally depends on the design and layout of the device, process conditions, temperature, drift region length, doping concentration of the drift region, and the various materials used to fabricate the device. The breakdown voltage is defined as the maximum reverse voltage that can be applied to the drain of a transistor without causing an exponential increase in current. Also, various parasitic capacitances in the device can result in a decrease in the operating frequency.
Chinese patent application CN103035726A discloses a double-gate VDMOS device comprising a double-gate structure including a first gate region and a second gate region defining a gap between the first gate region and the second gate region to reduce a gate-drain capacitance Cgd.
In the manufacturing method of the dual gate structure disclosed in the above patent, a mask is used once when the dual gate structure is formed, and when a P body region is formed by injection, since a spacing region is left between the dual gate structures, the self-aligned injection molding of the P body region cannot be completed by directly using the gate, an additional mask is required to assist in completing the injection molding of the P body region, or an additional process step is required to fill the spacing region left between the dual gate structures, which undoubtedly increases the production cost.
Disclosure of Invention
The present invention is directed to a method for fabricating a planar double-gate structure of a VDMOS device to solve the above-mentioned problems.
In order to achieve the above object, an aspect of the present invention provides a method for manufacturing a planar VDMOS device dual-gate structure, including the following steps:
forming an ONO structure of a first oxide layer, a nitride layer and a second oxide layer on the surface of an epitaxial layer of the planar VDMOS device;
arranging a first mask above the second oxide layer, wherein the arrangement position of the first mask is matched with the position of the double grid;
etching the second oxide layer and the nitride layer, wherein the second oxide layer left under the first mask is a double-gate interval oxide layer;
removing the first mask;
depositing polysilicon over the second oxide layer and the dual-gate spacer oxide layer;
and etching back the polysilicon to expose the surface of the dual-gate interval oxide layer, namely completely etching the polysilicon on the surface of the dual-gate interval oxide layer, and leaving polysilicon side walls on two sides of the dual-gate interval oxide layer, wherein the polysilicon side walls are of a dual-gate structure of the planar VDMOS device.
Preferably, the thickness of the first oxide layer is 800-1200A, the thickness of the nitride layer is 200-500A, and the thickness of the second oxide layer is 5000-10000A.
Preferably, the second oxide layer and the nitride layer are etched by a wet etching method with a high selectivity ratio, and the second oxide layer left below the first mask is a dual-gate spacer oxide layer, so that the loss of the thickness of the first oxide layer during etching can be reduced, and the reliability is improved.
Preferably, the internal structure of the planar VDMOS device is already arranged inside the epitaxial layer.
Preferably, the internal structure comprises an IGBT device structure and an SJMOS device structure.
Preferably, the method further comprises the step of arranging an internal structure of the planar VDMOS device in the epitaxial layer.
Preferably, after the double gate structure is formed, the method further includes:
and implanting and forming a body region on the surface of the epitaxial layer.
The invention also provides a manufacturing method of the planar VDMOS device double-gate structure, which comprises the following steps:
forming a third oxidation layer on the surface of the epitaxial layer of the planar VDMOS device;
a second mask is arranged above the third oxide layer, and the arrangement position of the second mask is matched with the position of the double grid;
etching the third oxide layer, wherein the third oxide layer left under the second mask is a double-gate interval oxide layer, and a fourth oxide layer is left on the surface of the epitaxial layer;
removing the second mask;
depositing polysilicon over the fourth oxide layer and the dual-gate spacer oxide layer;
and etching back the polysilicon to expose the surface of the dual-gate interval oxide layer, and reserving polysilicon side walls on two sides of the dual-gate interval oxide layer, wherein the polysilicon side walls are of a dual-gate structure of the planar VDMOS device.
Preferably, the thickness of the third oxide layer is 5000-10000A, and the thickness of the fourth oxide layer is 800-1200A.
Preferably, the third oxide layer is etched by adopting a wet etching mode with a high selectivity ratio, the third oxide layer left below the second mask is a dual-gate interval oxide layer, and a fourth oxide layer is left on the surface of the epitaxial layer, so that the thickness of the fourth oxide layer can be ensured, and the reliability is improved.
Compared with the prior art, the invention has the following beneficial effects:
(1) according to the invention, the double-gate interval oxide layer is formed firstly, and the double-gate structure is formed on two sides of the double-gate interval oxide layer by combining with the etching of the polycrystalline silicon, so that the forming method is ingenious, the process steps are simple, and the cost is saved.
(2) The double-grid spacing oxide layer fills the spacing region between the double grids before the double-grid structure is formed, so that the position of the double-grid structure can be accurately controlled, the self-alignment of P body region injection molding can be realized, the extra mask process step or the extra process step of filling the spacing region between the double-grid structure is saved, and the cost is saved.
Drawings
Fig. 1 is a schematic structural diagram of an SJMOS device according to a first embodiment of the present invention;
FIG. 2 is a flow chart illustrating a method for fabricating a dual gate structure according to a first embodiment of the present invention;
fig. 3A to 3F are schematic structural diagrams illustrating a method for fabricating a dual gate structure according to a first embodiment of the invention;
FIG. 4 is a flow chart illustrating a method for fabricating a dual gate structure according to a second embodiment of the present invention;
fig. 5A to 5F are schematic structural views illustrating a method for fabricating a dual gate structure according to a second embodiment of the invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
First embodiment
In this embodiment, an SJMOS device is taken as an example, and a device structure of the SJMOS device has already been formed in an N-type epitaxial layer of the SJMOS device, as shown in fig. 1, the SJMOS device structure includes an N-type substrate 1 and a plurality of layers of P pillars 3 sequentially formed on an N-type epitaxial layer 2, and the SJMOS device structure and the forming process thereof are common technical means of those skilled in the art and are not described herein again. Those skilled in the art will appreciate that other device structures for the SJMOS device are also within the scope of the present invention, such as a Pillar pilar structure.
The method for manufacturing the dual-gate structure of the SJMOS device in this embodiment, as shown in fig. 2, includes the following steps:
s1) as shown in fig. 3A, an ONO structure of the first oxide layer 4, the nitride layer 5, and the second oxide layer 6 is formed on the surface of the epitaxial layer 2 of the SJMOS device. Preferably, the thickness of the first oxide layer 4 is 800-1200A, the thickness of the nitride layer 5 is 200-500A, and the thickness of the second oxide layer 6 is 5000-10000A.
S2) as shown in fig. 3B, a first mask 7 is disposed over the second oxide layer 6, the position of the first mask 7 being matched with the positions of the double gates 8, that is, the position of the first mask 7 is the position of the gap between the double gates 8.
S3) as shown in fig. 3C, the second oxide layer 6 and the nitride layer 5 are etched by wet etching with high selectivity, the second oxide layer 6 left under the first mask 7 is the dual-gate spacer oxide layer 9, and at the same time, the first oxide layer 4 remains over the epitaxial layer 2 as the gate oxide layer of the SJMOS device.
S4) removing the first mask 7.
S5) as shown in fig. 3D, polysilicon 10 is deposited over the second oxide layer 6 and the double gate spacer oxide layer 9, the polysilicon 10 covering the entire surface of the SJMOS device, including the second oxide layer 6. Here, preferably, the polysilicon 10 is deposited by isotropic CVD, and the polysilicon 10 will necessarily form the topography shown in fig. 3D under the influence of the structure of the second oxide layer 6 and the dual gate spacer oxide layer 9.
S6), as shown in fig. 3E, the polysilicon 10 is etched back to expose the surface of the dual-gate spacer oxide layer 9, i.e. the polysilicon 10 on the surface of the dual-gate spacer oxide layer 9 is completely etched, and polysilicon sidewalls are left on both sides of the dual-gate spacer oxide layer 9, and the polysilicon sidewalls are the dual-gate 8 of the dual-gate structure of the planar VDMOS device. It can be understood by those skilled in the art that when the polysilicon 10 on the surface of the dual gate spacer oxide layer 9 is completely etched during the etch-back process, the polysilicon 10 on the surface of the first oxide layer 4 can be completely etched, and only polysilicon sidewalls are left on two sides of the dual gate spacer oxide layer 9.
S7) as shown in fig. 3F, then the body region 11 is implanted and formed on the surface of the epitaxial layer 2, and the steps of setting other SJMOS device structures are performed.
In the embodiment, the double-gate interval oxide layer 9 is formed firstly, and the double-gate structure is formed on two sides of the double-gate interval oxide layer 9 by combining with the etching of the polysilicon 10, so that the forming method is ingenious, the process steps are simple, and the cost is saved.
The dual-gate spacer oxide layer 9 of the embodiment fills the spacer region between the dual gates 8 before the dual-gate structure is formed, so that on one hand, the position of the dual-gate structure can be accurately controlled, on the other hand, self-alignment of injection molding of the body region 11 can be realized, additional mask process steps or additional process steps for filling the spacer region between the dual-gate structures are saved, and the cost is saved.
Second embodiment
The present embodiment differs from the first embodiment in that: the present embodiment is an example of an IGBT device, and before forming the double-gate structure of the IGBT device of the present embodiment, the device structure of the IGBT device is not formed in the epitaxial layer 2 of the IGBT device.
The method for manufacturing the double-gate structure of the IGBT device according to this embodiment, as shown in fig. 4, includes the following steps:
s10), as shown in fig. 5A, the third oxide layer 12 is formed on the surface of the epitaxial layer 2 of the IGBT device. Wherein, the thickness of the third oxide layer 12 is 5000-.
S20) as shown in fig. 5B, a second mask 13 is disposed over the third oxide layer 12, the position of the second mask 13 being matched with the position of the double gate 8.
S30) as shown in fig. 5C, etching the third oxide layer 12 by wet etching with high selectivity, wherein the third oxide layer 12 left under the second mask 13 is the dual-gate spacer oxide layer 9, and a fourth oxide layer 14 is left on the surface of the epitaxial layer 2 to serve as a gate oxide layer of the IGBT device, and preferably, the thickness of the fourth oxide layer is 800-.
S40) removing the second mask 13.
S50) as shown in fig. 5D, polysilicon 10 is deposited over the fourth oxide layer 14 and the double gate spacer oxide layer 9, the polysilicon 10 covering the entire surface of the IGBT device. Here, preferably, the polysilicon 10 is deposited by isotropic CVD, and under the influence of the structure of the fourth oxide layer 14 and the dual gate spacer oxide layer 9, the polysilicon 10 will necessarily form the profile shown in fig. 5D.
S60), as shown in fig. 5E, the polysilicon 10 is etched back, so that the surface of the dual-gate spacer oxide layer 9 is exposed, that is, the polysilicon 10 on the surface of the dual-gate spacer oxide layer 9 is completely etched, and polysilicon sidewalls are left on both sides of the dual-gate spacer oxide layer 9, where the polysilicon sidewalls are the dual-gate structure of the planar VDMOS device. It can be understood by those skilled in the art that when the polysilicon 10 on the surface of the dual gate spacer oxide layer 9 is completely etched during the etch-back process, the polysilicon 10 on the surface of the fourth oxide layer can also be completely etched, and only polysilicon sidewalls are left on two sides of the dual gate spacer oxide layer 9.
S70) as shown in fig. 5F, then, a body region 11 is implanted and formed on the surface of the epitaxial layer, and the setting steps of other IGBT device structures are performed.
Those skilled in the art will understand that the embodiments of the present invention are not limited to the planar VDMOS device as the SJMOS device and the IGBT device, and other planar VDMOS devices suitable for the dual-gate structure are within the scope of the present invention.
It will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential attributes thereof. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.
Furthermore, it should be understood that although the present description refers to embodiments, not every embodiment may contain only a single embodiment, and such description is for clarity only, and those skilled in the art should integrate the description, and the embodiments may be combined as appropriate to form other embodiments understood by those skilled in the art.
Claims (10)
1. A manufacturing method of a planar VDMOS device double-gate structure is characterized by comprising the following steps:
forming an ONO structure of a first oxide layer, a nitride layer and a second oxide layer on the surface of an epitaxial layer of the planar VDMOS device;
arranging a first mask above the second oxide layer, wherein the arrangement position of the first mask is matched with the position of the double grid;
etching the second oxide layer and the nitride layer, wherein the second oxide layer left under the first mask is a double-gate interval oxide layer;
removing the first mask;
depositing polysilicon over the second oxide layer and the dual-gate spacer oxide layer;
and etching back the polysilicon to expose the surface of the dual-gate interval oxide layer, and reserving polysilicon side walls on two sides of the dual-gate interval oxide layer, wherein the polysilicon side walls are of a dual-gate structure of the planar VDMOS device.
2. The method as claimed in claim 1, wherein the thickness of the first oxide layer is 800-1200A, the thickness of the nitride layer is 200-500A, and the thickness of the second oxide layer is 5000-10000A.
3. The method of claim 1, wherein the second oxide layer and the nitride layer are etched by wet etching with high selectivity, and the second oxide layer left under the first mask is a dual gate spacer oxide layer.
4. A manufacturing method of a planar VDMOS device double-gate structure is characterized by comprising the following steps:
forming a third oxidation layer on the surface of the epitaxial layer of the planar VDMOS device;
a second mask is arranged above the third oxide layer, and the arrangement position of the second mask is matched with the position of the double grid;
etching the third oxide layer, wherein the third oxide layer left under the second mask is a double-gate interval oxide layer, and a fourth oxide layer is left on the surface of the epitaxial layer;
removing the second mask;
depositing polysilicon over the fourth oxide layer and the dual-gate spacer oxide layer;
and etching back the polysilicon to expose the surface of the dual-gate interval oxide layer, and reserving polysilicon side walls on two sides of the dual-gate interval oxide layer, wherein the polysilicon side walls are of a dual-gate structure of the planar VDMOS device.
5. The method as claimed in claim 3, wherein the thickness of the third oxide layer is 5000-10000A, and the thickness of the fourth oxide layer is 800-1200A.
6. The method according to claim 3, wherein the third oxide layer is etched by wet etching with high selectivity, the third oxide layer left under the second mask is a dual-gate spacer oxide layer, and a fourth oxide layer is left on the surface of the epitaxial layer.
7. A method for manufacturing a planar VDMOS device according to claim 1 or 3, wherein the internal structure of the planar VDMOS device has been arranged inside the epitaxial layer.
8. The method of manufacturing of claim 7, wherein the internal structure comprises an IGBT device structure, an SJMOS device structure.
9. The method of manufacturing according to claim 1 or 3, further comprising providing an internal structure of a planar VDMOS device inside the epitaxial layer.
10. The method of manufacturing according to claim 1 or 3, further comprising, after forming the double gate structure:
and implanting and forming a body region on the surface of the epitaxial layer.
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|---|---|---|---|---|
| US20020140042A1 (en) * | 2001-03-28 | 2002-10-03 | International Rectifier Corporation | Ultra low QGD power MOSFET |
| JP2007142102A (en) * | 2005-11-17 | 2007-06-07 | Sanyo Electric Co Ltd | Semiconductor device, and method for manufacturing same |
| US20070278571A1 (en) * | 2006-05-31 | 2007-12-06 | Alpha & Omega Semiconductor, Ltd | Planar split-gate high-performance MOSFET structure and manufacturing method |
| CN102569385A (en) * | 2010-12-17 | 2012-07-11 | 上海华虹Nec电子有限公司 | VDMOS (vertical double-diffused metal oxide semiconductor) structure provided with shielding grid and preparation method thereof |
| CN104025299A (en) * | 2011-12-14 | 2014-09-03 | 密克罗奇普技术公司 | Self-aligned gate structure for field effect transistor |
| US20150200290A1 (en) * | 2014-01-16 | 2015-07-16 | Mau Lam Lai | Planar mosfets and methods of fabrication, charge retention |
| CN105140273A (en) * | 2015-08-10 | 2015-12-09 | 深圳深爱半导体股份有限公司 | Gate structure of semiconductor device and fabrication method of gate structure |
-
2022
- 2022-01-17 CN CN202210051895.6A patent/CN114373676A/en active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020140042A1 (en) * | 2001-03-28 | 2002-10-03 | International Rectifier Corporation | Ultra low QGD power MOSFET |
| JP2007142102A (en) * | 2005-11-17 | 2007-06-07 | Sanyo Electric Co Ltd | Semiconductor device, and method for manufacturing same |
| US20070278571A1 (en) * | 2006-05-31 | 2007-12-06 | Alpha & Omega Semiconductor, Ltd | Planar split-gate high-performance MOSFET structure and manufacturing method |
| CN102569385A (en) * | 2010-12-17 | 2012-07-11 | 上海华虹Nec电子有限公司 | VDMOS (vertical double-diffused metal oxide semiconductor) structure provided with shielding grid and preparation method thereof |
| CN104025299A (en) * | 2011-12-14 | 2014-09-03 | 密克罗奇普技术公司 | Self-aligned gate structure for field effect transistor |
| US20150200290A1 (en) * | 2014-01-16 | 2015-07-16 | Mau Lam Lai | Planar mosfets and methods of fabrication, charge retention |
| CN105140273A (en) * | 2015-08-10 | 2015-12-09 | 深圳深爱半导体股份有限公司 | Gate structure of semiconductor device and fabrication method of gate structure |
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