CN114354665A

CN114354665A - Stripping method for failure chip

Info

Publication number: CN114354665A
Application number: CN202210274980.9A
Authority: CN
Inventors: 俞佩佩; 王丽雅; 胡明辉
Original assignee: Jingxincheng Beijing Technology Co Ltd; Nexchip Semiconductor Corp
Current assignee: Jingxincheng Beijing Technology Co Ltd; Nexchip Semiconductor Corp
Priority date: 2022-03-21
Filing date: 2022-03-21
Publication date: 2022-04-15
Anticipated expiration: 2042-03-21
Also published as: CN114354665B

Abstract

The invention discloses a stripping method of a failed chip, which at least comprises the following steps: acquiring a failure chip to be analyzed, and confirming a target area of the failure chip; preprocessing a failure chip to expose metal wiring of a target area; removing the metal wiring, and cleaning the failed chip; grinding the medium layer of the target area to obtain a stripping sample; wherein the step of removing the metal wiring comprises: sticking a mucous membrane on the metal wiring; and removing the adhesive film after the adhesive film is adhered to the metal wiring so as to remove the metal wiring. The invention provides a layer stripping method for a failed chip, which can improve the uniformity of physical layer stripping of the chip.

Description

Stripping method for failure chip

Technical Field

The invention belongs to the field of semiconductor chip inspection, and particularly relates to a layer stripping method for a failed chip.

Background

When the chip test is abnormal, the chip with the abnormal test needs to be subjected to corresponding failure analysis. For failure analysis of a chip, the chip needs to be stripped layer by layer from top to bottom through physical stripping to find out the problem. At present, in the stripping process, the problem of failure analysis of a chip sample is easy to occur, and the risk of damaging the chip sample also exists.

Disclosure of Invention

The invention aims to provide a layer stripping method for a failed chip, which can improve the uniformity of the physical layer stripping of the chip, so as to improve the accuracy of failure analysis of a chip sample and protect the chip sample from being damaged.

In order to solve the technical problems, the invention is realized by the following technical scheme:

the invention provides a stripping method of a failed chip, which at least comprises the following steps:

obtaining a failure chip to be analyzed, and confirming a target area of the failure chip;

preprocessing the failure chip to expose the metal wiring of the target area;

removing the metal wiring, and cleaning the failure chip; and

grinding the medium layer of the target area to obtain a stripping sample;

wherein the step of removing the metal wiring comprises:

sticking a mucous membrane on the metal wiring; and

and after the mucous membrane is adhered to the metal wiring, removing the mucous membrane so as to remove the metal wiring.

In an embodiment of the present invention, the process of preprocessing the failed chip includes: and soaking the failed chip in an acid solution, taking out the failed chip, cleaning and carrying out ultrasonic oscillation.

In an embodiment of the present invention, the process of preprocessing the failed chip further includes: and grinding the failed chip to expose the metal wiring of the target area.

In an embodiment of the invention, when the failed chip is ground, the center of gravity of grinding is located in the target area.

In an embodiment of the invention, after the failed chip is preprocessed, the exposed area of the metal wiring is greater than or equal to 1/8 of the original area of the metal wiring, and the exposed area of the metal wiring is less than or equal to 1/6 of the original area of the metal wiring.

In an embodiment of the invention, the width of the mucous membrane is 1.3-1.5 times of the width of the metal wiring, and the distance between the side edge of the mucous membrane and the side edge of the metal wiring is 1/8-1/5 of the width of the metal wiring.

In an embodiment of the present invention, after the mucosa is torn off, when the remaining area of the metal wiring is smaller than 1/12 of the original area of the metal wiring, the dielectric layer of the target region is ground.

In an embodiment of the present invention, after tearing off the adhesive film, when the remaining area of the metal wiring is greater than or equal to 1/12 of the original area of the metal wiring, the step of removing the metal wiring is repeated.

In one embodiment of the present invention, after the failed chip is pretreated and before the metal wiring is removed, the failed chip is treated with an acid solution.

As described above, the method for peeling the failed chip provided by the invention can peel the whole chip sample, not only has high peeling observation efficiency, but also can improve the uniformity of grinding peeling, improve the observation definition of the sample under a scanning electron microscope, is beneficial to improving the accuracy of chip failure analysis, and ensures that the device layer is not damaged in the chip peeling process.

Of course, it is not necessary for any product in which the invention is practiced to achieve all of the above-described advantages at the same time.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without creative efforts.

Fig. 1 is a flowchart of a chip delamination method according to the present invention.

Fig. 2 is a schematic structural diagram of a sample.

Fig. 3 is a schematic structural diagram of the target region.

FIG. 4 is a schematic diagram of a sample polishing top dielectric layer.

Fig. 5 is a sectional view of a metal wiring.

Fig. 6 is a schematic view of the surface structure of the target area after step S1.

Fig. 7 is a schematic view of the surface structure of the target region after step S1.

Fig. 8 is a schematic view of the surface structure of the target region after step S1.

Fig. 9 is a flowchart of step S2.

Fig. 10 is a schematic diagram of the grinding operation of the sample.

Fig. 11 is a schematic view of the target area surface after step S3.

Fig. 12 is a schematic view of the adhesive structure of the mucous membrane in step S4.

Fig. 13 is a schematic view of the surface structure of the target region after the metal wiring is peeled off by the mucous membrane in step S4.

Fig. 14 is a schematic view of the surface structure of the target region after the metal wiring is peeled off by the mucous membrane in step S4.

Fig. 15 is a schematic structural view of a dielectric layer and a lower metal wiring.

Fig. 16 is a schematic view of the adhesion distribution of the mucosa on the first region wiring and the second region wiring.

Fig. 17 is a view showing the adhesion of the adhesive film to the metal wiring under a scanning electron microscope.

FIG. 18 is a graph showing the results of polishing without being treated by the method described in this example.

FIG. 19 is a view showing the result of removing a metal wiring by the method of the present invention.

FIG. 20 is a graph showing the results of removing the second barrier layer by the method of the present invention.

Description of reference numerals: the method comprises the following steps of 1 sample, 2 target areas, 3 grinding pads, 4 liquid supply devices, 5 grinding liquids, 10 substrates, 20 device layers, 30 dielectric layers, 40 metal wiring lines, 401 first area wiring lines, 402 second area wiring lines, 50 first barrier layers, 501 second barrier layers and 60 mucous membranes.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

The failure analysis of the chip has important significance on the production and the use of the product, the failure of the chip can occur at each stage of the life cycle of the product, and the failure analysis relates to each link of the research and development design, incoming material inspection, processing and assembly, test screening, client use and the like of the product. By analyzing samples of process defective products, early failure, test failure, pilot test failure and field failure, a failure mode is confirmed, failure mechanisms are analyzed, failure reasons are determined, preventive measures are finally given, and the occurrence of failure is reduced or avoided. Therefore, the chip failure has strong practical significance in the aspects of improving the product quality, developing and improving the technology, repairing the product, arbitrating failure accidents and the like.

In various embodiments, methods of failure analysis of a chip may include visual analysis under optical microscopy, ultrasonic scanning microscopy of internal material conditions, X-ray detection of package defects, scanning electron microscopy of micro-zone analysis, micro-optic microscopy of leakage current paths, and the like. The chip is stripped to remove the passivation layer inside the chip and expose the lower metal layer of the failed chip, or the metal layer is removed to continue observing the lower structure, so that the problems of the failed chip device can be found intuitively and quickly, and the microscope observation is facilitated.

Referring to fig. 1 and 2, the invention discloses a method for peeling a failed chip, which includes steps S1 to S5.

S1, sample 1 to be analyzed is taken, and target region 2 in sample 1 is confirmed.

S2, sample 1 is pretreated to expose metal wiring 40 of target area 2.

S3, treat sample 1 with an acid solution.

S4, sticking the adhesive film on the metal wiring 40, and removing the adhesive film to remove the metal wiring 40.

And S5, washing off residual mucous of mucous membrane, and grinding the medium layer 30 of the target area 2 to obtain a delaminating sample.

Referring to fig. 2 and 3, in one embodiment of the present invention, in step S1, the sample 1 to be analyzed is, for example, a dead chip after removing the package. The chip comprises a substrate 10, a device layer 20 arranged on the substrate 10 and a dielectric layer 30 arranged on the device layer 20, wherein a metal wiring 40 is arranged in the dielectric layer 30, a plurality of semiconductor devices are arranged in the device layer 20, and the semiconductor devices are electrically connected through the metal wiring layer 40 to form an integrated device. Both sides of the metal wiring 40 are provided with the first barrier layer 50 and the second barrier layer 501. The first barrier layer 50 covers the metal wire 40, and the metal wire 40 covers the second barrier layer 501. The sectional length of the first barrier layer 50, the sectional length of the metal wiring 40, and the sectional length of the second barrier layer 501 are equal to each other. Such as a source, a drain, a gate, etc. disposed in an active region of the substrate 10.

Referring to fig. 1 and 2, in an embodiment of the present invention, in sample 1, the material of the dielectric layer 30 is a dielectric, such as silicon dioxide. The material of the metal wiring 40 may be copper or aluminum. The device layer 20 includes, for example, the semiconductor devices and shallow trench isolation structures and the like provided between the semiconductor devices. The metal wiring 40 in the dielectric layer 30 may be structured with regularly dense wirings such as the first region wiring 401. The metal wiring 40 in the dielectric layer 30 may also be configured as a relatively scattered wiring, such as the second region wiring 402. When the sample 1 is ground, the grinding rate of the dielectric layer 30 is higher than that of the metal wiring 40, so in the invention, after the metal wiring 40 is processed separately, the dielectric layer 30 is ground, so that the dielectric layer 30 and the metal wiring 40 are uniformly ground, the damage to a grid electrode and the like in the device layer 20 in the grinding process is avoided, and the structure of each layer can be clearly seen in the failure analysis of the sample 1.

Referring to fig. 2-4, in one embodiment of the present invention, a plurality of metal wires 40 are disposed in the dielectric layer 30, and the plurality of metal wires 40 are removed step by a reverse process of the chip process. That is, in the present invention, the multi-layered metal wiring 40 in the dielectric layer 30 is removed layer by layer. In this embodiment, the metal wiring 40 in the dielectric layer 30, for example, in the nth layer, may include only the first region wiring 401 without the second region wiring 402. In other embodiments, the metal wiring 40 in the dielectric layer 30, for example, the nth layer, may also include only the second region wiring 402 without the first region wiring 401. In other embodiments, the metal wiring 40, for example, of the nth layer in the dielectric layer 30 includes a first region wiring 401 and a second region wiring 402.

Referring to fig. 2-5, in an embodiment of the present invention, during the process of removing the metal wiring 40 of the nth layer, for example, the position of the target region 2 is first confirmed under an Optical Microscope (OM) so as to focus the polishing center on the target region 2 in the subsequent polishing process. In step S1, the dielectric layer 30 covering the n-th layer of metal wiring 40 is first ground, and the delaminated sample 1 is placed under a scanning electron microscope to be observed, and the thickness H of the dielectric layer 30 above the metal wiring 40 is measured, as shown in fig. 5. When the thickness H of the dielectric layer 30 remaining over the metal wiring 40 is equal to or less than, for example, 50 angstroms, step S2 is performed. If the thickness H of the dielectric layer remaining over the metal wire 40 is greater than, for example, 50 angstroms, the dielectric layer 30 in the target region 2 is continuously polished until the thickness H of the dielectric layer remaining over the metal wire 40 is less than or equal to 50 angstroms under the observation of an optical microscope, and then step S2 is performed.

Referring to FIGS. 6-8, in one embodiment of the present invention, in step S1, when H is less than or equal to 50 angstroms, the first barrier layer 50 covered by the dielectric layer 30 is exposed. Since the first barrier layer 50 and the second barrier layer 501 are used to help fix the position of the metal wire 40 in the dielectric layer 30, the metal wire 40 is prevented from migrating in the dielectric layer 30. Therefore, the dielectric layer 30 and the first barrier layer 50 have different polishing ratios, and when the dielectric layer 30 and the first barrier layer 50 are directly polished, a pattern structure as shown in fig. 6 may occur. At this time, pits appear near the center of gravity of the polishing, and the center of gravity of the polishing diffuses outward, so that the surfaces of the first barrier layer 50 and the dielectric layer 30 are no longer flush, and the dielectric layer 30 is polished more. In the case of such grinding unevenness, there is a difference in height between the dielectric layer 30 and the first barrier layer 50, and the metal wiring 40. Due to the different polishing ratios of the dielectric layer 30 and the first barrier layer 50, the metal wiring 40 may be exposed, as shown in fig. 8. The metal wiring 40 may also be under the coverage of the first barrier layer 50, as shown in fig. 6. The metal wiring 40 may also be completely exposed as shown in fig. 7. The material of the first barrier layer 50 and the second barrier layer 501 is, for example, thin film titanium nitride. At this time, the color of the first barrier layer 50 is clearly seen through observation by an optical microscope, whereas the color of the metal wiring 40 is hardly clearly seen.

Referring to fig. 6-10, in an embodiment of the present invention, step S2 includes:

and S21, placing the sample 1 in an acid solution for soaking, taking out the sample 1 and ultrasonically oscillating the sample 1.

S22, sample 1 was observed under an optical microscope.

S23, in sample 1, it was observed whether or not the metal wiring in target region 2 was exposed. When the metal wiring of the target area 2 is exposed, step S3 is performed. When the metal wiring of the target area 2 is not exposed, step S24 is performed.

S24, sample 1 was polished so that the metal wiring of target region 2 was exposed.

Referring to fig. 6-10, in one embodiment of the present invention, sample 1 is pretreated after the dielectric layer 30 on the metal wiring 40 is completely removed. For example, the sample 1 may be placed in an acid solution, soaked for 4-6 min, and then the sample 1 is taken out and cleaned, and the sample 1 is ultrasonically vibrated for 45-75 s. Specifically, the sample 1 may be soaked in a dilute hydrochloric acid solution for, for example, 5min, and then the sample 1 may be removed and washed, followed by ultrasonic oscillation for, for example, 1 min. The pretreatment of sample 1 was completed. The treated sample 1 was then observed under an optical microscope to confirm whether or not the metal wiring 40 was exposed. If the metal wiring 40 is exposed, step S3 is executed. If the metal wiring 40 is not exposed, step S24 is executed. Since the first barrier layer 50 is insoluble in acid, if the metal wiring 40 is already exposed on the surface of the sample 1 after the polishing in step S1, the acid solution can corrode the metal wiring 40 by passing through the exposed portion of the metal wiring 40. The first barrier layer 50 loses the adhesion of the metal wiring 40, and is carried away by the acid solution and the cleaning water, so that the exposed metal wiring 40 can be observed under an optical microscope. If the metal wire 40 is not exposed on the surface of the sample 1 after the step S1, the metal wire 40 is not exposed under an optical microscope after the pretreatment because the acid solution does not react with the dielectric layer 30 and the first barrier layer 50, and thus the step S24 is performed.

Referring to fig. 6-10, in one embodiment of the present invention, in step S24, the sample 1 is placed on the polishing pad 3, and the target area 2 is in contact with the polishing pad 3. A polishing liquid 5 is applied to the polishing pad 3 by a liquid supply means 4, and is pressed against the sample 1 with, for example, a finger. The sample 1 is subjected to a pressing force F, wherein the point of action of the pressing force F is located on the surface of the sample 1 and directly above the target area 2. The rotation of the polishing pad 3 and the pressing of the sample 1 rub the surface of the sample 1, so that the first barrier layer 50 or the remaining dielectric layer 30 covered on the metal wiring 40 is polished and removed, and the polishing time is controlled to be, for example, 10 to 20 seconds. The ground sample 1 was again pretreated with an acid solution, and the steps S21 to S23 were repeated until the metal wiring 40 was exposed under observation with an optical microscope. Therefore, the thickness of the dielectric layer on the metal wiring 40 is controlled to be, for example, 50 angstroms or less by the S1 grinding, so that the metal wiring 40 is rapidly exposed on the basis of controlling the height difference between the dielectric layer 30 and the metal wiring 40, and the number of acid solution treatments is reduced. In other embodiments of the present invention, after step S24 is completed, the polished sample 1 may be directly placed under an optical microscope to observe whether the metal wires 40 are exposed, so as to reduce the number of acid solution treatments and avoid damage to the sample 1 caused by an excessively long acid solution treatment time. In the polishing process of step S24, the exposed area of the metal line 40 is controlled to be equal to or larger than 1/8, for example, of the original area of the metal line 40, and equal to or smaller than 1/6, for example, of the original area of the metal line 40. When the exposed area of the metal wire 40 is greater than or equal to 1/8, for example, the original area of the metal wire 40, step S3 is performed to facilitate the subsequent detachment of the metal wire 40. The exposed area of the metal wiring 40 is controlled to be less than or equal to 1/6, for example, of the original area of the metal wiring 40 to ensure that the difference in height between the metal wiring 40 and the dielectric layer 30 is not further enlarged by the polishing.

Referring to fig. 6-10, in one embodiment of the present invention, when the metal wire 40 is copper, if the metal wire 40 is exposed, the metal wire 40 is reacted with the acid solution, and neither the first barrier layer 50 nor the dielectric layer 30 is reacted with the acid. Therefore, after the first barrier layer 50 is removed, a purple-red metal can be clearly seen under an optical microscope. In other embodiments, when the metal wire 40 is aluminum, the metal wire 40 can be seen through an optical microscope as a silver white metal if it is exposed. In the case where the metal line 40 is not exposed, when the first barrier layer 50 is made of titanium nitride, it is observed under an optical microscope that, for example, a light blue shade is observed at the position of the metal line 40 in the target region. When the metal wiring 40 is removed, the exposed second barrier layer 501 can be observed under an optical microscope, and the second barrier layer 501 appears light blue under the optical microscope.

Referring to fig. 2 and 11, in an embodiment of the present invention, in step S3, after step S2, the first barrier layer 50 is removed and the metal wire 40 is exposed, and the sample 1 is again subjected to the acid solution treatment. The specific process of step S3 is to place the sample 1 in an acid solution, soak for 1-5 min, take out the sample 1, wash it, and shake it for 45-75S in an ultrasonic environment. The acid solution treatment process for the sample 1 is repeated, for example, 2 to 3 times. By step S3, sample 1 in which the metal wiring 40 was completely exposed was obtained. The etching of the metal wire 40 by the acid solution treatment of step S3 helps to remove the remaining first barrier layer 50 and further reduces the height difference between the metal wire 40 and the dielectric layer 30. In step S3, the acid solution treatment process of the sample 1 may specifically be that the sample 1 is placed in dilute hydrochloric acid, soaked for example for 1min, and then the sample 1 is taken out and cleaned, and then shielded for example for 1min in an ultrasonic environment. This process is repeated, for example, 2 times. The thinned metal wiring 40 is obtained, and the thickness of the thinned metal wiring 40 is less than, for example, 100 angstroms.

Referring to fig. 2, 11-14, in an embodiment of the present invention, in step S4, the sample 1 is placed on a sample stage of an optical microscope, and the adhesive film 60 is attached to the metal wire 40 by the optical microscope. Wherein, the adhesive film 60 covers the metal wiring 40, and the width of the adhesive film 60 is larger than the width of the metal wiring 40. After the adhesive film 60 is attached, the adhesive film 60 is scraped from one side to the other side of the adhesive film 60 by a scraper to remove excess air bubbles, so that the adhesive film 60 is tightly attached to the metal wiring 40. After the mucous membrane 60 is adhered to the metal wiring 40, the mucous membrane 60 is kept still for 2-3 min for example, and is quickly torn off. Since the metal wiring 40 is thinned and has a loose structure after the processing of step S3, the remaining metal wiring 40 can be quickly torn off through the adhesive film 60. After tearing off the mucous membrane 60, the sample 1 was placed under an optical microscope to see whether the metal wiring 40 was completely removed. If it is completely removed or the remaining area of the metal wire 40 is smaller than the original area of the metal wire 40, e.g., 1/12, step S5 is performed. If there are remaining metal lines 40, step S4 may be performed again until the metal lines 40 are completely removed or the remaining area of the metal lines 40 is smaller than the original area of the metal lines 40, for example, 1/12. And when S4 is executed again, the attaching and detaching direction of the adhesive film 60 may be perpendicular to the previous attaching and detaching direction, so that the remaining metal wires 40 are detached.

Referring to fig. 13-15, in step S4, in the present embodiment, the adhesive film 60 may be an adhesive tool, such as an adhesive tape, and the adhesive tape may be single-sided and transparent, so as to confirm that the adhesive film 60 can better cover the metal wire 40 and facilitate the operation of tearing off the adhesive film 60. In other embodiments, the adhesive film 60 may be a curable adhesive material, such as an acrylic adhesive, the adhesive film 60 is applied to the metal wire 40, the adhesive film 60 is naturally cured or the adhesive film 60 is cured by ultraviolet light, for example, and then the adhesive film 60 is peeled off and the metal wire 40 is removed. The adhesive material of the adhesive film 60 may be transparent, and in other embodiments, multiple colors of adhesive material may be used to facilitate the differentiation and tearing off of the adhesive film 60, depending on the application. After the adhesive film 60 is used, a portion of the adhesive film 60 remains on the dielectric layer 30 and the remaining metal wires 40 of the target region 2. Therefore, in step S5, the surface of the sample 1 is washed with an organic solvent, such as acetone, to remove the residual adhesive remained on the mucous membrane 60. The remaining adhesive on the surface of sample 1 was washed away. And then, the second barrier layer 501 is removed by grinding, specifically, the sample 1 can be placed on the grinding pad 3, the target area 2 is in contact with the surface of the grinding pad 3, and then the grinding liquid 5 is dripped on the upper surface of the grinding pad 3 to press the upper side of the target area 2, so that the grinding center is concentrated on the upper side of the second barrier layer 501. And then, the second barrier layer 501 and the remaining part of the metal wiring 40 are removed by rotating the polishing pad 3 and pressing with fingers, and the dielectric layer 30 at the edge is polished as little as possible in the polishing process, so that the dielectric layer 30 is prevented from being further polished and the height difference is prevented from being enlarged. In this embodiment, after the metal wire 40 is torn off, when the dielectric layer 30 is higher than the second barrier layer 501, in step S5, the dielectric layer 30 is first ground until the edges of the dielectric layer 30 and the second barrier layer 501 are connected. The grinding center of gravity is placed on the second barrier layer 501, and the second barrier layer 501 is continuously ground until the second barrier layer 501 is completely removed, so that the delaminated sample is obtained. Specifically, when the sample 1 is observed under an optical microscope, the surface of the target region 2 is free from a black mask, i.e., the removal of the metal wiring 40 of, for example, the nth layer is completed. After the metal wiring 40 is removed, since the second barrier layer 501 is in the form of a film and is ground together with the dielectric layer 30, the grinding ratio is less different. Therefore, by adjusting the center of gravity of the finger pressure, it is possible to help reduce the height difference between the dielectric layer 30 and the second barrier layer 501 and reduce the polishing amount in the region other than the target region 2. After the second barrier layer 501 is removed, the dielectric layer 30 is ground, so that the dielectric layer 30 can be flattened quickly and simply.

Referring to fig. 1 to 15, in an embodiment of the present invention, through steps S1 to S5, in the process of peeling the metal wire 40, a height difference between the dielectric layer 30 and the metal wire 40 is adjusted in time, which is beneficial to local uniformity of peeling, and avoids device damage caused by over-polishing of the dielectric layer 30 when the metal wire 40 is peeled. When the last metal wiring 40 is stripped, the dielectric layer 30 is continuously polished after the second barrier layer 501 is removed in step S5, so that the dielectric layer 30 in the target region 2 can be easily controlled to be uniformly polished to the device layer 20. Specifically, the surface of the gate electrode can be used, which not only can clearly and effectively observe the device layer 20, but also can ensure that the device layer 20 is not damaged by stripping, for example, the gate electrode is damaged, and the accuracy of failure analysis of the sample 1 is affected. In the present embodiment, when the first metal wiring 40 is stripped, the target region 2 may be polished to the surface of the tsv, and then the steps S1 to S5 may be performed.

Referring to fig. 2 to 16, in an embodiment of the invention, when the metal wiring 40 of the nth layer includes the first area wiring 401, in step S4, the adhesive film 60 may be directly attached on the entire target area 2. The area of the mucous membrane 60 is larger than the area of the target area 2, and the distance from the side edge of the mucous membrane 60 to the edge of the target area 2 is, for example, 1/8-1/10 of the width of the target area 2. In other embodiments of the present invention, when the metal wiring 40 of the nth layer includes the second region wiring 402, in step S4, the adhesive film 60 is attached on each scattered metal wiring 40, and the width of the adhesive film 60 is greater than that of the metal wiring 40. Specifically, the width of the adhesive film 60 is 1.3 to 1.5 times of the width of the metal wiring 40, for example, and the distance between the side edge of the adhesive film 60 and the side edge of the metal wiring 40 is 1/8 to 1/5 of the width of the metal wiring 40, so that the adhesive film 60 can be coated on the metal wiring 60, and adjacent adhesive films 60 do not affect each other, and the adhesive film is particularly suitable for removing the first area wiring 40. In the masking process of step S5, the center of gravity is to be located in the target region 2 and away from other regions so as to protect the dielectric layer 30 and reduce the degree of grinding of the dielectric layer 30, thereby reducing the height difference between the dielectric layer 30 and the metal wire 40. In other embodiments of the present invention, when the metal wiring 40 of the nth layer includes the first region wiring 401 and the second region wiring 402. In step S5, the center of gravity is placed at the center of the target region 2 so that the first-region wiring 401 and the second-region wiring 402 can be simultaneously ground away.

Referring to fig. 2, 3 and 17, in an embodiment of the present invention, the first area wiring 401 may be a package area of the sample 1, and the second area wiring 402 may be an area outside the package area. The adhesive tape 60 is attached to, for example, the sealing region, as shown in fig. 17, so that the plurality of metal wires 40 in the same layer can be covered, and it is apparent that the adhesive tape 60 has excellent covering ability.

Referring to fig. 2, 18 and 19, fig. 18 is a Scanning Electron Microscope (SEM) observation diagram of a sample 1 directly stripped without using the stripping method of this embodiment to obtain a stripped sample. Fig. 19 is a scanning electron microscope observation image of the delaminated sample obtained in the delaminating operation method according to the present example. It is evident that in fig. 18, the gate structure of the device layer 20 is already visible outside the encapsulation area, in case the dielectric layer 30 has not been completely removed in the encapsulation area. And then polished down without adjusting the height difference, so that the device layer 20 is damaged if the metal wiring 40 in the packaging area is not removed. In addition, in the same layer of the sample 1, it can be obviously seen that the grinding of the medium layer 30 is not uniform, because the local grinding is not uniform, the whole structure of the sample 1 is not clear, and great difficulty is brought to failure analysis. In fig. 19, it can be seen that the metal wiring 40 has been removed in the package area, leaving the second barrier layer 501. In the packaging area, the metal wiring 40 is removed cleanly and uniformly, is consistent with the level outside the packaging area, and can be synchronously and uniformly ground to the device layer 20, so that the damage to the device layer 20 is avoided. Globally, the grinding of the dielectric layer 30 is uniform, the structure of each region of the sample 1 can be clearly observed under a scanning electron microscope, and chip failure analysis is facilitated. Therefore, in the sample 1 in this embodiment, the metal wiring 40 and the dielectric layer 30 can be quickly and uniformly removed, which is beneficial to improving the accuracy of failure analysis and improving the efficiency of chip delamination.

Referring to fig. 17-20, in the present embodiment, the sem has great advantages in observing various phenomena in the micron and submicron ranges, and can achieve better results when used for failure analysis of chips. By utilizing the scanning electron microscope and combining a good chip stripping effect, a good observation and analysis effect can be achieved on metallographic analysis. For example, analysis of basic microstructures such as cryptoneedle martensite, troostite and the like, which cannot be resolved by various optical microscopes, for example, analysis of fine structures of microstructures such as morphology of two phases of ferrite and cementite in upper bainite, morphology of elongated lath-like structures of lath-like martensite and the like, for example, various intermetallic compound phases, carbide phases, boride phases and nitrides and the like. The fracture can be analyzed and classified by using a scanning electron microscope, the fracture type is determined, the wear surface and wear products of a sample are analyzed by using the scanning electron microscope, the metal corrosion condition is analyzed by using the scanning electron microscope, and the like. The failure analysis which can be realized by the scanning electron microscope is established on the observation of the sample 1, so that in the embodiment, the sample 1 which is uniformly stripped in each area and has intact devices in each area can be obtained, high-quality observation conditions can be stably provided for the analysis and observation of the scanning electron microscope, and the accuracy of the chip failure analysis can be improved. Moreover, the device of sample 1 obtained by the present example was intact, and had a value of reuse after the cause of failure was identified.

Referring to fig. 2-4 and 20, fig. 20 is a scanning electron microscope observation view of sample 1 after removing the second barrier layer 501 in the encapsulation region after step S5 in this embodiment. As shown in fig. 20, it is apparent that the second barrier layer 501 is uniformly removed, and the dielectric layer 30 at the edge is polished less, so that the dielectric layer 30 is planarized by the subsequent polishing of the dielectric layer 30. Therefore, in the grinding process, by adjusting the grinding center of gravity to fall on the target region 2, which is the package region in this embodiment, the dielectric layer 30 at the edge can be effectively prevented from being thinned, and the height difference between the dielectric layer 30 and the metal wiring 40 is further reduced. In the delamination of the sample 1, the manual polishing is used as the polishing method, and the polishing center of gravity can be controlled more accurately and distributed in the target region 2.

Referring to fig. 1 to 20, the present invention provides a delamination method for a failed chip, which separates the metal wiring 40, the dielectric layer 30, the first barrier layer 50 and the second barrier layer 501. In the stripping process, the height difference of the grinding of the dielectric layer 30 and the metal wiring 40 can be controlled and reduced to ensure that the grinding uniformity between local areas is good and the height difference is small on the surface of the sample 1 in the target area 2. In particular, the extent of polishing in each region is the same when the layers are stripped to the device layer 20. Therefore, the method for stripping the failed chip provided by the invention can be used for stripping the whole chip sample 1, has high stripping observation efficiency, can improve the uniformity of grinding stripping, improves the observation definition of the sample 1 under a scanning electron microscope, is beneficial to improving the accuracy of chip failure analysis, and ensures that the device layer 20 is not damaged in the chip stripping process.

In the description of the present specification, reference to the description of the terms "present embodiment," "example," "specific example," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

The embodiments of the invention disclosed above are intended merely to aid in the explanation of the invention. The examples are not intended to be exhaustive or to limit the invention to the precise forms disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention. The invention is limited only by the claims and their full scope and equivalents.

Claims

1. A delamination method for a failed chip is characterized by at least comprising the following steps:

preprocessing the failure chip to expose the metal wiring of the target area;

removing the metal wiring, and cleaning the failure chip; and

grinding the medium layer of the target area to obtain a stripping sample;

wherein the step of removing the metal wiring comprises:

attaching a mucous membrane to the metal wiring; and

2. The method of claim 1, wherein the step of pre-treating the failed chip comprises: and soaking the failed chip in an acid solution, taking out the failed chip, cleaning and carrying out ultrasonic oscillation.

3. The method of claim 1, wherein the step of pre-treating the failed chip further comprises: and grinding the failed chip to expose the metal wiring of the target area.

4. A delamination method for a failed chip as recited in claim 3, wherein, when grinding said failed chip, a center of gravity of grinding is located in said target region.

5. The method of claim 1, wherein after the pre-treating of the failed chip, the exposed area of the metal wiring is greater than or equal to 1/8 of the original area of the metal wiring, and the exposed area of the metal wiring is less than or equal to 1/6 of the original area of the metal wiring.

6. The delaminating method of the failed chip as claimed in claim 1, wherein the width of the adhesive film is 1.3-1.5 times the width of the metal wire, and the distance between the side edge of the adhesive film and the side edge of the metal wire is 1/8-1/5 of the width of the metal wire.

7. The delamination method for a failed chip as defined in claim 1, wherein after removing said adhesive film, when the remaining area of said metal wire is smaller than 1/12 of the original area of said metal wire, said dielectric layer of said target area is ground.

8. The delamination method for a failed chip as defined in claim 1, wherein after removing said adhesive film, when the remaining area of said metal wire is greater than or equal to 1/12 of the original area of said metal wire, the step of removing said metal wire is repeated.

9. The method of claim 1, wherein the failed chip is treated with an acid solution after the failed chip is pretreated and before the metal wires are removed.

10. The method of claim 1, wherein the adhesive film is an adhesive tape.