CN114300011A - SRAM (static random Access memory) construction method, device, storage medium and intelligent equipment - Google Patents
SRAM (static random Access memory) construction method, device, storage medium and intelligent equipment Download PDFInfo
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- CN114300011A CN114300011A CN202111519774.1A CN202111519774A CN114300011A CN 114300011 A CN114300011 A CN 114300011A CN 202111519774 A CN202111519774 A CN 202111519774A CN 114300011 A CN114300011 A CN 114300011A
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- 230000003068 static effect Effects 0.000 title description 3
- 239000002184 metal Substances 0.000 claims abstract description 46
- 229910052751 metal Inorganic materials 0.000 claims abstract description 46
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 30
- 229920005591 polysilicon Polymers 0.000 claims abstract description 30
- 230000005540 biological transmission Effects 0.000 claims abstract description 26
- 238000000034 method Methods 0.000 claims abstract description 12
- 101100310593 Candida albicans (strain SC5314 / ATCC MYA-2876) SOD4 gene Proteins 0.000 claims description 22
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- 101100190148 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) PGA2 gene Proteins 0.000 claims description 22
- MYHXHCUNDDAEOZ-FOSBLDSVSA-N prostaglandin A2 Chemical compound CCCCC[C@H](O)\C=C\[C@H]1C=CC(=O)[C@@H]1C\C=C/CCCC(O)=O MYHXHCUNDDAEOZ-FOSBLDSVSA-N 0.000 claims description 22
- 229910052755 nonmetal Inorganic materials 0.000 claims description 21
- 239000004065 semiconductor Substances 0.000 claims description 21
- 239000000463 material Substances 0.000 claims description 13
- YBHMPNRDOVPQIN-UHFFFAOYSA-N (13E,15S)-15-Hydroxy-9-oxo-8(12),13-prostadienoic acid Natural products CCCCCC(O)C=CC1=C(CCCCCCC(O)=O)C(=O)CC1 YBHMPNRDOVPQIN-UHFFFAOYSA-N 0.000 claims description 11
- YBHMPNRDOVPQIN-VSOYFRJCSA-N prostaglandin B1 Chemical compound CCCCC[C@H](O)\C=C\C1=C(CCCCCCC(O)=O)C(=O)CC1 YBHMPNRDOVPQIN-VSOYFRJCSA-N 0.000 claims description 11
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- PRFXRIUZNKLRHM-UHFFFAOYSA-N l-prostaglandin B2 Natural products CCCCCC(O)C=CC1=C(CC=CCCCC(O)=O)C(=O)CC1 PRFXRIUZNKLRHM-UHFFFAOYSA-N 0.000 claims description 10
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- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 6
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Abstract
The embodiment of the invention discloses an SRAM construction method, which comprises a transmission tube construction step, a resistive connection cutting step and a metal interconnection step; by introducing the step of resistive connection and disconnection in the construction process, the resistance caused by the polysilicon can be removed, the symmetry of the circuit is improved, and the read current mismatching caused by the polysilicon series resistor is avoided.
Description
Technical Field
The invention belongs to the technical field of microelectronics, and particularly relates to a construction method, a device, a storage medium and related intelligent equipment of a dual-port DP (double port) static Random Access memory (DP-SRAM).
Background
The dual-port SRAM has special word lines and bit lines, so that the read-write speed is greatly improved compared with that of a single-port SP (Single Port) SRAM, and more data access can be completed in the same time; however, due to the defects of the design of the existing structure, the DP-SRAM has the technical problem of unmatched reading speed, and the overall performance of the DP-SRAM is further influenced. For example, in the existing design structure shown in fig. 3, the current mismatch may reach more than 30%, and it is necessary to develop a new solution for such a system to suppress the occurrence of this phenomenon.
Disclosure of Invention
The embodiment of the invention discloses an SRAM construction method which comprises a transmission tube construction step, a resistive connection cutting step and a metal interconnection step.
Wherein, the transmission tube constructing step constructs the transmission tube structure of the double-port SRAM; the transmission tube structure of the dual-port SRAM comprises an 8 transmission tube structure; the dual-port SRAM also comprises bit lines and word lines for facilitating data reading;
constructing a cutting structure in the resistive connection cutting step; the cutting structure comprises a first cutting structure and a second cutting structure; wherein the first cut-off structure separates the resistive connection between the fifth pass tube PGB1 and the sixth pass tube PGA2, and the second cut-off structure separates the resistive connection between the first pass tube PGB2 and the second pass tube PGA 1;
meanwhile, the first disconnection structure disconnects the resistive connection of the second node N2 and the sixth pass transistor PGA2, and the second disconnection structure disconnects the resistive connection of the first node N1 and the second pass transistor PGA 1.
The first node N1 and the sixth transmission pipe PGA2 are communicated in the metal interconnection step; meanwhile, the second node N2 is communicated with a second transmission pipe; metal connections are used in the metal interconnect step to replace resistive connections provided by non-metals or semiconductors and ultimately form SRAM structures or devices.
Further, the resistive connection between fifth pass transistor PGB1 and sixth pass transistor PGA2 is made by polysilicon material before disconnection.
Similarly, the resistive connection between the first pass tube PGB2 and the second pass tube PGA1 is made of polysilicon material before disconnection.
The first node N1 and the sixth pass tube (216) PGA2 are interconnected by metal instead of resistive connection provided by non-metal or semiconductor;
the second node N2 and the second pass tube PGA1 are interconnected by metal instead of resistive connection provided by non-metal or semiconductor.
Further, the resistive connection provided by the non-metal or the semiconductor is realized by polysilicon.
In addition, the metal is copper metal.
Further, the active area AA structure of the SRAM is the same before and after the resistive connection cut-off step is performed; the only difference is that the metal interconnect replaces the original resistive connection.
The SRAM device adopting the structure comprises a double-port transmission tube structure; wherein the dual-port structure comprises an 8-transmission tube structure; the dual port SRAM further includes bit lines and word lines.
Further, the device includes a cut-off structure; the cutting structure comprises a first cutting structure and a second cutting structure; wherein the first cut-off structure separates the resistive connection between the fifth pass tube PGB1 and the sixth pass tube PGA2, and the second cut-off structure separates the resistive connection between the first pass tube PGB2 and the second pass tube PGA 1;
meanwhile, the first disconnection structure disconnects the resistive connection of the second node N2 and the sixth pass transistor PGA2, and the second disconnection structure disconnects the resistive connection of the first node N1 and the second pass transistor PGA 1.
The device also includes a metal interconnect structure; the first node N1 and the sixth transmission pipe PGA2 are connected by a metal material; the second node N2 and the second transmission pipe are also connected by a metal material.
The resistive connection between fifth pass cell PGB1 and sixth pass cell PGA2 is made of polysilicon material before it is disconnected.
The resistive connection between the first pass tube PGB2 and the second pass tube PGA1 is made of polysilicon material before disconnection.
Instead of resistive connections provided by non-metals or semiconductors, metal interconnects are used between the first node N1 and the sixth pass tube PGA 2.
Instead of providing a resistive connection with a non-metal or semiconductor, a metal interconnection is used between the second node N2 and the second pass tube PGA 1.
The resistive connection provided by the nonmetal or semiconductor is realized by polysilicon; after the characteristic dimension reaches a certain degree, the metal is copper metal.
The storage medium body for storing the computer program can realize corresponding functions when being executed by the microprocessor.
The intelligent device may comprise any one of the above devices and may also comprise the above storage medium; the structural design disclosed by the invention has the core that by changing the connection structure, the NPGA can be directly conducted through metal instead of serially connected polysilicon resistors, so that the serially connected resistors can be greatly reduced, and the read current mismatching caused by serially connected polysilicon resistors is avoided.
The method and the device disclosed by the embodiment of the invention overcome the structural design defect of the read current mismatching of the dual-port SRAM, and avoid the phenomenon of unmatched read operation caused by serially connecting polysilicon resistors by changing the structural design of the DP-SRAM unit of the 8 transmission tube.
It should be noted that the terms "first", "second", and the like are used herein only for describing the components in the technical solution, and do not constitute a limitation on the technical solution, and are not understood as an indication or suggestion of the importance of the corresponding component; an element in the similar language "first", "second", etc. means that in the corresponding embodiment, the element includes at least one.
Drawings
To more clearly illustrate the technical solutions of the present invention and to facilitate further understanding of the technical effects, technical features and objects of the present invention, the present invention will be described in detail with reference to the accompanying drawings, which form an essential part of the specification, and which are used together with the embodiments of the present invention to illustrate the technical solutions of the present invention, but do not limit the present invention.
Like reference symbols in the various drawings indicate like elements,
specifically, the method comprises the following steps:
FIG. 1 is a schematic diagram of a dual-port SRAM structure in the prior art;
FIG. 2 is a diagram of a dual-port SRAM circuit in the prior art;
FIG. 3 is a diagram illustrating the read current mismatch of a dual-port SRAM in the prior art;
FIG. 4 is a diagram of a dual-port SRAM layout structure according to an embodiment of the present invention;
FIG. 5 is a schematic circuit diagram of a dual port SRAM in accordance with an embodiment of the present invention;
FIG. 6 is a flow chart of an embodiment of the method of the present invention.
Wherein:
10-the step immediately before the step of,
11-a transfer tube construction step in which,
22-a resistive connection cut-off step,
33-a step of metal interconnection,
40-tightening;
55-a layer of a metal,
the region 66-AA of the molecule,
77-a cutting-off structure for cutting off the fiber,
88-a contact zone of the contact material,
99-a polysilicon (interconnect) layer;
101-double-port layout structure in background art;
102-two-port circuit configuration of the background art;
asymmetry related data of the read current between 111-bit lines;
211-first transmission pipe PGB2,
212-a second transfer tube PGA1,
213-third transfer (pull-up) tube,
214-fourth transfer (pull-up) tube,
215-fifth transfer pipe PGB1,
216-sixth transfer tube PGA2,
217-seventh transfer (pull-down) pipe,
218-an eighth transfer (pull down) tube;
333-read current asymmetry table;
401-first node (N1),
402-second node (N2);
411-the power supply Vdd-the power supply,
412-supply Vss;
601-a first word line of a word line,
602-a second word line;
701-a first bit line,
702-a second bit line, the second bit line,
703-a third bit line, the third bit line,
704-a fourth bit line;
771-a first cutting structure for cutting the first cutting structure,
772-a second cleavage structure;
881 first asymmetric resistance in the background art,
882-second asymmetric resistance in background art.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples. Of course, the following specific examples are provided only for explaining the technical solutions of the present invention, and are not intended to limit the present invention. In addition, the portions shown in the embodiments or the drawings are only illustrations of the relevant portions of the present invention, and are not all of the present invention.
The method for constructing the SRAM shown in FIG. 6 comprises a transmission tube constructing step 11, a resistive connection cutting step 22 and a metal interconnection step 33.
As shown in fig. 4 and 5, the pass-tube constructing step 11 constructs pass- tube structures 201 and 202 of the dual-port SRAM; the transmission tube structures 201 and 202 of the dual-port SRAM comprise 8 transmission tube structures 211, 212, 213, 214, 215, 216, 217 and 218; the dual port SRAM further includes bit lines 701, 702, 703, 704 and word lines 601, 602;
constructing severing structures 771, 772 at the resistive connection severing step 22; the severing structures 771, 772 include a first severing structure 771 and a second severing structure 772.
The first cut-off structure 771 separates the resistive connection between the fifth pass transistor 215 (PGB 1) and the sixth pass transistor 216 (PGA 2), and the second cut-off structure 772 separates the resistive connection between the first pass transistor 211 (PGB 2) and the second pass transistor 212 (PGA 1).
At the same time, the first disconnect structure disconnects the resistive connection between the second node 402 (N2) and the sixth pass transistor 216 (PGA 2), and the second disconnect structure disconnects the resistive connection between the first node 401 (N1) and the second pass transistor 212 (PGA 1).
In the metal interconnection step 33, the first node 401 (N1) is communicated with the sixth transfer tube 216 (PGA 2); and also communicates the second node 402 (N2) with the second transfer tube 212; the metal interconnect step 33 replaces the resistive connections provided by the non-metal or semiconductor with metal connections and ultimately forms an SRAM structure or device.
Further, the resistive connection between fifth pass transistor 215 (PGB 1) and sixth pass transistor 216 (PGA 2) is made by polysilicon material before disconnection.
The resistive connection between the first transfer tube 211 (PGB 2) and the second transfer tube 212 (PGA 1) is made of polysilicon material before disconnection.
Further, instead of the resistive connection provided by the non-metal or semiconductor, the interconnection between the first node 401 (N1) and the sixth pass tube 216 (PGA 2) is made by metal.
Further, instead of the resistive connection provided by the non-metal or semiconductor, metal interconnects are used between the second node 402 (N2) and the second pass tube 212 (PGA 1).
Further, the resistive connection provided by the non-metal or semiconductor is realized by polysilicon.
Further, copper metal is used as the interconnect dielectric.
Further, the active area AA structure of the SRAM is the same before and after the resistive connection cut-off step 22 is performed; the only difference is that the metal interconnect replaces the original resistive connection.
For the SRAM device comprising the structures shown in FIG. 4 and FIG. 5, a two-port transmission tube structure 201, 202 is included; wherein, the dual- port structures 201 and 202 comprise 8 transmission tube 211, 212, 213, 214, 215, 216, 217 and 218 structures; the dual port SRAM also includes bit lines 701, 702, 703, 704 and word lines 601, 602.
Further, a severing structure 771, 772, i.e. a first severing structure 771 and a second severing structure 772; the first cut-off structure 771 separates the resistive connection between the fifth pass transistor 215 (PGB 1) and the sixth pass transistor 216 (PGA 2), and the second cut-off structure 772 separates the resistive connection between the first pass transistor 211 (PGB 2) and the second pass transistor 212 (PGA 1).
At the same time, the first disconnect structure disconnects the resistive connection between the second node 402 (N2) and the sixth pass transistor 216 (PGA 2), and the second disconnect structure disconnects the resistive connection between the first node 401 (N1) and the second pass transistor 212 (PGA 1).
Furthermore, a metal interconnection structure can be included; wherein, the first node 401 (N1) and the sixth transfer pipe 216 (PGA 2) are connected by a metal material; the second node (N2) and the second transfer tube 212 are also connected by a metallic material.
Further, the resistive connection between fifth pass transistor 215 (PGB 1) and sixth pass transistor 216 (PGA 2) is made of polysilicon material before it is disconnected.
Further, the resistive connection between first transfer tube 211 (PGB 2) and second transfer tube 212 (PGA 1) is made of polysilicon material before disconnection.
Further, instead of the resistive connection provided by the non-metal or semiconductor, the interconnection between the first node 401 (N1) and the sixth pass tube 216 (PGA 2) is made by metal.
Further, instead of the resistive connection provided by the non-metal or semiconductor, metal interconnects are used between the second node 402 (N2) and the second pass tube 212 (PGA 1).
Further, the resistive connection provided by the non-metal or semiconductor is realized by polysilicon.
Further, the metal of the interconnect shown in fig. 4 is copper metal.
The computer storage medium and the intelligent device are similar in structure and are not described in detail herein.
As shown in fig. 4. The definition of the different pass tubes and WLs in the new architecture will be different in order to keep up with the model represented by the circuit diagram.
The embodiment of the invention firstly separates the polysilicon Poly of PGB1 and PGA2, PGB2 and PGA1 by polysilicon cutting, and simultaneously disconnects N2 and PGA2, and disconnects N1 and PGA 1.
Further, as shown in fig. 5, the connection between N1 and PGB1 is the same as the original structure, but the connection to PGA2 is made by changing the connection between M1 and CT so that they are directly connected through metal instead of the previous connection to polysilicon, and similarly, the connection between N2 and PGA1 is designed as such.
As reflected in circuit diagram 5, the pre-existing polysilicon series resistance can be removed, and the BL and BLB read current mismatch due to resistance can be resolved. The embodiment of the invention does not change the structures of the original AA and PO, is realized only by changing the connection method of POC and CT/M1, and is simple and convenient.
The core of the structural design disclosed by the embodiment of the invention is that the resistance effect of the polysilicon is avoided by changing the connection structure, and the series resistance shown in figure 2 in the prior art can be greatly reduced, so that the read current mismatching caused by the series connection of polysilicon resistors is avoided.
It should be noted that the above examples are only for clearly illustrating the technical solutions of the present invention, and those skilled in the art will understand that the embodiments of the present invention are not limited to the above contents, and obvious changes, substitutions or replacements can be made based on the above contents without departing from the scope covered by the technical solutions of the present invention; other embodiments will fall within the scope of the invention without departing from the inventive concept.
Claims (14)
1. An SRAM construction method, comprising:
a transmission pipe constructing step (11), a resistive connection cutting step (22) and a metal interconnection step (33);
the transmission tube constructing step (11) constructs transmission tube structures (201, 202) of a double-port SRAM; wherein, the transmission tube structure (201, 202) of the dual-port SRAM comprises an 8 transmission tube (211, 212, 213, 214, 215, 216, 217, 218) structure; the dual-port SRAM further comprises bit lines (701, 702, 703, 704) and word lines (601, 602);
the resistive connection cut-off step (22) constructs cut-off structures (771, 772); the severing structure (771, 772) comprising a first severing structure (771) and a second severing structure (772); wherein said first cut-off structure (771) disconnects the resistive connection between the PGB1 of the fifth pass transistor (215) and the PGA2 of the sixth pass transistor (216), and said second cut-off structure (772) disconnects the resistive connection between the PGB2 of the first pass transistor (211) and the PGA1 of the second pass transistor (212);
simultaneously, the first disconnecting structure disconnects the resistive connection of the second node (402) N2 to the sixth pass tube (216) PGA2, and the second disconnecting structure disconnects the resistive connection of the first node (401) N1 to the second pass tube (212) PGA 1;
the metal interconnection step (33) communicating the first node (401) N1 with the sixth transfer tube (216) PGA 2; simultaneously communicating the second node (402) N2 with the second transfer tube (212); the metal interconnect step (33) replaces the resistive connections provided by the non-metal or semiconductor with metal connections and ultimately forms an SRAM structure or device.
2. The method of claim 1, wherein:
the resistive connection between the fifth pass tube (215) PGB1 and the sixth pass tube (216) PGA2 is made by polysilicon material before disconnection;
the resistive connection between the first transfer tube (211) PGB2 and the second transfer tube (212) PGA1 is made of polysilicon material before disconnection.
3. The method of claim 1, wherein:
the first node (401) N1 and the sixth pass tube (216) PGA2 are interconnected by metal instead of resistive connection provided by non-metal or semiconductor;
instead of providing a resistive connection with a non-metal or semiconductor, metal interconnects are used between the second node (402) N2 and the second pass tube (212) PGA 1.
4. The method of claim 3, wherein:
the resistive connection provided by the non-metal or the semiconductor is realized by polysilicon.
5. The method of claim 3, wherein:
the metal is copper metal.
6. The method of any of claims 1-5, wherein:
the active area AA structure of the SRAM is the same before and after the resistive connection cut-off step (22) is performed; the only difference is that the metal interconnect replaces the original resistive connection.
7. An SRAM device, comprising:
a two-port transfer tube structure (201, 202); wherein the dual-port structure (201, 202) comprises an 8 transmission tube (211, 212, 213, 214, 215, 216, 217, 218) structure; the dual-port SRAM further comprises bit lines (701, 702, 703, 704) and word lines (601, 602);
also comprises a cut-off structure (771, 772); the severing structure (771, 772) comprising a first severing structure (771) and a second severing structure (772); wherein said first cut-off structure (771) disconnects the resistive connection between the PGB1 of the fifth pass transistor (215) and the PGA2 of the sixth pass transistor (216), and said second cut-off structure (772) disconnects the resistive connection between the PGB2 of the first pass transistor (211) and the PGA1 of the second pass transistor (212);
simultaneously, the first disconnecting structure disconnects the resistive connection of the second node (402) N2 to the sixth pass tube (216) PGA2, and the second disconnecting structure disconnects the resistive connection of the first node (401) N1 to the second pass tube (212) PGA 1;
also includes a metal interconnection structure; wherein the first node (401) N1 and the sixth transmission pipe (216) PGA2 are connected by a metal material; the second node (402) N2 and the second transmission pipe (212) are also connected by a metal material.
8. The device of claim 7, wherein:
the resistive connection between the fifth pass tube (215) PGB1 and the sixth pass tube (216) PGA2 is made of polysilicon material before disconnection;
the resistive connection between the first transfer tube (211) PGB2 and the second transfer tube (212) PGA1 is made of polysilicon material before disconnection.
9. The device of claim 8 or 7, wherein:
the first node (401) N1 and the sixth pass tube (216) PGA2 are interconnected by metal instead of resistive connection provided by non-metal or semiconductor;
instead of providing a resistive connection with a non-metal or semiconductor, metal interconnects are used between the second node (402) N2 and the second pass tube (212) PGA 1.
10. The device of claim 8 or 7, wherein:
the resistive connection provided by the non-metal or the semiconductor is realized by polysilicon.
11. The device of claim 8 or 7, wherein:
the metal is copper metal.
12. A computer storage medium, comprising:
a storage medium body for storing a computer program;
the computer program, when executed by a microprocessor, implements the method of any of claims 1-6.
13. The storage medium of claim 12, wherein:
the storage medium body comprising a device according to any of claims 7-11.
14. A smart device, comprising:
the device of any of claims 7-11;
and/or a storage medium according to claim 12 or 13.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101246888A (en) * | 2007-02-15 | 2008-08-20 | 台湾积体电路制造股份有限公司 | Integrated circuit, dual port sram cell and semiconductor structure |
| US20120086082A1 (en) * | 2010-10-07 | 2012-04-12 | Pierre Malinge | Dual port static random access memory cell layout |
| US20130170275A1 (en) * | 2011-12-30 | 2013-07-04 | Stmicroelectronics Pvt. Ltd. | Dual port sram having reduced cell size and rectangular shape |
| CN104183268A (en) * | 2013-05-21 | 2014-12-03 | 中芯国际集成电路制造(上海)有限公司 | Static random access memory structure |
| US20210366537A1 (en) * | 2020-05-25 | 2021-11-25 | Shanghai Huali Integrated Circuit Corporation | 8T Dual Port SRAM and a Manufacturing Method Thereof |
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2021
- 2021-12-14 CN CN202111519774.1A patent/CN114300011A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101246888A (en) * | 2007-02-15 | 2008-08-20 | 台湾积体电路制造股份有限公司 | Integrated circuit, dual port sram cell and semiconductor structure |
| US20120086082A1 (en) * | 2010-10-07 | 2012-04-12 | Pierre Malinge | Dual port static random access memory cell layout |
| US20130170275A1 (en) * | 2011-12-30 | 2013-07-04 | Stmicroelectronics Pvt. Ltd. | Dual port sram having reduced cell size and rectangular shape |
| CN104183268A (en) * | 2013-05-21 | 2014-12-03 | 中芯国际集成电路制造(上海)有限公司 | Static random access memory structure |
| US20210366537A1 (en) * | 2020-05-25 | 2021-11-25 | Shanghai Huali Integrated Circuit Corporation | 8T Dual Port SRAM and a Manufacturing Method Thereof |
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