CN114299820B - Array substrate and display panel - Google Patents
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- CN114299820B CN114299820B CN202111642253.5A CN202111642253A CN114299820B CN 114299820 B CN114299820 B CN 114299820B CN 202111642253 A CN202111642253 A CN 202111642253A CN 114299820 B CN114299820 B CN 114299820B
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- 239000000758 substrate Substances 0.000 title claims abstract description 130
- 238000000034 method Methods 0.000 claims abstract description 10
- 239000002184 metal Substances 0.000 claims description 13
- 239000004020 conductor Substances 0.000 claims description 7
- 230000000694 effects Effects 0.000 abstract description 10
- 239000011295 pitch Substances 0.000 description 35
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- 230000009286 beneficial effect Effects 0.000 description 2
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Abstract
The application discloses an array substrate and a display panel, wherein the array substrate comprises a substrate, and a plurality of pixel circuit units which are arranged in an array and are positioned on one side of the substrate; the orthographic projection areas of the pixel circuit units on the substrate are the same, the length of orthographic projection of the pixel circuit units is smaller than 61 micrometers, and the width of orthographic projection of the pixel circuit units is smaller than 61 micrometers; a plurality of pixel circuit units which are arranged in an array form a pixel circuit group, and the plurality of pixel circuit groups are arranged in an array; the distance between the front projections of the adjacent pixel circuit units in each pixel circuit group on the substrate is smaller than the distance between the front projections of the adjacent pixel circuit groups on the substrate. According to the pixel circuit unit arrangement method and device, under the condition that the pixel circuit units are tightly arranged, arrangement periods of a plurality of pixel circuit groups in a display area are guaranteed to be identical, so that space is effectively compressed, and the moire effect is avoided.
Description
Technical Field
The application relates to the technical field of display, in particular to an array substrate and a display panel.
Background
In the prior art, in order to achieve a narrow frame, a portion of the pixel circuit area is typically compressed, thereby achieving a narrow frame effect.
However, this compression method may cause the pixel circuit size of the compression area to be smaller than that of the normal area, and the pixel circuit size is different, so that moire is easily generated, resulting in Mura (uneven display) and further affecting the display screen effect.
Disclosure of Invention
The technical problem that this application mainly solves is to provide an array substrate and display panel, through the size of each pixel circuit unit of compression to adjust the interval between the inside pixel circuit unit of pixel circuit group and the interval between the adjacent pixel circuit group, can solve the problem that the narrow frame produced mole line easily among the prior art of realization.
In order to solve the technical problems, a first technical scheme adopted by the application is to provide an array substrate, wherein the array substrate comprises a substrate and a plurality of pixel circuit units arranged in an array and positioned at one side of the substrate; the orthographic projection areas of the pixel circuit units on the substrate are the same, the length of orthographic projection of the pixel circuit units is smaller than 61 micrometers, and the width of orthographic projection of the pixel circuit units is smaller than 61 micrometers; a plurality of pixel circuit units which are arranged in an array form a pixel circuit group, and the plurality of pixel circuit groups are arranged in an array; the distance between the front projections of the adjacent pixel circuit units in each pixel circuit group on the substrate is smaller than the distance between the front projections of the adjacent pixel circuit groups on the substrate.
The distance between the orthographic projections of adjacent pixel circuit units in each pixel circuit group on the substrate along the first direction is smaller than the distance between the orthographic projections of each adjacent pixel circuit group on the substrate along the first direction; and/or the spacing of the orthographic projections of the adjacent pixel circuit units in each pixel circuit group on the substrate along the second direction is smaller than the spacing of the orthographic projections of the adjacent pixel circuit groups on the substrate along the second direction; wherein the first direction is a row direction and the second direction is a column direction.
Wherein, each pixel circuit group is distributed at equal intervals.
Wherein the length of the orthographic projection of the single pixel circuit unit is 51 micrometers, and the width is 51 micrometers.
The array substrate further comprises virtual wires, and orthographic projections of the virtual wires on the substrate are located between orthographic projections of each adjacent pixel circuit group on the substrate.
The orthographic projection of the virtual wire on the substrate extends along a second direction; and/or, the orthographic projection of the virtual wire on the substrate extends along the first direction.
And the distance between the orthographic projection of each pixel circuit group on the substrate and the orthographic projection of the virtual wire on the substrate is equal to the distance between the orthographic projections of the adjacent pixel circuit units in each pixel circuit group on the substrate.
The space between the orthographic projection of the pixel circuit groups on the substrate and the orthographic projection of the nearest virtual wire on the substrate is equal to the space between the orthographic projections of the adjacent pixel circuit units in the pixel circuit groups on the substrate; the distance between the orthographic projections of the adjacent virtual wires on the substrate is equal to the distance between the orthographic projections of the adjacent pixel circuit units in each pixel circuit group on the substrate.
The array substrate comprises a plurality of layers of film layers which are arranged on a substrate in a laminated mode, and the virtual wire is arranged on at least one layer of film layer in the plurality of layers of film layers and/or is arranged between any two adjacent film layers.
Wherein the multilayer film layer comprises a plurality of metal layers; the virtual wire and at least one metal layer in the multiple metal layers are arranged in the same layer; preferably, the multi-layered metal layer includes a first electrode layer including a plurality of first electrodes, each first electrode being electrically connected to each pixel circuit unit, and the dummy conductive line being located between the first electrodes.
The beneficial effects of this application are: compared with the prior art, the array substrate and the display panel are provided, the size of each pixel circuit unit is compressed by keeping the orthographic projection areas of all the pixel circuits on the substrate to be the same, and the orthographic projection distance of the adjacent pixel circuit units in each pixel circuit group on the substrate is smaller than the orthographic projection distance of each adjacent pixel circuit group on the substrate, so that the arrangement period of a plurality of pixel circuit groups in a display area is ensured to be the same under the condition that the pixel circuit units are closely arranged, and the space is effectively compressed to avoid moire effect.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a top view of a first embodiment of an array substrate according to an embodiment of the present application;
FIG. 2 is a top view of a second embodiment of an array substrate according to an embodiment of the present disclosure;
FIG. 3 is a top view of a third embodiment of an array substrate according to an embodiment of the present disclosure;
fig. 4 is a top view of a fourth embodiment of an array substrate according to an embodiment of the present application.
Detailed Description
The following description of the embodiments of the present application will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all, of the embodiments of the present application. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present disclosure.
The terminology used in the embodiments of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in this application and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise, the "plurality" generally includes at least two, but does not exclude the case of at least one.
It should be understood that the term "and/or" as used herein is merely one relationship describing the association of the associated objects, meaning that there may be three relationships, e.g., a and/or B, may represent: a exists alone, A and B exist together, and B exists alone. In addition, the character "/" herein generally indicates that the front and rear associated objects are an "or" relationship.
It should be understood that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising … …" does not exclude the presence of other like elements in a process, method, article or apparatus that comprises the element.
Referring to fig. 1, fig. 1 is a top view of a first embodiment of an array substrate according to an embodiment of the present application.
As shown in fig. 1, the array substrate 100 includes a base (not shown), and a pixel circuit region 110 disposed on one side of the base, wherein the pixel circuit region 110 includes a plurality of pixel circuit units 112 arranged in an array. The front projection area of each pixel circuit unit 112 on the substrate is the same, and the length of the front projection of the pixel circuit unit 112 is less than 61 micrometers, and the width is less than 61 micrometers. The plurality of pixel circuit units 112 arranged in an array form one pixel circuit group 111, and the plurality of pixel circuit groups 111 are arranged in an array. The pitch of the orthographic projection of the adjacent pixel circuit units 112 in each pixel circuit group 111 on the substrate is smaller than the pitch of the orthographic projection of each adjacent pixel circuit group 111 on the substrate.
Specifically, the size of the orthographic projection of the standard circuit on the substrate is generally 61 micrometers in length and 61 micrometers in width, and by compressing the size of each pixel circuit unit 112 to make the length and width smaller than 61 micrometers, the pixel circuit area can be compressed without affecting the display, thereby realizing a narrow frame design.
In a preferred embodiment, the size of the orthographic projection of each pixel circuit unit 112 on the substrate may be compressed to a length of 51 microns and a width of 51 microns. It can be appreciated that the size of the pixel circuit unit 112 is compressed to have a length and width of 51 micrometers, so that the distribution area of the pixel circuit unit 112 can be greatly reduced, thereby optimizing the narrow frame design.
Specifically, the maximum compressible area of each pixel circuit unit 112 is 70% of the standard circuit area, that is, the length and width of each pixel circuit unit 112 can be adjusted within 51-61 micrometers, and in other embodiments, the length and width of the front projection of each pixel circuit unit 112 on the substrate can be set to any value (excluding the end point value) within 51-61 micrometers, which is not limited in this application.
It will be appreciated that since the orthographic projection areas of all the pixel circuit units 112 on the substrate in the display area are the same, uniformity among the pixel circuit units 112 is maintained, and display differences caused by different sizes of the pixel circuit units 112 in different areas are avoided.
Each pixel circuit unit 112 corresponds to one first electrode, if only each pixel circuit unit 112 is compressed, but not grouped, the area of the pixel circuit area 110 formed by all the pixel circuit units 112 will be greatly smaller than the area of the first electrode layer 130, and the connection lines of the plurality of pixel circuit units 112 and the plurality of first electrodes will cross, which is not beneficial to wiring. Meanwhile, in order to further compress the pixel circuit region 110, the pitch of the pixel circuit units 112 inside each pixel circuit group 111 is compressed.
In this embodiment, the pitch of the orthographic projection of the adjacent pixel circuit units 112 on the substrate in each pixel circuit group 111 along the first direction is smaller than the pitch of the orthographic projection of each adjacent pixel circuit group 111 on the substrate along the first direction. Wherein the first direction is a row direction and the second direction is a column direction.
Specifically, the array substrate 100 includes a plurality of scan lines 122 disposed in parallel and a plurality of data lines 121 disposed in parallel, and the data lines 121 are disposed perpendicular to the scan lines 122. In this embodiment, the array substrate 100 further includes a horizontal enable signal trace (not shown) and a vertical working voltage trace (not shown), where the arrangement periods of the scan line 122, the enable signal trace, the data line 121 and the working voltage trace are the same and are distributed in a grid shape.
The row direction is the extending direction of the scan lines 122, and the column direction is the extending direction of the data lines 121.
In another embodiment, a pitch of an orthographic projection of adjacent pixel circuit units on the substrate in the second direction in each pixel circuit group is smaller than a pitch of an orthographic projection of each adjacent pixel circuit group on the substrate in the second direction. For example, referring to fig. 2, fig. 2 is a top view of a second embodiment of an array substrate according to an embodiment of the present application. As shown in fig. 2, the pitch of the orthographic projection of the adjacent pixel circuit units 112 on the substrate in each pixel circuit group 111 in the array substrate 100 is smaller than the pitch of the orthographic projection of each adjacent pixel circuit group on the substrate in the second direction.
In yet another embodiment, a pitch of the orthographic projection of the adjacent pixel circuit units on the substrate in the each pixel circuit group along the first direction is smaller than a pitch of the orthographic projection of the adjacent pixel circuit groups on the substrate along the first direction, and a pitch of the orthographic projection of the adjacent pixel circuit units on the substrate in the each pixel circuit group along the second direction is smaller than a pitch of the orthographic projection of the adjacent pixel circuit groups on the substrate along the second direction. Specifically, referring to fig. 3 and fig. 4, fig. 3 is a top view of a third embodiment of an array substrate according to an embodiment of the present application, and fig. 4 is a top view of a fourth embodiment of an array substrate according to an embodiment of the present application.
As shown in fig. 3 and fig. 4, the pitch of the orthographic projection of the adjacent pixel circuit units 112 on the substrate in each pixel circuit group 111 in the array substrate 100 is smaller than the pitch of the orthographic projection of each adjacent pixel circuit group 111 on the substrate in the first direction, and at the same time, the pitch of the orthographic projection of the adjacent pixel circuit units 112 on the substrate in each pixel circuit group 111 in the second direction is smaller than the pitch of the orthographic projection of each adjacent pixel circuit group on the substrate in the second direction. In fig. 3, each pixel circuit group 111 includes 9 pixel circuit units 112 in total of 3×3 (3 per row, 3 per column). In fig. 4, each pixel circuit group 111 includes 16 pixel circuit units 112 in total of 4×4 (4 per row, 4 per column).
In the present embodiment, the pixel circuit groups 111 are arranged at equal intervals. Specifically, the pixel circuit groups 111 are arranged at equal intervals in the first direction.
In a specific embodiment, as shown in fig. 1, the pixel circuit groups 111 are arranged at equal intervals along the first direction, and the number of rows in each pixel circuit group 111 is greater than the number of columns, and includes at least two columns of pixel circuit units 112. In another specific embodiment, as shown in fig. 2, the pixel circuit groups 111 are arranged at equal intervals along the second direction, and each pixel circuit group 111 has a larger column number than a row number and includes at least two rows of pixel circuit units 112. In another embodiment, as shown in fig. 3 and fig. 4, the pixel circuit groups 111 are arranged at equal intervals along the first direction and the second direction, and the number of rows is equal to the number of columns. The pitch along the first direction and the pitch along the second direction may be the same or different, which is not limited in the present application.
It can be understood that the equidistant arrangement can make the circuit arrangement period of all the pixel circuit groups 111 in the display area the same, and because the interval between the adjacent pixel circuit units 112 inside the pixel circuit groups 111 is smaller than the interval between the adjacent pixel circuit groups 111 outside, the routing area of the pixel circuit groups 111 can be effectively compressed, so that the pixel circuit units 112 are closely arranged, and the pixel area 110 in the display area is compressed, so as to realize the narrow frame design. Further, in this embodiment, the intervals between the columns and/or rows of the adjacent pixel circuit units 112 in all the regularly arranged pixel circuit groups 111 in the display area are compressed, instead of compressing only the pixel circuit areas on the left and right sides or a certain pixel circuit area, so that the moire effect caused by the fact that the compressed area is only a part of the other non-compressed area and the moire effect caused by the fact that the arrangement periods of the pixel circuit units 112 are different can be avoided, and then the display Mura is avoided, so that the display screen effect is improved.
In the present embodiment, the gate lines 140 are disposed at both sides of the left and right edges of the pixel circuit region 110.
In the prior art, the position of the first electrode layer corresponds to the position of the pixel circuit region, and the gate circuit is generally disposed outside the first electrode layer, but the area of the pixel circuit region 110 is smaller than that of the first anode layer 130 due to the overall compression of the pixel circuit region 110, and a part of regions on the left and right sides of the first anode layer 130 are left, and a part of the gate circuit can be disposed at a portion of the first anode layer 130 which does not correspond to the pixel circuit region 110, so that the narrow frame design is further realized.
Further, the array substrate 100 further includes dummy conductive lines (not shown), and the orthographic projections of the dummy conductive lines on the substrate are located between the orthographic projections of each adjacent pixel circuit group 111 on the substrate.
In this embodiment, the orthographic projection of the dummy conductive line on the substrate extends along the second direction.
Specifically, one or more dummy wires may be disposed between each adjacent pixel circuit group 111 according to the size of the pitch of the orthographic projection of each adjacent pixel circuit group 111 on the substrate.
For example, when the pitch of the front projection of each adjacent row and/or column pixel circuit group 111 on the substrate is equal to twice the pitch of the front projection of the adjacent row and/or column pixel circuit units 112 on the substrate within each adjacent pixel circuit group 111, only one dummy wire may be provided between each adjacent row and/or column pixel circuit group 111, and the front projection of the dummy wire on the substrate is located between the front projections of each adjacent row and/or column pixel circuit group 111 on the substrate, such that the pitch of the front projection of each adjacent row and/or column pixel circuit group 111 on the substrate and the front projection of the dummy wire on the substrate is equal to the pitch of the front projections of the adjacent row and/or column pixel circuit units 112 on the substrate within each pixel circuit group 111.
For another example, when the pitch of the front projection of each adjacent row and/or column pixel circuit group 111 on the substrate is equal to at least three times the pitch of the front projection of each adjacent row and/or column pixel circuit unit 112 on the substrate within each pixel circuit group 111, a plurality of dummy conductors are provided between each adjacent row and/or column pixel circuit group 111, and the pitch between the front projection of the pixel circuit group 111 on the substrate and the front projection of the nearest one dummy conductor on the substrate is equal to the pitch of the front projection of each adjacent row and/or column pixel circuit unit 112 within each pixel circuit group 111 on the substrate. Wherein the pitch of the orthographic projections of adjacent dummy conductors on the substrate is equal to the pitch of the orthographic projections of adjacent row and/or column pixel circuit units 112 within each pixel circuit group 111 on the substrate.
It will be appreciated that the orthographic projection formed by the dummy conductive lines is to form a new pitch between the pixel circuit groups 111 of each adjacent row and/or column, that is, the pitch formed by orthographic projections of each pixel circuit group 111 of each adjacent row and/or column and the dummy conductive lines, when the new pitch is equal to the pitch between the pixel circuit units 112 of each adjacent row and/or column in each pixel circuit group 111, the pitches formed by the pixel circuit units 112 in the pixel circuit group 111 and the pixel circuit units 112 outside the group along the row and/or column directions can be made equal, so that uniformity of circuit density in the whole display area is achieved, influence of crosstalk on the precision and size of the pixel circuit units 112 is avoided, and influence of crosstalk on key signals is avoided, thereby further avoiding moire effect.
In other embodiments, the new spacing between the pixel circuit groups 111 of each adjacent row and/or column may be slightly greater or slightly less than the spacing between the pixel circuit units 112 of adjacent rows and/or columns within each pixel circuit group 111, which is not limited in this application.
In this embodiment, the array substrate 100 includes a plurality of film layers stacked on a base, and the dummy conductive lines are disposed on at least one of the plurality of film layers and/or between any two adjacent film layers.
Wherein the multilayer film layer comprises a plurality of metal layers. The virtual wire and at least one metal layer in the multiple metal layers are arranged in the same layer. Preferably, the multi-layered metal layer includes a first electrode layer 130, the first electrode layer 130 includes a plurality of first electrodes, each first electrode is electrically connected to each pixel circuit unit, and the dummy conductive line is located between the first electrodes. Wherein the first electrode layer 130 is an anode layer.
In particular, when the dummy conductive lines extend only in the first direction or extend only in the second direction, the dummy conductive lines may be disposed on at least one of the plurality of film layers since the dummy conductive lines do not cross each other. When the dummy conductive lines extend in the first direction and the second direction at the same time, in order to avoid crossing of the dummy conductive lines on the same metal film layer, the dummy conductive lines extending in different directions must be disposed on different film layers.
Compared with the prior art, the embodiment is characterized in that the front projection areas of all the pixel circuits on the substrate are kept the same, the size of each pixel circuit unit is compressed, and the front projection distance of the adjacent row and/or column pixel circuit units in each pixel circuit group on the substrate is smaller than the front projection distance of the pixel circuit groups in each adjacent row and/or column on the substrate, so that the arrangement period of a plurality of pixel circuit groups in a display area is ensured to be the same under the condition that the pixel circuit units are closely arranged, and therefore the space is effectively compressed, and the moire effect is avoided. In addition, by arranging the virtual wires between the pixel circuit groups of each adjacent row and/or column, and enabling the interval between the orthographic projections of the adjacent pixel circuit groups and the virtual wires to be equal to the interval between the pixel circuit units in each pixel circuit group, uniformity of circuit density distribution in the whole display area can be achieved, influence of crosstalk on the precision and the size of the pixel circuit units is avoided, influence of the crosstalk on key signals is avoided, and therefore moire effect is further avoided.
The foregoing description is only of embodiments of the present application, and is not intended to limit the scope of the patent application, and all equivalent structures or equivalent processes using the descriptions and the contents of the present application or other related technical fields are included in the scope of the patent application.
Claims (9)
1. An array substrate comprises a substrate, a plurality of pixel circuit units arranged in an array and positioned at one side of the substrate; the method is characterized in that the orthographic projection areas of the pixel circuit units on the substrate are the same, the length of the orthographic projection of the pixel circuit units is smaller than 61 micrometers, and the width of the orthographic projection of the pixel circuit units is smaller than 61 micrometers; a plurality of pixel circuit units which are arranged in an array form a pixel circuit group, and a plurality of pixel circuit groups are arranged in an array; the distance between the orthographic projections of the adjacent pixel circuit units in each pixel circuit group on the substrate is smaller than the distance between the orthographic projections of the adjacent pixel circuit groups on the substrate;
the array substrate further comprises virtual wires, and orthographic projections of the virtual wires on the substrate are located between orthographic projections of each adjacent pixel circuit group on the substrate.
2. The array substrate of claim 1, wherein a pitch of orthographic projections of adjacent pixel circuit units on the substrate in each of the pixel circuit groups along a first direction is smaller than a pitch of orthographic projections of adjacent pixel circuit groups on the substrate along the first direction; and/or the number of the groups of groups,
the distance between the orthographic projections of the adjacent pixel circuit units in each pixel circuit group on the substrate along the second direction is smaller than the distance between the orthographic projections of the adjacent pixel circuit groups on the substrate along the second direction;
wherein the first direction is a row direction and the second direction is a column direction.
3. The array substrate of claim 2, wherein the pixel circuit groups are arranged at equal intervals.
4. The array substrate of any one of claims 1 to 3, wherein the length of the orthographic projection of a single pixel circuit unit is 51 micrometers and the width is 51 micrometers.
5. The array substrate of claim 1, wherein an orthographic projection of the dummy conductive line on the base extends in a second direction; and/or, the orthographic projection of the virtual wire on the substrate extends along a first direction.
6. The array substrate of claim 5, wherein only one dummy conductor is disposed between each adjacent pixel circuit group, such that a distance between an orthographic projection of each pixel circuit group on the substrate and an orthographic projection of the dummy conductor on the substrate is equal to a distance between orthographic projections of adjacent pixel circuit units in each pixel circuit group on the substrate.
7. The array substrate according to claim 5, wherein a plurality of the dummy conductors are provided between each adjacent pixel circuit group, and a distance between an orthographic projection of the pixel circuit group on the substrate and an orthographic projection of one of the dummy conductors closest to the substrate is equal to a distance between orthographic projections of adjacent pixel circuit units in each pixel circuit group on the substrate; the distance between the orthographic projections of the adjacent virtual wires on the substrate is equal to the distance between the orthographic projections of the adjacent pixel circuit units in each pixel circuit group on the substrate.
8. The array substrate according to any one of claims 5 to 7, wherein the array substrate comprises a plurality of film layers stacked on the substrate, and the dummy leads are disposed on at least one of the plurality of film layers and/or between any two adjacent film layers.
9. The array substrate of claim 8, wherein the multi-layer film layer comprises a plurality of metal layers;
the virtual wire and at least one metal layer in the multi-layer metal layers are arranged in the same layer;
the multi-layer metal layer comprises a first electrode layer, the first electrode layer comprises a plurality of first electrodes, each first electrode is electrically connected with each pixel circuit unit, and the virtual wire is located between the first electrodes.
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| CN202111642253.5A CN114299820B (en) | 2021-12-29 | 2021-12-29 | Array substrate and display panel |
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| CN202111642253.5A CN114299820B (en) | 2021-12-29 | 2021-12-29 | Array substrate and display panel |
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